Programmable logic array

A programmable logic array (PLA) is a kind of programmable logic device used to implement combinational logic circuits. The PLA has a set of programmable AND gate planes, which link to a set of programmable OR gate planes, which can then be conditionally complemented to produce an output. It has 2N AND gate s for N input variables and for M outputs from PLA, there should be M OR gates, each with programmable inputs from all of the AND gates. This layout allows for many logic functions to be synthesized in the sum of products canonical forms. The Programmable Logic Array (PLA) has a programmable AND array followed by a programmable OR array. Programmable Logic Array (PLA) circuit is built by using AND gates and OR gates. The 3x 4 bits data can be stored in this circuit. The large storage data bits of PLA circuit store by a using large AND-OR array with lots of inputs and product terms, and programmable connections. Programmable Logic Array circuit functions as ROM circuit.

This paper shows, on the basis of experiments, that execution of conformance tests of programmable logic controllers with minimum-length test sequences built from specifications in FSMs may yield spurious results. A new approach to build test sequences is then proposed to remove, or at least strongly lessen, this issue.

In Brazil, the national Bar exams for legal professionals are called the OAB exams, which indicate aptitude for practice of the law. The logic iALC is an intuitionistic description logic which was created to deal with the world of laws. In this article we convey some experiments on the use of logical deductions as a kind of intermediate data structure to help in the task of explaining "juridicial sentences" on the basis legal systems in "Civil Law" states. The deductions are concretely developed in the iALC description logic for representing legal systems and reasoning inside them. We then discuss what can be extrapolated from that which was found and propose next steps.

Many modern Field Programmable Logic Arrays (FPGAs) use lookup table (LUT) logic blocks which can be programmed to realize any function of a fixed number of inputs. It is possible to employ logic blocks that realize only a subset of all functions, while the rest can be obtained by permuting and negating the inputs. Such blocks, known as Universal Logic Modules (ULMs), have already been considered for application in FPGAs; in this paper, we propose a new class of ULMs which is more useful in the FPGA environment. Methodology for systematic development of such blocks is presented, based on the BDD description of logic functions. We give an explicit construction of a three-input LUT replacement that requires only five programming bits, which is the optimum for such ULMs. A realistic size four-input LUT replacement is obtained which uses 13 programming bits.

The Pulse Code Modulation is the vital part of Analog to Digital Converter (ADC). The PCM includes the process of sampling and quantization in order to digitize the analog input along the time scale and amplitude scale respectively. This project aims to design the Pulse Code Modulation Multiplexer (PCMM) in which analog inputs with different frequencies are multiplexed and pulse code modulated. The PCMM is developed using Very High Speed Integrated Circuit Hardware Description Language (VHDL). The proposed Pulse Code Modulated Multiplexer is validated by comparing the design parameters like power and area, implemented in the Xilinx Spartan Field Programmable Gate Array (FPGA).

In this paper the problem of selecting an appropriate programmable cell structure for FPGA architecture design is addressed. The cells studied here c an be c ongured to the desired functionality by applying input permutation, negation, bridging or constant assignment, or output negation. A general methodology to determine logic description of such cells, which are capable of being congured to a given set of functions is described. Experimental results suggest that the new cell behaves as well as the Actel 2 cell in terms of logic power but requires substantially less area and wiring overhead.

The new family of Field Programmable Gate Arrays, CLI6000 from Concurrent Logic Inc realizes the truly Cellular Logic. It has been mainly designed for the realization of data path architectures. However, introduced by it new universal logic cell calls also for new logic synthesis methods based o n r egularity of connections. In this paper we present two programs, exact and approximate, for the minimization of Permuted R eed-Muller Trees that are obtained b y r epetitive application of Davio expansions (Shannon expansions for EXOR gates) in all possible orders of variables in subtrees. Such trees are p articularly well matched t o b oth the realization of logic cell and connection structure of the CLI6000 device. It is shown on several standard b enchmarks that the heuristic algorithm gives good quality results in much less time than the exact algorithm.

The paper deals with the fault tolerance of finite state machines (FSMs) implemented by nanoelectronic programmable logic arrays (PLAs). The paper studies a fault tolerant nano-PLA structure, which is based on implementing an initial FSM in a form of three interacting dense PLAs. The paper provides experimental benchmarks results for estimation of fault tolerance properties of the proposed solution. The results indicate a high efficiency of the proposed decomposition approach.

A method of a self-checking synchronous Finite State Machine (FSM) network design with low overhead is developed. Checkers are used only for FSMs, which output lines are at the same time output lines of the network. The checkers observe output lines of these FSMs. The method is based on reducing the problem to a self-checking synchronous FSM design. The latter is provided by applying a special description of FSM namely, so-called unate Programmable Logic Array (PLAu) description. Single stuck-at fault on the FSM poles and gate poles are considered. PLAu realization of FSM allows a factorized or multilevel logic synthesis. They both provide a unidirectional manifestation of the above mentioned faults on the output lines of the corresponding FSMs. This realization also gives rise to a transparency of each component FSM of the network for the faults. PLAu realization is derived from the State Transition Graph (STG) description of FSMs with using the m-out-of-n encoding of its states an...

The paper deals with designing finite state machines (FSM) by Nano PLA structures. Due to the devicemissing domination in nano-structures, it is desired to minimize both the area and the number of PLA devices required for the FSM implementation. We propose a solution of the minimization problem. Our solution is based on: a) partition of the FSM for two interacting components; b) transformation of one or two of the component FSMs into a dense form. We show that combining the above techniques provides a significant ...

This paper describes a new detailed routing algorithm, speciffically designed for those types of architecturesthat are found on the most recent generations of Field-Programmable Gate Arrays (FP-GAs). The algorithm, called RAISE, can be applied to a broad range of optimizations problems and has been used for detailed routing of symmetrical FPGAs, whose routing architecture consists of rows and columns of logic cells interconnected by routing channels. RAISE (Router using AadaptIve Simulated Evolution) searches not only for a possible solution, but tries to find the one with minimum delay. Excelent routing results have been obtained over a set of several benchmark circuits getting solutions close to the minimum number of tracks.

We present a new matrix formulation of the face hypercube embedding problem that motivates the design of an efficient search strategy to find an encoding that satisfies all faces of minimum length. Increasing dimensions of the Boolean space are explored; for agiven dimension constraints are satisfied oneatatime. The following features help toreduce the nodes of thesolution space that mustbeexplored: candidate cubes instead than candidate codesare generated, cubes yieldingsymmetric solutions are not generated, asmaller sufficient setof solutions (producing basic sections) isexplored, necessary conditions help discard unsuitable candidate cubes, early detection that apartial solution cannot beextended tobe a global solution prunes infeasible portions of the search tree. We have implemented a prototype package Minsk based on the previous ideas and run experiments toevaluate it. The experiments show that MINSK is faster and solves more problems than any available algorithm. Moreover, MINSK is a robust algorithm, while most of the proposed alternatives are not. Besides most problems of the complete MCNC benchmark suite, other solved examples include an important set of decoder PLAs coming from the design of microprocessor instruction sets. 1 Introduction Consider a set of symbols 5 and an encoding function e : S-+ Bk, for a given k, that assigns to each symbol s € S acode e(s), i.e., abinary vector oflength k. Usually the only requirement isthat eisinjective, i.e., that different symbols are mapped to different binary vectors. Invarious applications it is important to satisfy other encoding constraints, inorder to obtain acode that is correct or desireable to meet a certain objective. The encoding length kmay be part ofthe problem instance or it may be an unknown to be found (usually minimized) by the procedure that satisfies the given encoding constraints [15]. Given aset ofsymbols 5, aface constraint cf isasubset S' C S specifying that the symbols in5' are tobe assigned to one face (or subcube) of abinary fc-dimensional cube, without any other symbol sharing thesame face. Face constraints are generated by multiple-valued (input) literals in two-level and multi-level multi-valued minimization [15]. As an exampe, given symbols a, 6, c, d, e, an input constraint involving symbols a,6,c is denoted by (a,6, c). An encoding satisfying (a, 6, c) is given by a = 111, 6 = 011, c = 001,d = 000ande = 100 and theface spanned by (a, 6, c)is-1. Notice that the vertex 101 is not and should not be assigned to any other symbol. Given a set of face constraints C/, it is always possible tofind an encoding that satisfies it, as long as one is free to choose a suitable code length. It is a well-known fact that for k = | S | any setC/ is satisfied by choosing as e the 1-hot encoding function (which assigns to a state s, the binary vector that isalways 0 except for aposition to1, the latter denoting state «,-). Itisan importantcombinatorial optimizationproblem, sometimes called [16] face hypercube embedding, to find the minimum fc and arelated e : S-> Bk such that Cj is satisfied. The decision version ofthis problem is NP-complete [11]. An exact solution based on a branch-and-bound strategy to search the partially ordered set of faces of hypercubes was described first in [16], but it is not computationally practical. An exact solution by reduction tothe problem ofsatisfaction ofencoding dichotomies! was proposed in [17]. Ituses a reduction 'An encoding dichotomy on S is a bipartition (S\, Si) such that S\ US2 C 5.

Field programmable gate arrays (FPGA 's) reduce the turnaround time of application-spec@c integrated circuits from weeks to minutes. However, the high complexity of their architectures makes manual mapping of designs time consuming and error prone thereby offsetting any turnaround advantage. Consequently, effective design automation tools are needed to reduce design time. Among the most important is logic synthesis. While standard synthesis techniques could be used for FPGA's, the quality of the synthesized designs is often unacceptable. As a result, much recent work has been devoted to developing logic synthesis tools targeted to different FPGA architectures. The paper surveys this work. The three most popular types of FPGA architectures are considered, namely those using logic blocks based on lookuptables, multiplexers and wide AND/OR arrays. The emphasis is on tools which attempt to minimize the area of the combinational logic part of a design since little work has been done on optimizing performance or routability, or on synthesis of the sequential part of a design. The different tools surveyed are compared using a suite of benchmark designs.

This paper is concerned with the design of optical and optoelectronic circuits. In particular new designs for an exclusive-OR circuit, set-reset trigger flip-flop, and a programmable logic array (PLA) are proposed. The PLA utilizes optical properties and performs computation on binary images using optical parallel logic devices, lenses, etc. This work is then extended to the design of erasable programmable logic devices.

This work aims to present the most relevant results derived from the development of a novel FPGA matrix. Nevertheless its capacity, its highlights are low cost and its ability to deal with high frequencies. This prototype matrix, named FLECHA, presents some structural novelties, as a different approach to perform the interconnections between logic cells and I/O Pads and an internal controller. One of the major contributions of this work deals with the strategy of placing the logic cells in rows, allowing a drastic reduction of the number of switches without reducing interconnection capacity between logic cells and I/O Pads. Following this principle, a new matrix presenting 600 equivalent gates was constructed including 40 logic cells and 40 programmable I/O Pads. The FLECHA matrix is intended to implement simple logic functions as for fast "glue logic" between processors and memories, reaching an operational frequency of 145 MHz.

The challenge of extending Moore's Law past the physical limits of the present semiconductor technology calls for novel innovations. Several novel nanotechnologies are being proposed as an alternative to their CMOS counterparts, with nanowire crossbar being one of the most promising paradigms. Quite recently, a new promising clock-free architecture, called the Asynchronous Crossbar Architecture has been proposed to enhance the manufacturability and to improve the robustness of digital circuits by removing various timing related failure modes. Even though the proposed clock-free architecture offers several merits, it is not free from the high defect rates induced due to nondeterministic nanoscale assembly. In this work, a unique Functional Test Algorithm (FTA) has been proposed and validated to test for manufacturing defects in this architecture. The proposed Functional Test Algorithm is aimed at reducing the testing overhead in terms of the time and space complexity associated with the existing sequential test scheme. In addition, it is designed to provide high fault coverage and excellent fault-tolerance via post-reconfiguration. This test scheme can be effectively used to assure true functionality of any threshold gate realized on a given PGMB. The main motivation behind this research is to propose a comprehensive test scheme which can achieve sufficiently high test coverage with acceptable test overhead. This test algorithm is a significant effort towards viable nanoscale computation. This work has been organized into three papers, explaining the proposed algorithm, demonstrating its working, describing the achievable replacement schemes using the proposed tool and providing a performance evaluation metric specifically proposed to evaluate the functional test algorithm. v ACKNOWLEDGEMENTS First and foremost, I would like to thank Almighty God for providing me with all the good health, strength and knowledge to complete my thesis and masters. I would like to express sincere gratitude and heartfelt thanks to my advisor Dr. Minsu Choi for his guidance, encouragement and invaluable contributions throughout my graduate study as well as in completing this research. I would also like to thank him for providing me with financial support during my master's study. To my committee members, Dr. Sahra Sedigh and Dr. Theodore McCracken, I extend my deepest appreciation and thanks for their time and effort in serving as committee members and reviewing this dissertation. My sincere thanks to Dr. V A Samaranayake of Mathematics and Statistics department for his important inputs. Special thanks to Ravi Bonam and Shikha Chaudhary, senior research members of Dr.Choi's research group for their help and ideas. Thanks go to my friends and roommates for all the happy times and memorable moments we shared. Lastly, but most importantly, I am indebted to my parents, my mother aunt for their unparallel love and patience with me during my endeavors. Without special support and motivation from my uncles, aunt and love from my brothers, Srihari, Varun, Karthik and young sister Vaishnavi, grandparents and all my close relatives and friends back in India, I would not have been able to reach this stage of life. vi

Many modern Field Programmable Logic Arrays (FPGAs) use lookup table (LUT) logic blocks which can be programmed to realize any function of a fixed number of inputs. It is possible to employ logic blocks that realize only a subset of all functions, while the rest can be obtained by permuting and negating the inputs. Such blocks, known as Universal Logic Modules (ULMs), have already been considered for application in FPGAs; in this paper, we propose a new class of ULMs which is more useful in the FPGA environment. Methodology for systematic development of such blocks is presented, based on the BDD description of logic functions. We give an explicit construction of a three-input LUT replacement that requires only five programming bits, which is the optimum for such ULMs. A realistic size four-input LUT replacement is obtained which uses 13 programming bits.

We review some of the techniques for designing with FPGAs and CPLDs used in our design of a large-scale multiprocessor. Several issues concerning high-speed design are addressed: selecting the appropriate programmable logic family, obtaining the fastest circuits with given families, and supplementing the synthesis software. We describe techniques that we used for designing controllers and counters with both CPLDs and FPGAs.

HAMLET is a CAD tool that translates a user specification of a multiple-valued expression into a layout of a multiple-valued programmable logic array (MVL-PLA) which realizes that expression. It is modular to accommodate future minimization heuristics and future MVL-PLA technologies. At present, it implements two heuristics, [2] and [8] and one MVL-PLA technology, current-mode CMOS [6]. Specifically, HAMLET accepts a sum-of-products expression from the user, applies a minimization heuristic, and then produces a PLA layout of a multiple-valued current-mode CMOS PLA. Besides its design capabilities, HAMLET can also analyze heuristics. Random functions can be generated, heuristics applied, and statistics computed on the results. User-derived expressions can also be analyzed. In addition to the mininlization heuristics [2] and [8], HAMLET can apply search strategies based on these heuristics, which, in the extreme, is exhaustive, producing true minimal forms. HAMLET is available to the public; instructions on how to obtain this program are in Appendix A. It is written in C and conforms to the UNIX command line format. This paper describes HAMLET (Heuristic Analyzer for Multiple-valued Logic Expression Translation), a

The purpose of this work is to introduce two fault tolerant architectures for application in the mecatronics systems control, which require operation reliability and availability. The unit of processing in one of the architectures was the PIC 16F84A, and in another it was used the Basic Step 2K. Both the architectures are composed by three identical modules, which they communicate by means of protocols implemented by programming. They are able of detect faults in a module, of transparent way to the application. Or in another words, without interference or interruption in the control task. In both the architectures, in case of fault in a module, they can be left for maintenance and afterwards reintegrated to the system, without implying in the idleness of the controlled mecatronic system. Details on the differences and similarities between both architectures, characteristics of the hardware and software projects, as well as considerations about its performances, they are boarded alon...

Currently, digital systems that are able to meet major security restrictions are increasingly being demanded, both in the military and in commercial areas. Data security can be achieved by cryptographic algorithms. An important encryption algorithm known as data encryption standard (DES) was implemented in field programmable gate array (FPGA) in different synchronous architectures. In this paper, we have proposed the implementation of the DES algorithm in FPGA, in the asynchronous pipeline style. Compared to the implementation in FPGA using two different project styles, the proposed asynchronous obtained the average increase of 14.9% in throughput and the average reduction of 66.3% in latency.

Standard Deontic Logic (SDL) has been used as the underlying logic to model and reason over Multi-Agent Systems governed by norms (NorMAS). It is known that SDL is not able to represent contrary-to-duty (CTD) scenarios in a consistent way. That is the case, for example, of the so-called Chisholm paradox, which models a situation in which a conditional obligation that specifies what must be done when a primary obligation is violated holds. In SDL, the set of sentences that represent the Chisholm paradox derives inconsistent sentences. Due to the autonomy of the software agents of a NorMAS, norms may be violated and the underlying logic used to model the NorMAS should be able to represent violation scenarios. The contribution of this paper is threefold: (i) we present how Kelsenian thinking, from his jurisprudence in the context of legal ontologies, and Intuitionist Hybrid Logic can be adopted in the modeling of NorMAS, (ii) discuss how this approach overcomes limitations of the SDL a...

This paper present the research work directed towards the design of reversible programmable logic array using very high speed integrated circuit hardware description language (VHDL). Reversible logic circuits have significant importance in bioinformatics, optical information processing, CMOS design etc. In this paper the authors propose the design of new RPLA using Feynman & MUX gate. VHDL based codes of reversible gates with simulating results are shown .This proposed RPLA may be further used to design any reversible logic function or Boolean function (Adder, Subtractor etc.) which dissipate very low or ideally no heat.

Ecient parallel schemes for carry-propagation-free addition of modi®ed signed-digit trinary numbers are presented. The necessary minterms for implementation using an optical programmable logic array area are derived. The proposed schemes require only a truth table of 25 entries compared with an earlier scheme of 625 entries. The proposed schemes are amenable to optical implementation. Experimental results using an optical programmable logic array are demonstrated. The experiments show the problems of noise and crosstalk. This suggests some dc bias is necessary to increase the signal-to-noise ratio of the optical circuit.

The FPGA (Field Programmable Gate Array) circuits contain programmable logic components and are increasingly popular in implementing the applications for obtaining and processing signals. FPGA represents a modern development trend in digital electronics. The integration in the work with students of this trend is a difficult task, but also useful, because many students face problems when they must use a design environment. The application of FPGA technology can be useful to students either for the laboratory work on advanced topics, or for obtaining skills to use an industry standard design environment. The purpose of this paper is to conduct studies on the need to integrate the FPGA digital electronics trend in the laboratory didactic activity of the students. As case study, we present the design of a control circuit and its implementation in a FPGA, i.e. on a Basys2 board with Xilinx programming environment.

This paper explores the effect of logic block architecture on the speed of a field-programmable gate array (FPGA). Four classes of logic block architecture are investigated: NAND gates, multiplexer configurations, lookup tables, and wide-input AND-OR gates. An experimental approach is taken, in which each of a set of benchmark logic circuits is synthesized into FPGA's that use different logic blocks. The speed of the resulting FPGA implementations using each logic block is measured. While the results depend on the delay of the programmable routing, experiments indicate that five-and six-input lookup tables and certain multiplexer configurations produce the lowest total delay over realistic values of routing delay. The primary reason is that these blocks can implement typical logic using the fewest levels of logic blocks, and thus incur a small number of stages of the slow programmable routing present in all FPGA's. The secondary reason is that their inherent combinational delay is not excessive. The fine grain blocks, such as the two-input NAND gate, exhibit poor performance because these gates require many levels of logic block to implement the circuits and hence require a large routing delay.

This paper presents the architecture for a nanoelectronic logic system in which a regular array of logic gates with programmable interconnections is accompanied by a data transmitter and receiver as well as program registers and a controller. Binary programmable interconnections assure system versatility by providing the means of computing different logic operations. They also allow setting the redundancy level via the number of columns clustered to compute a certain function. A system operation is explained and visualized with a number of examples. The embedded scheme of fault tolerance can effectively mitigate permanent, as well as transient, faults. Some implementation and performance aspects are approached through simulations of single-electron tunneling structures. However, the proposed architectural concept is generic and can be applied to systems implemented with alternative nanotechnologies.

Standard Deontic Logic (SDL) has been used as the underlying logic to model and reason over Multi-Agent Systems governed by norms (NorMAS). It is known that SDL is not able to represent contrary-to-duty (CTD) scenarios in a consistent way. That is the case, for example, of the so-called Chisholm paradox, which models a situation in which a conditional obligation that specifies what must be done when a primary obligation is violated holds. In SDL, the set of sentences that represent the Chisholm paradox derives inconsistent sentences. Due to the autonomy of the software agents of a NorMAS, norms may be violated and the underlying logic used to model the NorMAS should be able to represent violation scenarios. The contribution of this paper is threefold: (i) we present how Kelsenian thinking, from his jurisprudence in the context of legal ontologies, and Intuitionist Hybrid Logic can be adopted in the modeling of NorMAS, (ii) discuss how this approach overcomes limitations of the SDL a...

Standard Deontic Logic (SDL) has been used as the underlying logic to model and reason over Multi-Agent Systems governed by norms (NorMAS). It is known that SDL is not able to represent contrary-to-duty (CTD) scenarios in a consistent way. That is the case, for example, of the so-called Chisholm paradox, which models a situation in which a conditional obligation that specifies what must be done when a primary obligation is violated holds. In SDL, the set of sentences that represent the Chisholm paradox derives inconsistent sentences. Due to the autonomy of the software agents of a NorMAS, norms may be violated and the underlying logic used to model the NorMAS should be able to represent violation scenarios. The contribution of this paper is threefold: (i) we present how Kelsenian thinking, from his jurisprudence in the context of legal ontologies, and Intuitionist Hybrid Logic can be adopted in the modeling of NorMAS, (ii) discuss how this approach overcomes limitations of the SDL a...

This paper presents some results of PLA area optimizing by means of its column and row folding. A more restricted type of PLA simple folding is considered. It is introduced by Egan and Liu and called as bipartite folding. An efficient approach is presented which allows finding an optimal bipartite folding without exhaustive computational efforts.

In this paper we present the design and implementation of architectures suitable for evolving digital circuits and show how these architectures can be instantiated on 'off-the-shelf' commercial programmable logic devices such as Field Programmble Gate Arrays (FPGA's). We discuss architecture details and the design flow from the initial cell specification through to targeting specific commercial devices. We also present an example of such an implementation, where a simple fine-grained programmable logic array is designed and targeted to a number of popular commercial FPGA's. A critical discussion of this approach is also given.

In this paper we describe a programmable and adaptive jilter based on floating-gate technology. We review the basics offloating-gate techniques and how they enable programmable and adaptive jilter circuits. We describe our programmable filter concepts, and show experimental results of programmable Jilter operation. We also describe programming methods, and extend the programmability to a wide range of functions and circuits using the same approach. Further; we describe our techniques and custom programmer board for joating-gate programming of an IC. We show how to extend our programmable jilters as adaptive jilters both through weight perturbation methods and continuously adapting correlation rule methods.

Code 128 Barcode Reader Implemented on Field Programmable Gate Array is an application of image capture and post-processing for encoded data analysis using programmable logic. The embedded Field Programmable Gate Array (FPGA) of Xilinx Spartan-3 Starter Kit Board was utilized for decoding a specific barcode input, the Code 128. The project used a CMOS camera to capture images and store data into the FPGA. The decoding logic is subdivided into different modules described using Very High Speed Integrated Circuit Hardware Description Language (VHSIC HDL or VHDL). The decoded results were displayed into a monitor screen in the form of characters based on the specific table for the Code 128 barcode.

In this paper, the design application is a telemetry system intended for health monitoring applications. The Field Programmable Gate Array (FPGA) is used as the brain control unit at both transmitter and receiver sides. The transmitter side is recording data packets through external interfaced sensors. Verilog Hardware Description Language (Verilog-HDL) has been used to implement the various functionalities required by the FPGA device. The power performance of the FPGA-based design will be assessed using the XILINX Xpower tool. A Model sim Code coverage feature has been incorporated to make sure that the test bench will cover all the nets branch statements of the design and create the most accurate Value Change Dump (VCD) file for the power consumption assessment process.

Nano-crossbar arrays have emerged as area and power efficient structures with an aim of achieving high performance computing beyond the limits of current CMOS. Due to the stochastic nature of nano-fabrication, nano arrays show different properties both in structural and physical device levels compared to conventional technologies. Mentioned factors introduce random characteristics that need to be carefully considered by synthesis process. For instance, a competent synthesis methodology must consider basic technology preference for switching elements, defect or fault rates of the given nano switching array and the variation values as well as their effects on performance metrics including power, delay, and area. Presented synthesis methodology in this study comprehensively covers the all specified factors and provides optimization algorithms for each step of the process.

In this paper we describe a programmable and adaptive jilter based on floating-gate technology. We review the basics offloating-gate techniques and how they enable programmable and adaptive jilter circuits. We describe our programmable filter concepts, and show experimental results of programmable Jilter operation. We also describe programming methods, and extend the programmability to a wide range of functions and circuits using the same approach. Further; we describe our techniques and custom programmer board for joating-gate programming of an IC. We show how to extend our programmable jilters as adaptive jilters both through weight perturbation methods and continuously adapting correlation rule methods.

A novel GaAs logic family, pseudodynamic latched logic (PDLL), is presented in this paper. It is composed of a dynamic circuit where the logic is performed and a static latch whose function is to permanently refresh the stored data on a dynamic node. Because of this hybrid structure, PDLL takes advantage of both static and dynamic families and thus, permits implementation of very complex structures with good speed-areapower tradeoff. Moreover, the inclusion of the latch permits this class of logic family to be highly efficient for pipelined systems working even at high temperature without loss of data due to leakage currents. Barrel-shifters, programmable logic arrays (PLA's), and carry lookahead adders (CLA's) were verified by simulations demonstrating its feasibility for the development of high-performance very large scale integration (VLSI) systems.

A recently introduced TRAnsistor-level Programmable fabric (TRAP) has demonstrated great promise towards seamless unification of high-density reconfigurable logic with Application-Specific Integrated Circuits (ASICs). However, practical deployment of TRAP relies on the development of a comprehensive mechanism for detecting manufacturing defects. Unfortunately, the state-of-the-art test schemes are developed either for ASICs or for Field-Programmable Gate Arrays (FPGAs) and do not support this new transistor-level architecture. To address this limitation, we present a novel application-agnostic test methodology specifically tailored to the TRAP fabric. We first introduce a multi-phase, cascadable scheme to efficiently test the programmable transistors in TRAP's Logic Elements (LEs). Then, we define the required test patterns for verifying the correct functionality of the built-in D flip-flop, full-adder, and multiplexer of each LE. Next, we present a systematic approach for testing the interconnect network. Lastly, we discuss the limitations in testing the memory cells used for storing the TRAP programming bits and we propose design modifications for improving test coverage.

The paper introduces a new approach for designing of self-checking Microprogram Control Units (MCU). Using a Finite State Machine (FSM) as a form of MCU representation leads to its PLA-implementation having a system of product terms which are orthogonal and complete. An additional important property of MCU is related to a limited total number of possible code-words. These features can be used for construction of self-checking PLAs with relatively small overheads. Keywords: Self-checking, on-line checking, microprogram ...

The FPGA (Field Programmable Gate Array) circuits contain programmable logic components and are increasingly popular in implementing the applications for obtaining and processing signals. FPGA represents a modern development trend in digital electronics. The integration in the work with students of this trend is a difficult task, but also useful, because many students face problems when they must use a design environment. The application of FPGA technology can be useful to students either for the laboratory work on advanced topics, or for obtaining skills to use an industry standard design environment. The purpose of this paper is to conduct studies on the need to integrate the FPGA digital electronics trend in the laboratory didactic activity of the students. As case study, we present the design of a control circuit and its implementation in a FPGA, i.e. on a Basys2 board with Xilinx programming environment.

Field-programmable gate arrays (FPGA's) are now widely used for the implementation of digital systems, and many commercial architectures are available. Although the literature and data books contain detailed descriptions of these architectures, there is very little information on how the high-level architecture was chosen and no information on the circuit-level or physical design of the devices. In Part I of this paper, we described the high-level architectural design of a static randomaccess memory programmable FPGA. This paper will address the circuit-design issues through to the physical layout. We address area-speed tradeoffs in the design of the logic block circuits and in the connections between the logic and the routing structure. All commercial FPGA designs are done using full-custom hand layout to obtain absolute minimum die sizes. This is both labor and time intensive. We propose a design style with a minitile that contains a portion of all the components in the logic tile, resulting in less full-custom effort. The minitile is replicated in a 4 2 4 array to create a macro tile. The minitile is optimized for layout density and speed, and is customized in the array by adding appropriate vias. This technique also permits easy changing of the hard-wired connections in the logic block architecture and the segmentation length distribution in the routing architecture.