Processing Element

V. SUMMARY We have given parallel algorithms for recognizing and parsing context-free languages on a hypercube of p PE's, 1 5 p 5 n. The algorithms are both time-wise and space-wise optimal with respect to the most efficient sequential algorithm. The recognition algorithms were ...

This paper describes initial results of a project developing fault tolerant control systems for critical aircraft systems and focuses on the early detection of faulty components. The main goal is to present the use of signal processing techniques to analyze sensor information and data-mine changes that could be attributable to faulty behavior. The approach compares well with residual-based techniques but requires only output data. Hence, it could be applied to situations where residual-based approaches are not feasible.

To subdivide the axis k into 2 new axes p and q, we place k=p+qN/r with p=0,1, ... , N/r s-1, s=0,1, ... ,logrN-1 and q = 0,1,...., r -1. Therefore, X(k) is replaced using new indices p and q where x [n] is the input sequence, X[k] is the output sequence, N is the transform length, w: k = e-j(2tr/N)nk is called the twiddle factor in the butterfly structure, and j2=_1. Both x [n] and X [k] are complex valued number sequences.

Artificial Neural Networks are proposed to model and predict electricity consumption of Turkey. Multi layer perceptron with backpropagation training algorithm is used as the neural network topology. Tangent-sigmoid and pure-linear transfer functions are selected in the hidden and output layer processing elements, respectively. These input-output network models are a result of relationships that exist among electricity consumption and several other socioeconomic variables. Electricity consumption is modeled as a function of economic indicators such as population, gross national product, imports and exports. It is also modeled using export-import ratio and time input only. Performance comparison among different models is made based on absolute and percentage mean square error. Electricity consumption of Turkey is predicted until 2027 using data from 1975 to 2006 along with other economic indicators. The results show that electricity consumption can be modeled using Artificial Neural Networks, and the models can be used to predict future electricity consumption.

Multi-Step ahead prediction of a chaotic time series is a difficult task that has attracted increasing interest in recent years. The interest in this work is the development of nonlinear neural network models for the purpose of building multistep ahead prediction of North and South hemisphere sunspots chaotic time series. In the literature there is a wide range of different approaches but their success depends on the predicting performance of the individual methods. Also the most popular neural models are based on the statistical and traditional feed forward neural networks. But it is seen that this kind of neural model may present some disadvantages when longterm prediction is required. In this paper focused time lagged recurrent neural network (FTLRNN) model with gamma memory is developed not only for short-term but also for long-term prediction which allows to obtain better predictions of northern and southern chaotic time series in future. The authors experimented the performance of this FTLRNN model on predicting the dynamic behavior of typical northern and southern sunspots chaotic time series. Static MLP model is also attempted and compared against the proposed model on the performance measures like mean squared error (MSE), Normalized mean squared error (NMSE) and Correlation Coefficient (r) .The standard back propagation algorithm with momentum term has been used for both the models. The various parameters like number of hidden layers, number of processing elements in the hidden layer, step size, the different learning rules, the various transfer functions like tanh, sigmoid, linear-tanh and linear sigmoid, different error norms L 1 ,L 2 (Euclidean), L 3, L 4 ,L 5 and L ∞ , and different combination of training and testing samples are exhaustively varied and experimented for obtaining the optimal values of performance measures. The obtained results indicates the superior performance of estimated dynamic FTLRNN based model with gamma memory over the static MLP NN in various performance metrics. In addition, the output of proposed FTLRNN neural network model with gamma memory closely follows the desired output for multi-step ahead prediction for all the chaotic time series considered in the study.

We present two designs (I and II) for IEEE 754 double precision floating point matrix multiplication, optimized for implementation on high-end FPGAs. It forms the kernel in many important tile-based BLAS algorithms, making an excellent candidate for acceleration. The designs, both based on the rank-1 update scheme, can handle arbitrary matrix sizes, and are able to sustain their peak performance

The most important issue in sequential program parallelisation is the efficient assignment of computations into different processing elements. In the past, too many approaches were devoted in efficient program parallelization considering various models for the parallel programs and the target architectures. The most widely used parallelism description model is the task graph model with precedence constraints. Nevertheless, as far as physical mapping of tasks onto parallel architectures is concerned, little research has given practical results. It is well known that the physical mapping problem is NP-hard in the strong sense, thus allowing only for heuristic approaches. Most researchers or tool programmers use exhaustive algorithms, or the classical method of simulated annealing. This paper presents an alternative approach onto the mapping problem. Given the graph of clustered tasks, and the graph of the target distributed architecture, our heuristic finds a mapping by first placing the highly communicative tasks on adjacent nodes of the processor network. Once these «backbone» tasks are mapped, there is no backtracking, thus achieving low complexity. Therefore, the remaining tasks are placed beginning from those close to the «backbone» tasks. The paper concludes with performance and comparison results which reveal the method's efficiency.

The Mayfly is a scalable general-purpose parallel processing system being designed at HP Laboratories, in collaboration with colleagues at the University of Utah. The system is intended to efficiently support parallel variants of modern programming languages such as Lisp, Prolog, and Object Oriented Programming models. These languages impose a common requirement on the hardware platform to support dynamic system needs such as runtime type checking and dynamic storage management. The main programming language for the Mayfly is a concurrent dialect of Scheme. The system is based on a distributed-memory model, and communication between processing elements is supported by message passing. The initial prototype of Mayfly will consist of 19 identical processing elements interconnected in a hexagonal mesh structure. In order to achieve the goal of scalable performance, each processing element is a parallel processor as well, which permits the application code, runtime operating system, and communication to all run in parallel. A 7 processing element subset of the prototype is presently operational. This paper describes the hardware architecture after a brief background synopsis of the software system structure.

This paper describes an efficient architecture to perform modular exponentiation using the Montgomery Powering Ladder algorithm. The implementation is composed by two parallel modular multiplication modules in order to speedup the modular exponentiation time. The modular multiplication architecture is high-radix and presents an onedimensional array of processing elements within multiplexed multipliers. This architecture can performs the 1024 bits RSA decryption in 2.5 ms. Furthermore, the modular exponentiation architecture presents a countermeasure against SPA attack.

Abstract: The growing computational power of modern graphics processing units is making them very suitable for general purpose computing. These commodity processors operate generally as parallel SIMD platforms and, among other factors, the effectiveness of the codes is ...

Speech-to-speech translation technology has difficulties processing elements of spontaneity in conversation. We propose a discourse marker attribute in speech corpora to help overcome some of these problems. There have already been some attempts to annotate discourse markers in speech corpora. However, as there is no consistency on what expressions count as discourse markers, we have to reconsider how to set a framework for annotating, and, in order to better understand what we gain by introducing a discourse marker category, we have to analyse their characteristics and functions in discourse. This is especially important for languages such as Slovenian where no or little research on the topic of discourse markers has been carried out. The aims of this paper are to present a scheme for annotating discourse markers based on the analysis of a corpus of telephone conversations in the tourism domain in the Slovenian language, and to give some additional arguments based on the characteristics and functions of discourse markers that confirm their special status in conversation.

I NFORMATION SYSTEMS STRATEGY PLANNING (ISSP) has been identified as vital to continuing organizational success and effective IS performance.'-3 However, although ISSP methodologies have been used for many years, organizations are still failing to deal effectively with untangling IS planning-related problems. This is mainly because many ISSP methodologies do not seem to realize that the IS-related problems result not merely from technological problems, but are also derived from paying too little attention to the interrelationship between IS and business and organizational factors." Research has shown that despite the growing number of theoretical frameworks for ISSP, practice still faces three major problems: ?? need for integration of ISSP and overall corporate ?? moderate practical utility of existing ISSP meth-?? limited management involvement and commitment to the ISSP activities4."

Modern software-intensive systems are developed in a world where only constant thing is change. This results in continuously changing requirements. Failure to manage these changing requirements properly may result in failure of system. To manage these requirements, many requirements change management (RCM) process model has been proposed in the literature. Process models facilitate human understating and communication, support process improvement and process management. Coverage of process elements like activities, artifacts and roles has an affect on process model and its usage. This paper reports the current requirements change management process models in the literature on the basis of activities, artifacts and roles. Our survey highlights that there is lack of consensus on RCM process and it has not been described in sufficient detail for use of requirements engineers in the real world.

Artificial neural networks (ANNs) are biologically inspired computer programs designed to simulate the way in which the human brain processes information. ANNs gather their knowledge by detecting the patterns and relationships in data and learn (or are trained) through experience, not from programming. An ANN is formed from hundreds of single units, artificial neurons or processing elements (PE), connected with coefficients (weights), which constitute the neural structure and are organised in layers. The power of neural computations comes from connecting neurons in a network. Each PE has weighted inputs, transfer function and one output. The behavior of a neural network is determined by the transfer functions of its neurons, by the learning rule, and by the architecture itself. The weights are the adjustable parameters and, in that sense, a neural network is a parameterized system. The weighed sum of the inputs constitutes the activation of the neuron. The activation signal is passed through transfer function to produce a single output of the neuron. Transfer function introduces non-linearity to the network. During training, the inter-unit connections are optimized until the error in predictions is minimized and the network reaches the specified level of accuracy. Once the network is trained and tested it can be given new input information to predict the output. Many types of neural networks have been designed already and new ones are invented every week but all can be described by the transfer functions of their neurons, by the learning rule, and by the connection formula. ANN represents a promising modeling technique, especially for data sets having non-linear relationships which are frequently encountered in pharmaceutical processes. In terms of model specification, artificial neural networks require no knowledge of the data source but, since they often contain many weights that must be estimated, they require large training sets. In addition, ANNs can combine and incorporate both literature-based and experimental data to solve problems. The various applications of ANNs can be summarised into classification or pattern recognition, prediction and modeling. Supervised associating networks can be applied in pharmaceutical fields as an alternative to conventional response surface methodology. Unsupervised feature-extracting networks represent an alternative to principal component analysis. Non-adaptive unsupervised networks are able to reconstruct their patterns when presented with noisy samples and can be used for image recognition. The potential applications of ANN methodology in the pharmaceutical sciences range from interpretation of analytical data, drug and dosage form design through biopharmacy to clinical pharmacy.

Ray-based seismic modeling methods can be applied at various stages of the exploration and production process. The standard ray method has several advantages, e.g., computational efficiency and the possibility of simulating propagation of elementary waves. As a high-frequency approximation, the method also has a number of limitations, particularly with respect to a lack of amplitude reliability in the presence of rapid changes of the model functions representing elastic parameters and interfaces. Given the objective of improving the applicability of the standard ray method, we present a strategy that does not require specific extension to finite frequencies. Instead, we define each ray-based process as an element of a system that, as a composite process, is able to obtain better results than the ray-based process applied alone. Other elements of the composite process can be finite-difference modeling or numerical solutions for surface and volume integrals, which are basic constituents of Kirchhoff modeling and imaging. We also include among the process elements recently developed techniques for simulating the migration amplitude on a target reflector and in a local volume, e.g., a reservoir zone. The model is decomposed according to its complexity into volume elements, surface elements, or a combination. The composite process consists of a specified interaction between process elements and model elements, which fits well with the philosophy of modern software design. Model elements that will be exposed to ray-tracing algorithms may need appropriate preparation, e.g., smoothing and resampling. We demonstrate specifically, in a tutorial example, that simulating the seismic response from a reflector by ray-based composite processes can yield better results than applying standard ray tracing alone.

To solve the contradiction between the noise reducing effect and the time complexity of the standard median filter algorithm, this paper proposed an improved median filter algorithm. This paper focuses on a 3x3 image window filtering in which the sorting network of the filter should be able to produce the desired result within the shortest time possible. That means, the sorting network will be able to exercise parallelism in processing the image pixel and the number of the required hardware maintained minimal. The algorithm derived shows that the sorting network will be able to produce the result within the required time. The improved filter algorithm was implemented using Hardware Description Language Verilog, simulated using Xilinx isim and was loaded on to Xilinx FPGA. The hardware result showed that this proposed algorithm has better output result as compared to standard median algorithm as well as adaptive median algorithm. It has a good application prospect in real-time image processing.

Black liquor is the major by-product and fuel of pulp mills. In this work, effects of black liquor properties on its recovery unit operation are analyzed. Thus, an experimental methodology for characterizing the principal chemical and physical properties of eucalyptus Kraft and bamboo soda black liquors has been developed, including sample collections from six Brazilian mills. Based on results, eucalyptus and bamboo black liquors present higher contents of non-processing elements (NPEs), higher concentration and different molar mass of lignin than those reported by the pine Kraft black liquor. This leads to distinct rheological properties of these liquors. By comparing results obtained for the both liquors, the bamboo and the eucalyptus, the former has the lowest sulfur level, the highest silicon and lignin concentration and, consequently, the highest apparent viscosity.

A conceptual frame of reference called The River is presented for training of beginning psychotherapists. Using metaphors, trainees are taught specific tools (Equipment) and to identify salient features of the therapy process (Topography) by means of a series of metaphors for the process elements of timing and of level of intervention. Student therapist feedback indicated that this model facilitated learning of how much or little to do at given points in the therapeutic process, and that these metaphors appeared to transcend specific theoretical orientations.

The voltage/frequency island (VFI) design paradigm is a practical architecture for energy-efficient networks-on-chip (NoC) systems. In VFI-based NoC systems, each island can be operated with different voltage and clock frequency and thus it is important to carefully partition processing elements (PEs) into islands based on their workloads and communications. In this paper, we propose an energy-efficient design scheme that optimizes energy consumption and hardware costs in VFI-based NoC systems. Since on-chip networks take up a substantial portion of system power budget in NoC-based systems, the proposed scheme uses communication-aware VFI partitioning and tile mapping/routing algorithms to minimize the inter-VFI communications. Experimental results show that the proposed design technique can reduce communication energy consumption by 32–51% over existing techniques and total energy consumption by 3–14%.

Efficient run-time mapping of tasks onto Multiprocessor System-on-Chip (MPSoC) is very challenging especially when new tasks of other applications are also required to be supported at run-time. In this paper, we present a number of communication-aware run-time mapping heuristics for the efficient mapping of multiple applications onto an MPSoC platform in which more than one task can be supported by each processing element (PE). The proposed mapping heuristics examine the available resources prior to recommending the adjacent communicating tasks on to the same PE. In addition, the proposed heuristics give priority to the tasks of an application in close proximity so as to further minimize the communication overhead. Our investigations show that the proposed heuristics are capable of alleviating Networkon-Chip (NoC) congestion bottlenecks when compared to existing alternatives. We map tasks of applications onto an 8 Â 8 NoC-based MPSoC to show that our mapping heuristics consistently leads to reduction in the total execution time, energy consumption, average channel load and latency. In particular, we show that energy savings can be up to 44% and average channel load is improved by 10% for some cases.

The quest to improve performance forces designers to explore finer-grained multiprocessor machines. Ever increasing chip densities based on CMOS improvements fuel research in highly parallel chip multiprocessors with 100s of processing elements. With such increasing levels of parallelism, synchronization is set to become a major performance bottleneck and efficient support for synchronization an important design criterion. Previous research has shown that integrating support for fine-grained synchronization can have significant performance benefits compared to traditional coarse-grained synchronization. Not much progress has been made in supporting fine-grained synchronization transparently to processor nodes: a key reason perhaps why wide adoption has not followed.

We present an overview of imaging systems that incorporate a volume hologram as one of the optical field processing elements in the system. We refer to these systems as volume holographic imaging (VHI) systems. The volume hologram is recorded just once, and the recording parameters depend on the functional requirements of the imaging system. The recording step offers great flexibility in designing applicationspecific imaging systems. We discuss how a VHI system can be configured for diverse imaging applications ranging from surface profilometry to real-time hyperspectral microscopy, and summarize recent developments in this field.

A significant part of scientific codes consist of sparse matrix computations. In this work we propose two new pseudoregular data distributions for sparse matrices. The Multiple Recursive Decomposition (MRD) partitions the data using the prime factors of the dimensions of a multiprocessor network with mesh topology. Furthermore, we introduce a new storage scheme, storage-by-row-of-blocks, that significantly increases the efficiency of the Scatter distribution. We will name Block Row Scatter (BRS) distribution this new variant. The MRD and BRS methods achieve results that improve those obtained by other analyzed methods, being their implementation easier. In fact, the data distributions resulting from the MRD and BRS methods are a generalization of the Block and Cyclic distributions used in dense matrices.

We introduce a 64-bit ANSI/IEEE Std 754-1985 floating point design of a hardware matrix multiplier optimized for FPGA implementations. A general block matrix multiplication algorithm, applicable for an arbitrary matrix size is proposed. The algorithm potentially enables optimum performance by exploiting the data locality and reusability incurred by the general matrix multiplication scheme and considering the limitations of the I/O bandwidth and the local storage volume. We implement a scalable linear array of processing elements (PE) supporting the proposed algorithm in the Xilinx Virtex II Pro technology. Synthesis results confirm a superior performance-area ratio compared to related recent works. Assuming the same FPGA chip, the same amount of local memory, and the same I/O bandwidth, our design outperforms related proposals by at least 1.7X and up to 18X consuming the least reconfigurable resources. A total of 39 PEs can be integrated into the xc2vp125-7 FPGA, reaching performance of, e.g., 15.6 GFLOPS with 1600 KB local memory and 400 MB/s external memory bandwidth.

Highly affect-laden memory intrusions are a feature of several psychological disorders with intrusive images of trauma especially associated with post-traumatic stress disorder (PTSD). The trauma film paradigm provides a prospective experimental tool for investigating analogue peri-traumatic cognitive mechanisms underlying intrusion development. We review several historical papers and some more recent key studies that have used the trauma film paradigm. A heuristic diagram is presented, designed to simplify predictions about analogue peri-traumatic processing and intrusion development, which can also be related to the processing elements of recent cognitive models of PTSD. Results show intrusions can be induced in the laboratory and their frequency amplified/attenuated in line with predictions. Successful manipulations include competing task type (visuospatial vs. verbal) and use of a cognitive coping strategy. Studies show that spontaneous peri-traumatic dissociation also affects intrusion frequency although attempts to manipulate dissociation have failed. It is hoped that further use of this paradigm may lead to prophylactic training for at risk groups and an improved understanding of intrusions across psychopathologies.

In the world of complex SoCs for consumer applications, multiprocessor architectures usually deploy caching techniques to alleviate the cost of data communication between processing elements. In this application domain, the characteristics of streaming applications play a dominant role in the design of the multiprocessor architectures. These characteristics not only influence the design at SoC level, but also permeate the design of lower level blocks, such as caches. This paper proposes three novel techniques for data caching in multiprocessor streaming architectures. These techniques exploit the combination of mechanisms from the domains of stream caching and cache coherency, optimizing the effectiveness of data caches in a streaming multiprocessor context. Our first implementation targets cache systems in a multiprocessor architecture for high-definition MPEG decoding, where six function-specific processors communicate through shared embedded SRAM. Simulation results demonstrate the effectiveness of the presented techniques, even though the caches are of very small dimensions, i.e., 0.12 mm2 in 0.12µ technology.

I N this dissertation, we address the problem of runtime adaptation of the application to its execution environment. A typical example is changing the processing element on which a computation is executed, considering the available processing elements in the system. This is done based on the information and instrumentation provided by the compiler and taking into account the status of the environment. The work focuses on heterogeneous multicore embedded architectures. We address three aspects of application optimizations: hardware software mapping, memory allocation and parallel execution. For each aspect, an algorithm is developed and, using a suitable application, it is tested on the hardware platform. The programming paradigm on which this work is based is the Molen programming paradigm, extended and adapted for our specific platform and operating environment.

An MIMD multiprocessor digital signal-processing (DSP) chip containing four 64-b processing elements (PE's) interconnected by a 128-b pipelined split transaction bus (STBus) is presented. Each PE contains a 32-b RISC core with DSP enhancements and a 64-b single-instruction, multiple-data vector coprocessor with four 16-b MAC/s and a vector reduction unit. PE's are connected to the STBus through reconfigurable dual-ported snooping L1 cache memories that support shared memory multiprocessing using a modified-MESI data coherency protocol. High-bandwidth data transfers between system memory and on-chip caches are managed in a pipelined memory controller that supports multiple outstanding transactions. An embedded RTOS dynamically schedules multiple tasks onto the PE's. Process synchronization is achieved using cached semaphores. The 200-mm 2 , 0.25-m CMOS chip operates at 100 MHz and dissipates 4 W from a 3.3-V supply.

Image segmentation can be performed by recursively splitting the whole image or by merging together a large number of minute regions until a specified condition is satisfied. The split and merge procedure of image segmentation takes an intermediate level in an image description as the starting cutset and thereby achieves a compromise between merging small primitive regions and recursively splitting the whole image in order to reach the desired final cutset. The choice of the initial cutset offers significant savings in computation time. A 2-D array implementation of image segmentation by a directed split and merge procedure has been proposed in this paper. Parallelism is realized on two levels: one within the split and merge operations, where more than one merge (or split) may proceed concurrently, and the second between the split and merge operations, where several splits may be performed in parallel with merges. Both the split and merge operations are based on nearest neighbor communications between the processing elements (PE's) and therefore facilitate low communication costs. The basic arithmetic operations required to perform split and merge are comparison and addition. This allows a simple structure of the PE as well as a hardwired control. A local memory of 512 bytes is sufficient to hold the interim data associated with each PE. A prototype of the PE has been constructed using the 3-pm double metal CMOS technology. Considering a scaling for up to 0.8 pm, it is possible to incorporate 16 PE's on a 2-56 cm2 chip. With sufficiently large PE window sizes, image segmentation through the proposed approach can be achieved in linear time.

There are many problems which fall into the class of temporal signal processing. These problems have in common the need to relate the temporal properties of their inputs. Conventional solutions to these problems often have high hardware overhead, complex algorithmic solutions, or loss of information through the transformation of temporal properties of the input. To this end, a biologically motivated artificial and neural processing element has been developed. As in biological neurons, processing is time dependent and is implemented using both analog and digital techniques. These characteristics make the PE directly applicable a large class of temporal signal processing problems typically encountered in engineering and science. Multiple aspects of the PE behavior are adjustable, which produces a very wide range of behaviors from simple systems with only a few moderately connected processing elements. The processing element models are custom designed electric circuits based on basic CMOS components and therefore all developed systems can be directly implemented in any standard integrated CMOS technology. The integrated implementation, custom design, and a wide range of adaptable behaviors join to produce a very fast, low-hardware solution to complex spatiotemporal signal processing problems. Seven novel systems based on the hybrid PE are discussed as they relate to commonly encountered temporal signal processing problems.

The physical layer of most wireless protocols is traditionally implemented in custom hardware to satisfy the heavy computational requirements while keeping power consumption to a minimum. These implementations are time consuming to design and difficult to verify. A programmable hardware platform capable of supporting software implementations of the physical layer, or software defined radio, has a number of advantages. These include support for multiple protocols, faster time-to-market, higher chip volumes, and support for late implementation changes. The challenge is to achieve this without sacrificing power. In this paper, we present a design study for a fully programmable architecture, SODA, that supports software defined radio -a high-end signal processing application. Our design achieves high performance, energy efficiency, and programmability through a combination of features that include single-instruction multiple-data (SIMD) parallelism, and hardware optimized for 16bit computations. The basic processing element is an asymmetric processor consisting of a scalar and SIMD pipeline, and a set of distributed scratchpad memories that are fully managed in software. Results show that a four processor design is capable of meeting the throughput requirements of the W-CDMA and 802.11a protocols, while operating within the strict power constraints of a mobile terminal.

Image segmentation can be performed by recursively splitting the whole image or by merging together a large number of minute regions until a specified condition is satisfied. The split and merge procedure of image segmentation takes an intermediate level in an image description as the starting cutset and thereby achieves a compromise between merging small primitive regions and recursively splitting the whole image in order to reach the desired final cutset. The choice of the initial cutset offers significant savings in computation time. A 2-D array implementation of image segmentation by a directed split and merge procedure has been proposed in this paper. Parallelism is realized on two levels: one within the split and merge operations, where more than one merge (or split) may proceed concurrently, and the second between the split and merge operations, where several splits may be performed in parallel with merges. Both the split and merge operations are based on nearest neighbor communications between the processing elements (PE's) and therefore facilitate low communication costs. The basic arithmetic operations required to perform split and merge are comparison and addition. This allows a simple structure of the PE as well as a hardwired control. A local memory of 512 bytes is sufficient to hold the interim data associated with each PE. A prototype of the PE has been constructed using the 3-pm double metal CMOS technology. Considering a scaling for up to 0.8 pm, it is possible to incorporate 16 PE's on a 2-56 cm2 chip. With sufficiently large PE window sizes, image segmentation through the proposed approach can be achieved in linear time.

To subdivide the axis k into 2 new axes p and q, we place k=p+qN/r with p=0,1, ... , N/r s-1, s=0,1, ... ,logrN-1 and q = 0,1,...., r -1. Therefore, X(k) is replaced using new indices p and q where x [n] is the input sequence, X[k] is the output sequence, N is the transform length, w: k = e-j(2tr/N)nk is called the twiddle factor in the butterfly structure, and j2=_1. Both x [n] and X [k] are complex valued number sequences.

Reconfigurable computing offers a wide range of low cost and efficient solutions for embedded systems. The proper choice of the reconfigurable device, the granularity of its processing elements and its memory architecture highly depend on This work was supported in part by the European Union in the 6th R&D Framework Program (MORPHEUS IST project, number 027342).

This paper describes the first steps towards a Java multiprocessor system on a single chip for embedded systems. The chip multiprocessing (CMP) system consists of a homogeneous set of processing elements and a shared memory. Each processor core is based on the Java Optimized Processor (JOP). A major challenge in CMP is the shared memory access of multiple CPUs. The proposed memory arbiter resolves possible emerging conflicts of parallel accesses to the shared memory using a fixed priority scheme. Furthermore, the paper describes the boot-up of the CMP. We verify the proposed CMP architecture by the implementation of the prototype called JopCMP. JopCMP consists of multiple JOPs and a shared memory. Finally yet importantly, the first implementation of the CMP composed of two/three JOPs in an FPGA enables us to present a comparison of the performance between a single-core JOP and the CMP version by running real applications.

This paper presents an analysis of the fault tolerance achieved by an autonomous, fully embedded evolvable hardware system, which uses a combination of partial dynamic reconfiguration and an evolutionary algorithm (EA). It demonstrates that the system may self-recover from both transient and cumulative permanent faults. This self-adaptive system, based on a 2D array of 16 (4×4) Processing Elements (PEs), is tested with an image filtering application. Results show that it may properly recover from faults in up to 3 PEs, that is, more than 18% cumulative permanent faults. Two fault models are used for testing purposes, at PE and CLB levels. Two self-healing strategies are also introduced, depending on whether fault diagnosis is available or not. They are based on scrubbing, fitness evaluation, dynamic partial reconfiguration and in-system evolutionary adaptation. Since most of these adaptability features are already available on the system for its normal operation, resource cost for self-healing is very low (only some code additions in the internal microprocessor core).

The 1 S amino acid agent BPC 157, showing a wide range of organoprotective action in different experimental models, was used in our experiments in order to establish its influence on different elements connected with the healing process. Elements thought to be of greatest importance in the process of healing are formation of granulation tissue, angiogenesis and production of collagen. In our work we tested the influence of BPC 157 on: granulation tissue and collagen formation, on angiogenesis as well as on tensile strength development, using three experimental rat models: I) skin incisional wounds: 2) colon-colon anastomoses: and 3) angiogenesis model with synthetic sponge implantation. The specimens were histologically assessed for collagen, reticulin and blood vessels using scoring and morphometry. In all experiments significant differences between BPC 157.treated animals and controls were found, showing a strong, promoting involvement of BPC in the healing process. It is worth noting that these effects were achieved by different routes of application, including intragastric and local, making BPC IS7 a potentially useful therapeutic agent.

1 in 1982 to describe the first cases of unusual immune system failure that were identified in the previous year. The human immunodeficiency virus (HIV) was later identified as the cause of AIDS. Risk factor epidemiology examines the individual demographic and social characteri- stics and attempts to determine factors that place an indi- vidual at risk of acquiring a life-threatening

In this paper the multi step ahead prediction of typical Duffing Chaotic time series and the monthly sunspots real time series are carried out. These two time series are popularized due to their highly chaotic behavior. This paper compares the performance of two neural network configurations namely a Multilayer Perceptron (MLP) and proposed FTLRNN with gamma memory for the duffing time series for 1, 5,10,20,50 and 100-step ahead prediction and for monthly sunspot time series for 1, 6, 12, 18 & 24 month ahead prediction. The standard back propagation algorithm with momentum term has been used for both the models. It is seen that estimated dynamic fully recurrent model clearly outperforms the MLP NN in various performance matrices such as Mean square error (MSE), Normalized mean square error (NMSE) and correlation coefficient (r) on testing as well as training data set for multi step prediction (K=1,5,10,20,50,100) for duffing time series and for the sunspot time series for 1, 6, 12, 18 &24 month ahead prediction. In addition, the output of proposed neural network model closely follows the desired output for all the step ahead prediction. It is observed that suggested recurrent models have the remarkable capability of time series prediction. The major contribution of this paper is that Various parameters like number of processing elements, step size, momentum value in hidden layer, in output layer the various transfer functions like tanh, sigmoid, linear-tan-h and linear sigmoid, different error norms L1, L2 ,Lp to L.

PRAM algorithms for Symmetric Gaussian elimination is presented. We showed actual testing operations that will be performed during Symmetric Gaussian elimination, which caused symbolic factorization to occur for sparse linear systems. The array pattern of processing elements (PE) in row major order for the specialized sparse matrix in formulated. We showed that the access function in 2 +jn+k contains topological properties. We also proved that cost of storage and cost of retrieval of a matrix are proportional to each other in polylogarithmic parallel time using P-RAM with a polynomial numbers of processor. We use symbolic factorization that produces a data structure, which is used to exploit the sparsity of the triangular factors. In these parallel algorithms number of multiplication/division in O(log 3 n), number of addition/subtraction in O(log 3 n) and the storage in O(log 2 n) may be achieved.

One benefit of the No Child Left Behind legislation (2001) has been the increasing attention on the importance of the skills learned in the pre-kindergarten period for later academic achievement. There is a growing awareness that mathematics skills in kindergarten and beyond are influenced by the formal and informal mathematics skills acquired in the pre-kindergarten classroom. In recent years, a

The hypercube structure is an attractive and powerful topology for interconnecting processing elements in a multiprocessor system since it allows simple deadlock-free routing and broadcasting. In a hypercube architecture, one has to visualize multidimensional objects to develop efficient algorithms or to analyze system behavior. However, human beings are habituated to at most three-dimensional objects. In this paper, we propose a novel two-dimensional representation of the hypercube structure. The proposed representation is used to design routing and broadcasting algorithms. Finally, a comparison of the proposed representation with the conventional hypercube representation is elucidated. its fault tolerance and modularity [2,3]. There are simple and efficient algorithms for node-to-node communication, broadcasting, and other forms of communication in the hypercube [4]. Several variations of hypercube topology have been developed which further improve some of its properties. These include the twisted cube [5], cube connected cycles [6], bridged hypercube [7], generalized hypercubes [8], and binary orthogonal multiprocessors [9]. Several commercially available machines including Intel, N-Cube, and Thinking Machine as well as the Caltech Cosmic Cub have their communication network configured as a 1383-7621/0165-6074/98/$19.00

This paper presents a new plant-wide modelling methodology for describing the dynamic behaviour of water and sludge lines in WWTPs. The methodology is based on selecting the set of process transformations needed for each specific WWTP to model all unit-process elements in the entire plant. This ''transformation-based'' approach, in comparison with the conventional ''process-based'' approach, does not require the development of specific transformers to interface the resulting unit-process models, facilitates the mass and charge continuity throughout the whole plant and is flexible enough to construct models tailored for each plant under study. As an illustrative example, a plant-wide model for a WWTP that includes carbon removal and anaerobic digestion has been constructed, and the main advantages of the proposed methodology for integrated modelling have been demonstrated. As a final consequence, this paper proposes a rewriting of the existing unitprocess models according to the new standard transformation-based approach for integrated modelling purposes.