Processing Element

In this paper we present a method for mapping streaming applications, with real-time requirements, onto a reconfigurable MPSoC. In this method, the performance of the hardware architecture (the reconfigurable Processing Element, the Network Interface and the Network-on-Chip) is integrated in the performance models of the applications. In this way the performance of the mapped application can be determined at runtime. A predictable NoC (guaranteed bandwidth and bounded latency), a predictable Network Interface and a predictable Processing Element are key requirements for our approach.

Abstract: Reed Solomon (RS) codes have been widely used in a variety of communication systems such as space communication link, digital subscriber loops, and wireless systems as well as in networking communications and magnetic and data storage systems. Continual demand for ever higher data rates makes it necessary to devise very high-speed implementations of RS decoders. This report summarizes the most recent algorithms and architectures used for implementing high-speed RS decoders. The architecture which ...

photometric performances, estimated basing on the stellar populations crucial for understanding the formation and evolution of the Galaxy, are discussed. Performance of the GAIA photometric systems (PSs) is evaluated taking into account their ability to simultaneously determine the main stellar parameters: T eff , log g, [M/H], and E B-V , for a large variety of stars down to V ∼ 20. A sample of the stars (Photometric System Test Targets, PSTTs) applicable for evaluation of the GAIA photometric systems is presented. Definitions of the 1X PS and its accuracies of stellar parameterization are given. We conclude that there is still no photometric system, which would allow to achieve the scientific objectives of the GAIA mission at the limiting magnitude V = 20, proposed to date.

One ofthe goals of current VLSI design is to represent very complex systems on a chip. However, certain physical limitations sometimes exist, such as the number or wira and pins that can be used on IC packages. Yet it is known that fewer wires are needed to carry multipl~valued logic signals, and fewer wires means fewer pins per package. And. secondly. using multiple-valued logic, bit density of stored data in memory can be significantly raised by increasing the number of bits per memory cell. Target applications of particular interest for VLSI implementations are those whose wmplexity is great. either (a) in terms of the number of labour-intensive operations that must be performed per unit time or (b) in terms of the amount of data that must be stored or communicated to accommodate such operations. Some examples of applications which could easily fall into this target area are computer graphics, robotics, and picture processing. Multiple-valued logic can be introduced when it comes time to implement these applications. This paper describes how common picture processing functions can be designed to advantage by using multiple-valued logic.

In this paper, we present a Mirroring Neural Network architecture to perform non-linear dimensionality reduction and Object Recognition using a reduced lowdimensional characteristic vector. In addition to dimensionality reduction, the network also reconstructs (mirrors) the original high-dimensional input vector from the reduced low-dimensional data. The Mirroring Neural Network architecture has more number of processing elements (adalines) in the outer layers and the least number of elements in the central layer to form "converging-diverging" shape in its configuration. Since this network is able to reconstruct the original image from the output of the innermost layer (which contains all the information about the input pattern), these outputs can be used as object signature to classify patterns. The network is trained to minimize the discrepancy between actual output and the input by back propagating the mean squared error from the output layer to the input layer. After successfully training the network, it can reduce the dimension of input vectors and mirror the patterns fed to it. The Mirroring Neural Network architecture gave very good results on various test patterns.

The Instruction-Set extension problem has been one of the major topics in the last years and it is the addition of a set of new complex instructions to a given Instruction-Set. This problem in its general formulation requires an exhaustive search of the design space to identify the candidate instructions. This search turns into an exponential complexity of the solution. In this paper we propose an algorithm for the generation of Multiple Input Single Output instructions of variable size which can be directly selected or combined for Instruction-Set extension. Additionally, the algorithm is suitable for inclusion in a design flow for automatic generation of MIMO instructions. The proposed algorithm is not restricted to basic-block level and has linear complexity with the number of processed elements.

The Discrete Wavelet Transform (DWT) is an important operation in applications of digital signal processing. In this paper, we review several traditional DWT implementation approaches, e.g., application-specific integrated circuits, fieldprogrammable gate arrays, digital signal processors, generalpurpose processors, and graphic processors, and discuss their limitations in terms of performance and flexibility. In order to provide both high-performance and flexibility, we propose a new approach, namely a parallel architecture exploiting the collaboration of reconfigurable processing elements in grid computing. Grid computing can exploit the task level parallelism to execute the 2D DWT. In addition, reconfigurable computing offers a flexible platform and can be used as hardware accelerators. We mapped the DWT in a grid. Our experimental results show that speedups of up to 4.1x can be achieved.

In this paper, we present a runtime memory allocation algorithm, that aims to substantially reduce the overhead caused by shared-memory accesses by allocating memory directly in the local scratch pad memories. We target a heterogeneous platform, with a complex memory hierarchy. Using special instrumentation, we determine what memory areas are used in functions that could run on different processing elements, like, for example a reconfigurable logic array. Based on profile information, the programmer annotates some functions as candidates for accelerated execution. Then, an algorithm decides the best allocation, taking into account the various processing elements and special scratch pad memories of the the heterogeneous platform. Tests are performed on our prototype platform, a Virtex ML410 with Linux operating system, containing a PowerPC processor and a Xilinx FPGA, implementing the MOLEN programming paradigm. We test the algorithm using both state of the art H.264 video encoder as well as other synthetic applications. The performance improvement for the H.264 application is 14% compared to the software only version while the overhead is less than 1% of the application execution time. This improvement is the optimal improvement that can be obtained by optimizing the memory allocation. For the synthetic applications the results are within 5% of the optimum. 1

Reliability of a distributed processing system is an important design parameter that can be described in terms of the reliability of processing elements and communication links and also of the redundancy of programs and data files. The traditional terminal-pair reliability does not capture the redundancy of programs and files in a distributed system. Two reliability measures are introduced which are distributed program reliability that describes the probability of successful execution of a program requiring cooperation of several computers, and distributed system reliability which is the probability that all the specified distributed programs for the system are operational. These two reliability measures can be extended to incorporate the effects of user sites on reliability. We develop an efficient unified approach based on graph traversal to evaluate the proposed reliability measures. Index Terms-Allocation of files, distributed program, distributed system, file spanning tree, reliability analysis. I. INTRODUCTION Distributed processing involves cooperation among several loosely coupled computers communicating over a subnetwork. Distributed systems provide cost-effective means for resource sharing and extensibility, and obtain potential increases in performance, reliability, and fault tolerance 151, 161, 181, [9], [23], [24]. Performance improvement is possible due to multiple computers cooperatively executing common tasks, and increased reliability is achievable because of the redundancy of resources. Several issues of such systems, namely, process management, load balancing, file management, access control, distributed algorithms, etc., are under widespread investigation 151, [7], [9], 1141-[17], [19], 1201. A distributed program usually requires one or more of the resources such as PE's, data files, etc., for successful execution. For successful completion of a program, the local host, the processing elements having the required files, and the interconnecting links must all be operational. With processing elements and communication links having a certain probability of being operational, there is a certain probability associated with the event that a program can be successfully executed. Also the distribution of data file can affect the overall reliability of the system. Thus, an important problem in distributed system design and analysis is to define and efficiently evaluate various reliability measures as well as estimate the effect of Manuscript

Abstract–Clouds have a critical role in many studies, eg weather-and climate-related studies. However, they represent a source of errors in many applications, and the presence of cloud contamination can hinder the use of satellite data. This requires a cloud detection ...

In recent years, a number of database machines consisting of large numbers of parallel processing elements have been proposed. Unfortunately, there are two main limitations in database processing that prevent a high degree of parallelism; these are the available I/O bandwidth of the underlying storage devices and the concurrency control mechanisms necessary to guarantee data integrity. The main problem with conventional approaches is the lack of a computational model capable of utilizing the potential of any significant number of processing elements and storage devices and, at the same time, preserving the integrity of the database. This paper presents a database model and its associated architecture, which is based on the principles of data-driven computation. According to this model, the database is represented as a network in which each node is conceptually an independent, asynchronous processing element, capable of communicating with other nodes by exchanging messages along the ...

Due to the increasing complexity of scientific models, large-scale simulation tools often require a critical amount of computational power to produce results in a reasonable amount of time. For example, multi-system wireless network simulations involve complex algorithms of traffic balancing and communication control on large geographical areas. Moreover many of these intensive applications are designed for single sequential machines and large sums of money are spent on purchasing powerful servers that can give results in a satisfactory amount of time. The aim of this paper is to introduce a general-purpose tool, dubbed Transparent Remote Execution (TREx), which avoids resorting to expensive servers by providing a cost effective, high performance, distributed solution. TREx is a daemon that dynamically exploits idle operational in-use workstations. Based on elaborate rules of computational resource management, this daemon permits a master to scan workstations within a predefined subnetwork and share the workload among the least occupied processing elements. It also provides a clear framework for parallelization that applications can exploit. By providing a simple way of federating computational resources, such a framework could drastically reduce hardware investments.

Due to the increasing complexity of scientific models, large-scale simulation tools often require a critical amount of computational power to produce results in a reasonable amount of time. For example, multi-system wireless network simulations involve complex algorithms of traffic balancing and communication control on large geographical areas. Moreover many of these intensive applications are designed for single sequential machines and large sums of money are spent on purchasing powerful servers that can give results in a satisfactory amount of time. The aim of this paper is to introduce a general-purpose tool, dubbed Transparent Remote Execution (TREx), which avoids resorting to expensive servers by providing a cost effective, high performance, distributed solution. TREx is a daemon that dynamically exploits idle operational in-use workstations. Based on elaborate rules of computational resource management, this daemon permits a master to scan workstations within a predefined subnetwork and share the workload among the least occupied processing elements. It also provides a clear framework for parallelization that applications can exploit. By providing a simple way of federating computational resources, such a framework could drastically reduce hardware investments.

The invention of ever faster and more complex computers makes more and more applications of di-gital signal processing possible. And in turn, new application areas require increasingly more compu-tational power. One of the most computationally in-tensive areas is that of ( ...

The study of C-enhanced metal poor stars with s-process elements overabundances offers a chance of testing the AGB models at low metallicity and constrain the nucleosynthesis codes. We analyzed a total of 13 C-enhanced metal poor stars, of which 12 turned out to be s-process enriched. The combination of our results with the analyses already published in the literature allows to highlight the discrepancies present between the current state of the art AGB low metallicity models, suggesting that they are still lacking some ingredient.

We provide a high-dispersion line-by-line abundance analysis of Ðve red horizontal-branch (HB) stars in the extremely metal-rich Galactic globular cluster NGC 6553. These red HB stars are signiÐcantly hotter than the very cool stars near the tip of the giant branch in such a metal-rich globular cluster, and hence their spectra are much more amenable to an abundance analysis than would be the case for red giants. We Ðnd that the mean [Fe/H] for NGC 6553 is [0.16 dex, comparable to the mean abundance in the Galactic bulge found by McWilliam & Rich and considerably higher than that obtained from an analysis of two red giants in this cluster by Barbuy and coworkers. The relative abundance for the bestdetermined a-process element (Ca) indicates an excess of a-process elements of about a factor of 2. The metallicity of NGC 6553 reaches the average of the Galactic bulge and of the solar neighborhood.

This paper presents the chemical abundance analysis of a sample of 27 red giant stars located in 4 popolous intermediate-age globular clusters in the Large Magellanic Cloud, namely NGC 1651, 1783, 1978 and 2173. This analysis is based on high-resolution (R∼47000) spectra obtained with the UVES@VLT spectrograph. For each cluster we derived up to 20 abundance ratios sampling the main chemical elemental groups, namely light odd-Z, α, iron-peak and neutron-capture elements. All the analysed abundance patterns behave similarly in the 4 clusters and also show negligible star-to-star scatter within each cluster. We find [Fe/H]=-0.30±0.03, -0.35±0.02, -0.38±0.02 and -0.51±0.03 dex for NGC 1651, 1783, 1978 and 2173, respectively. 1 Based on observations obtained at Paranal ESO Observatory under proposal 072.D-0337(A), 072.D-0342(A) and 074.D-0369(A).

Parallel computing is currently the dominating architecture in embedded systems. Concurrency improves the performance of the system rather without increasing the clock speed which affects the power consumption of the system. However, concurrency needs to be exploited in order to improve the system performance in different applications environments. Multimedia applications (real-time conversational services such as video conferencing, video phone, etc.) have many new features that require complex computations compared to previous video coding standards. These applications have a challenging workload for future multiprocessors. Exploiting parallelism in multimedia applications can be done at data and functional levels or using different instruction sets and architectures. In this research, we design new parallel algorithms and mapping methodologies in order to exploit the natural existence of parallelism in multimedia applications, specifically the H.264/AVC video decoder. We mainly target symmetric shared-memory multiprocessors (SMPs) for embedded devices such as ARM Cortex-A9 multicore chips. We evaluate our novel parallel algorithms of the H.264/AVC video decoder on different levels : memory load, energy consumption, and execution time.

Recent progress in processing speeds, network bandwidths, and middleware technologies have contributed towards novel computing platforms, ranging from large-scale computing clusters to globally distributed systems. Consequently, most current computing systems possess different types of heterogeneous processing resources. Entering into the peta-scale computing era and beyond, reconfigurable processing elements such as Field Programmable Gate Arrays (FPGAs), as well as forthcoming integrated hybrid computing cores, will play a leading role in the design of future distributed systems. Therefore, it is important to develop simulation tools to measure the performance of reconfigurable processors in the current and future distributed systems. In this paper, we propose the design of a simulation framework to investigate the performance of reconfigurable processors in distributed systems. The framework incorporates the partial reconfigurable functionality to the reconfigurable nodes. Depending on the available reconfigurable area, each node is able to execute more than one task simultaneously. Furthermore as a case study, we present a simple task scheduling algorithm to verify the functionality of the simulation framework. The proposed algorithm supports the scheduling of tasks on partially reconfigurable nodes. The simulation results are based on various experiments and they provide a comparison between full (one node-one task mapping) and partial (one node-multiple tasks mapping) configuration of the nodes, for the same set of parameters in each simulation run. Results suggest that the average wasted area per task is less as compared to the full configuration, verifying the functionality of the simulation framework.

This thesis investigates a new protocol, iFlame, designed to provide highly scalable, distributed, real-time communication systems for the Internet. Scalabilityisachieved by using a client-oriented model rather than a more traditional server-centric one. The protocol specifies that servers maintain the locations of clients, but transactions are committed in a client-to-client fashion. iFlame is unique because it requires each client to be responsible for handling the load associated with the transactions it initiates. The claims of the protocol are demonstrated in an implementation called the iFlame Message System which combines the ability to send audio, video, text, and other MIME-encapulated data with dynamic client configuration via the Tcl/Tk scripting language. The system achieved several goals: scalability, efficiency, portability, and concurrency.

This paper describes a multi-layer maze routing accelerator which uses a two-dimensional array of processing elements (PEs) implemented in an FPGA. Routing for an L-layer N X N grid is performed by an array of N X N PEs that time-multiplex each layer over the array. This accelerates the classic Lee Algorithm from O(L X d 2) in software to O(L X d). Each PE can be implemented in 32 look up tables (LUTs) in a Xilinx Virtex-II FPGA, which makes possible routing arrays that are large enough to support detailed routing for VLSI. Cycle measurements show a speedup of 50-75X over a 2.54GHZ Pentium 4 for a 4-layer 8 X 8 array and 93X for a 4-layer 16 X 16 array.

More and more parallel and distributed systems (clusters, grid and global computing) are available all over the world, opening new perspectives for developers of a large range of applications including data mining, multi-media, and bio-computing. However, this very large potential of computing power remains unexploited to a large degree, mainly due to the lack of adequate and efficient software tools for managing the resources. Scheduling problems address the allocation of those resources over time to perform tasks being parts of processes and are the key components in resource management. As processors are the source of computing power of parallelism, it is crucial to carefully managing them in order to achieve a high efficiency of parallel systems. In most new parallel architectures and distributed platforms, the processors or machines are spatially distributed and communicate via various kinds of interconnections. Therefore, the communication medium is another important resource that must be considered during scheduling. New parameters like heterogeneity, the hierarchical character of memory, versatility of the context, and large scale computing should be taken into account as well. As conventional models and techniques cannot always be used, it is necessary to propose, implement and validate new approaches. Therefore, the classical topic of Scheduling and Load Balancing remains very active in the perspective of new parallel and distributed systems. The subjects presented in Topic 3 cover all aspects related to scheduling and load-balancing including applications, system level techniques, theoretical foundations and practical tools. Some new trends and emerging models are also presented and discussed. There were 31 papers submitted to this topic. Each submitted paper has been reviewed by 4 reviewers, and finally 11 papers were chosen to be included into the final program. They reflect the good and necessary synergy between theoretical approaches (models, analysis of algorithms, complexity, approximability results, multi-criteria analysis) and practical realizations and tools (new methods, simulation results, actual experiments, specific tuning for an application). Finally, we would like to express our thanks to our colleagues, experts in the fields, who helped in the reviewing process.

Discourse markers are verbal and non-verbal devices that mark transition points in communication. They presumably facilitate the construction of a mental representation of the events described by the discourse. A taxonomy of these relational markers is one important beginning in investigations of language use. While several taxonomies of coherence relations have been proposed for monolog, only a few have been proposed for dialog. This paper presents a taxonomy of between-turn coherence relations in dialog and discusses several issues that arise out of constructing such a taxonomy. A large number of discourse markers was sampled from the Santa Barbara Corpus of Spoken American English. Two judges substituted each type of these markers for all other markers. This extensive substitution test determined whether hyponymous, hypernymous and synonymous relations existed between the markers from this corpus of dialogs. Evidence is presented for clustering coherence relations into four categories: direction, polarity, acceptance and empathics.

The failure of some national projects AXES to expected results. According to experts one of the reasons is the lack of adequate theoretical apparatus for generating high-branching processes, unjustified detraction of opportunities enumerative models representative of AXES, which have their own laws paralleling computing, can not be reduced to algorithmic rules. This fact determines the need to develop innovative approaches to problem solving and organization of AXES interrelated levels of system design symbolic computation, from the linguistic level to the appropriate software and appropriate hardware level.

Cyclops is a new architecture for high performance parallel computers being developed at the IBM T. J. Watson Research Center. The basic cell of this architecture is a single-chip SMP system with multiple threads of execution, embedded memory, and integrated communications hardware. Massive intra-chip parallelism is used to tolerate memory and functional unit latencies. Large systems with thousands of chips can be built by replicating this basic cell in a regular pattern. In this paper we describe the Cyclops architecture and evaluate two of its new hardware features: memory hierarchy with flexible cache organization and fast barrier hardware. Our experiments with the STREAM benchmark show that a particular design can achieve a sustainable memory bandwidth of 40 GB/s, equal to the peak hardware bandwidth and similar to the performance of a 128-processor SGI Origin 3800. For small vectors, we have observed in-cache bandwidth above 80 GB/s. We also show that the fast barrier hardware can improve the performance of the Splash-2 FFT kernel by up to 10%. Our results demonstrate that the Cyclops approach of integrating a large number of simple processing elements and multiple memory banks in the same chip is an effective alternative for designing high performance systems.

As the main scope of mobile embedded systems shifts from control to data processing tasks high performance demand and limited energy budgets are often seen conflicting design goals. Heterogeneous, adaptive multicore systems are one approach to meet these challenges. Thus, the importance of multicore FPGAs as an implementation platform steadily grows. However, efficient exploitation of parallelism and dynamic runtime reconfiguration poses newchallenges for application software developement. In this paper the implementation of avirtualization layer between applications and the multicore FPGA is described. This virtualization allows at ransparent runtime-reconfiguration of the underlying system for adaption to changing system environments. The parallel application does not see the underlying, even heterogeneous multicore system. Manyo ft he requirements for an adaptive FPGA-realization are met by the SDVM, the scalable dataflow-drivenvirtual machine. This paper describes the concept of the FPGA firmware based on areimplementation and adaptation of the SDVM.

Context. Substellar objects have extremely long life spans. The cosmological consequence for older objects are low abundances for heavy elements, which in turn results in a wide distribution of objects over metallicity, hence over age. Within their cool atmosphere, dust clouds become a dominant feature, affecting the opacity and the remaining gas phase abundance of heavy elements. Aims. We investigate the influence of the stellar metallicity on the dust formation in substellar atmospheres and on the dust cloud structure and its feedback on the atmosphere. This work has implications for the general questions of star formation and of dust formation in the early universe. Methods. We utilise numerical simulations to solve a set of moment equations to determine the quasi-static dust cloud structure (Drift). These equations model the nucleation, the kinetic growth of composite particles, their evaporation, and the gravitational settling as a stationary dust formation process. Element conservation equations augment this system of equations by including the element replenishment by convective overshooting. The integration with an atmosphere code (Phoenix) allows determination of a consistent (T, p, v conv)-structure (T-local temperature, p-local pressure, v conv-convective velocity), hence, to calculate synthetic spectra. Results. A grid of Drift-Phoenix model atmospheres was calculated for a wide range of metallicity, [M/H] ∈ [+0.5, −0.0, −0.5, ..., −6.0], to allow for systematic study of atmospheric cloud structures throughout the evolution of the universe. We find dust clouds in even the most metal-poor ([M/H] = −6.0) atmosphere of brown dwarfs. Only the most massive among the youngest brown dwarfs and giant gas planets can resist dust formation. For very low heavy element abundances, a temperature inversion develops that has a drastic impact on the dust cloud structure. Conclusions. The combination of metal depletion by dust formation and the uncertainty of interior element abundances makes the modelling of substellar atmospheres an intricate problem in particular for old substellar objects. We furthermore show that the dust-togas ratio does not scale linearly with the object's [M/H] for a given effective temperature. The mean grain sizes and the composition of the grains change depending on [M/H], which influences the dust opacity that determines radiative heating and cooling, as well as the spectral appearance.

Error diffusion dithering is a technique that is used to represent a grayscale image on a printer, a computer monitor or other bi-level displays. For a number of years it was believed that error diffusion algorithms can not be parallelized. On this paper we present a simple error-diffusion parallel algorithm that can be easily implemented on parallel computers that contain linear arrays of processing elements. It can also be implemented easily on specialized hardware. One of the advantages of our algorithm is its low implementation cost, its scalability, and its ability to benefit from standard fault-tolerance techniques.

Elementary features are detected by calculating the number of objects inside partly overlapping windows fixed in an image plane. Each windowns contents is processed by a separate processing element (PE) on a SIMD grid or pyramid architecture. Two neighboring feature chunks are merged by adjacent PEs, and the merged &ature chunks are joined in each next lth parallei step by every 21 tb PE possessing complementary and adjacent feature. The shape coding terminates if a complete set of features (such as curve bounds, tips, corners, segments, regions forks and junctions) making a whole object meet together on one PE. This complete set is defined and proved to be sufficient to terminate the shape coding. Hierarchy of elementary features for a merging process is established to recognize object bounds and more primitive features first to have a complete feature set adequate for consideration by the termination condition at a given level of paralleI image recognition (i.e,, primal sketch, 2½D sketch and 3D world model). The approach has the property of mapping of image segments directly into phrases and English sentences.

In this paper a regular bidirectional linear systolic array (RBLSA) for computing all-pairs shortest paths of a given directed graph is designed. The obtained array is optimal with respect to a number of processing elements (PE) for a given problem size. The execution time of the array has been minimized. To obtain RBLSA with optimal number of PEs, the accommodation of the inner computation space of the systolic algorithm to the projection direction vector is performed. Finally, FPGAbased reprogrammable systems are revolutionizing certain types of computation and digital logic, since as logic emulation systems they offer some orders of magnitude speedup over software simulation; herein, a FPGA realization of the RBLSA is investigated and the performance evaluation results are discussed.

This paper presents a scale and rotation invariant face detection system. The system employs a hierarchical neural network, called SICoNNet, whose processing elements are governed by the nonlinear mechanism of shunting inhibition. The neural network is used as a face/nonface classifier that can handle in-plane rotated patterns. To train the network as a rotation invariant face classifier, an enhanced bootstrap training technique is developed, which prevents bias towards the nonface class. Furthermore, a multi-resolution processing is employed for scale invariance: an image pyramid is formed through subsampling and face detection is performed at each scale of the pyramid using an adaptive threshold. Evaluated on the benchmark CMU rotated face database, the proposed face detection system outperforms some of the existing rotation invariant face detectors; it has fewer false positives and higher detection accuracy.

Increasing on-chip wire delay along with the distributed nature of processing elements, makes instruction scheduling for tiled dataflow architectures very crucial. Our analysis reveals that careful placement of frequently executed sections of applications, and dynamic resource contention tracking can significantly improve the performance of the application. The former reduces the operand network latency, while the latter reduces stalls due to contention for processing elements. We augment one of the most recent instruction scheduling algorithms-hierarchical instruction scheduling-to better exploit spatial locality between instructions within a loop, thereby reducing expensive communication overhead by 6.5% and increasing average IPC by 5.13%. Secondly, in the presence of conditional branches and variable latency memory instructions, estimating resource contention, at compile time, is not only complex but also imperfect. We suggest dynamic tracking of contending instructions, and their re-location, once a contention threshold is exceeded. Results showed that dynamic contention tracking reduced the average ALU conflicts by 23%, thereby improving the average IPC by 14.22%. Combined together, these augmentations improve the average IPC by 19.39% and over 30% for some benchmarks.

The MULTIPLUSproject aims at the development of a modular parallel architecture suitable for the study of several aspects of parallelism in both true shared memory and virtual shared memory environments. The MULTIPLUS architecture is able to support up to 1024 Processing Elements based on SPARC microprocessors. The MULPLIX Unix-like operating system offers a suitable parallel programming environment for the MULTIPLUS architecture by providing facilities for the creation of threads, the allocation of private and shared memory space and the efficient use of synchronization primitives. After presenting the main features of the MULTIPLUS architecture and of the MULPLX operating system, the paper describes in detail the design and the implementation of the three MULTIPLUS architecture basic hardware modules: the Processing Element, the Multistage Interconnection Network and the I/O Processor. In addition, the defkition of the MULPLIX parallel programming primitives is discussed and their use is illustrated through an example. Finally, future directions in the development of the MULTIPLUS research project are commented.

In this paper, we describe the challenges of prototyping a reference application on System S, a distributed stream processing middleware under development at IBM Research. With a large number of stream PEs (Processing Elements) implementing various stream analytic algorithms, running on a large-scale, distributed cluster of nodes, and collaboratively digesting several multi-modal source streams with vastly differing rates, prototyping a reference application on System S faces many challenges. Specifically, we ...

We approach the construction of design methodologies for on-chip multiprocessor platforms, with the focus on the SegBus, a segmented bus platform. We study how applications can be mapped on such distributed architecture and show how to build the concrete level software procedures that will coordinate the control flow on the platform. The approach employs models developed in the Matlab-Simulink environment considering also a unified representation of both platform and application. The running example is represented by the H.264 encoder. Allocation of processing elements on the platform, structure and functionality and the eventual control code for arbiters are the main topics described here.

We present chemical abundances obtained by fitting synthetic spectra to the FEROS data of 12 C-J stars, normal and silicate carbon one. The Li and 13C abundance, as well as the s-process elements abundance indicates no evidence of a diferent mechanism of formation between the two kinds of C-J stars. We also studied the α elements, and that suggests a scenario that put the carbon C-R stars as a possible progenitor of the beither C-J stars. We made also available a study of the radial velocity of some stars of the sample calculated at different epochs. That allowed us to make some discussion about the probable binary system of some silicon C-J carbon stars. Based on these abundances and radial velocities, we discuss possible evolutive sequences for the C-J.

Most parallel computations require the exchange of data between processing elements. One of important basic communication operations is all-reduce, a variation of the reduction operation. This paper presents an all-reduce communication operation scheme using all-to-all broadcast communication pattern. All-to-all broadcast is the operation in which each processor sends its message to all other processors, and receives messages from all other processors in the system. In this paper, we develop an efficient all-reduce operation scheme in a star network topology with the single-port communication capability. Communication time is compared against known broadcasting schemes to verify the efficiency of the suggested scheme.

Constraint propagation algorithms present inherent parallelism. Each constraint behaves as a concurrent process triggered by changes in the store of variables, updating the store in its turn. There is an inherent sequentiality, a s w ell, since a constraint m ust be executed only as the consequence of a previous execution of another constraint. We h a v e developed di erent parallel execution models of constraint propagation for MIMD distributed memory machines. We have adopted the indexical scheme, an adequate approach t o a c hieve consistency for n-ary constraints. The proposed models arise from two techniques, dynamic and static, for scheduling constraint executions assignment of constraint executions to processing elements. In the static scheduling models the constraint

Increasing on-chip wire delay along with the distributed nature of processing elements, makes instruction scheduling for tiled dataflow architectures very crucial. Our analysis reveals that careful placement of frequently executed sections of applications, and dynamic resource contention tracking can significantly improve the performance of the application. The former reduces the operand network latency, while the latter reduces stalls due to contention for processing elements. We augment one of the most recent instruction scheduling algorithms -hierarchical instruction scheduling -to better exploit spatial locality between instructions within a loop, thereby reducing expensive communication overhead by 6.5% and increasing average IPC by 5.13%. Secondly, in the presence of conditional branches and variable latency memory instructions, estimating resource contention, at compile time, is not only complex but also imperfect. We suggest dynamic tracking of contending instructions, and their re-location, once a contention threshold is exceeded. Results showed that dynamic contention tracking reduced the average ALU conflicts by 23%, thereby improving the average IPC by 14.22%. Combined together, these augmentations improve the average IPC by 19.39% and over 30% for some benchmarks.

We report on the progress of an experimental research program to demonstrate the feasibility of multiplexing several holographic optical elements (HOEs) in a single film. Named the Shared Aperture Diffractive Optical Element (ShADOE), it is equivalent to ...

Due to the significant growth of link speeds, amount of data that should be stored on router line cards are rapidly increasing. Therefore, a large number of memory modules are required for packet storage. In addition, a high performance interconnection network on line cards is strongly needed for inter-communication between processing elements and memory modules. In this paper we propose a new interconnection network, known as hyper node torus that can support larger number of nodes compared to other topologies, such as common torus network on a limited area. Simulation results show that hyper node torus can sustain more traffic load, and also it has higher throughput than the torus network under different traffic loads. As a result, it has better scalability and higher performance for using in high-speed packet processors.

Coarse-grain reconfigurable architectures consist of a large number of processing elements (PEs) connected together in a network. For mapping applications to such coarse-grain architectures, we present an algorithm that takes into account the number and delay of interconnects. This algorithm maps operations to PEs and data transfers to interconnects in the fabric. We explore three different cost functions that largely affect the performance of the scheduler: (a) priority of the operations, (b) affinity of operations to PEs based on past mapping decisions, and (c) connectivity between the PEs. Our results show that a priority-based operation cost function coupled with a connectivity-based PE cost function gives results that are close to the lower bounds for a range of designs.