Optimization of Analog Integrated Circuits

In this paper, the problem of sizing an Operational Transconductance Amplifier (OTA) is addressed. The Pareto front is introduced as a useful analysis concept in order to explore the design space of such analog circuit. A genetic algorithm (GA) is employed to automatically detect this front in a process that efficiently finds optimal parameterizations and their corresponding values in an aggregate fitness space. Measures of the amplifier's transconductance, slew rate, linear range and input capacitance are used as fitness functions, since the problem is treated as a multi-objective optimization task. Finally, simulation results are presented, using a standard 0.5 μm CMOS technology.

The current paper is composed of two parts. In the first part, we present the analytical and semi-analytical models to estimate mold filling time in Liquid Composite Molding processes. Their accuracy and efficiency are examined through a comparison with Control Volume / Finite Element simulations. In the second part, we propose an integrated optimization of structural performance and manufacturing cost. The simple models are incorporated into the optimization procedure to investigate the couplings between structural performance and manufacturing costs. By considering manufacturing at the early stage of product design, excessive manufacturing costs which sometimes arise for the best structural performance can be avoided. In order to be cost effective, different manufacturing routes need to be selected depending on part dimensions, loading conditions and design criteria.