Optimization of Analog Integrated Circuits

The current paper is composed of two parts. In the first part, we present the analytical and semi-analytical models to estimate mold filling time in Liquid Composite Molding processes. Their accuracy and efficiency are examined through a comparison with Control Volume / Finite Element simulations. In the second part, we propose an integrated optimization of structural performance and manufacturing cost. The simple models are incorporated into the optimization procedure to investigate the couplings between structural performance and manufacturing costs. By considering manufacturing at the early stage of product design, excessive manufacturing costs which sometimes arise for the best structural performance can be avoided. In order to be cost effective, different manufacturing routes need to be selected depending on part dimensions, loading conditions and design criteria.

Over the years, the installed capacity of offshore wind turbines is increasing rapidly. However, the Levelized Costs Of Energy (LCOE) is still higher than the LCOE of traditional energy production methods like nuclear power or energy from coals or gas. This research focuses on a further decrease of the LCOE, by minimizing the mass of a monopile support structure of a wind turbine. This is done in a so called integrated way: Optimizing the tower and the foundation together. The design variables used in this research are the wall thickness and the diameter of every +-3 meter section. These can even be cylindrical or conical. To simplify the problem, a parametrization of the designs is used, which reduces the design variables from around 180 to 28. This is checked with existing designs. Due to the interaction between mostly the first eigenfrequency and eigenmode, the diameter and the waves, it is expected that several local optima exist. Therefore, the proposed optimization strategy is...

We study the integration of real-time traffic management and train control by using mixed-integer nonlinear programming (MINLP) and mixed-integer linear programming (MILP) approaches. Three innovative integrated optimization approaches for real-time traffic management that inherently include train control are developed to deliver both a train dispatching solution (including train routes, orders, departure and arrival times at passing stations) and a train control solution (i.e., train speed trajectories). Train speed is considered variable, and the blocking time of a train on a block section dynamically depends on its real speed. To formulate the integrated problem, we first propose an MINLP problem (P NLP), which is solved by a two-level approach. This MINLP problem is then reformulated by approximating the nonlinear terms with piecewise affine functions, resulting in an MILP problem (P PWA). Moreover, we consider a preprocessing method to generate the possible speed profile options for each train on each block section, one of which is further selected by a proposed MILP problem (P TSPO) with respect to safety, capacity, and speed consistency constraints. This problem is solved by means of a custom-designed two-step approach, in order to speed up the solving procedure. Numerical experiments are conducted using data from the Dutch railway network to comparatively evaluate the effectiveness and efficiency of the three proposed approaches with heterogeneous traffic. According to the experimental results, the MILP approach (P TSPO) yields the best overall performance within the required computation time. The experimental results demonstrate the benefits of the integration, i.e., train delays can be reduced by managing train speed.

We study the integration of real-time traffic management and train control by using mixed-integer nonlinear programming (MINLP) and mixed-integer linear programming (MILP) approaches. Three innovative integrated optimization approaches for real-time traffic management that inherently include train control are developed to deliver both a train dispatching solution (including train routes, orders, departure and arrival times at passing stations) and a train control solution (i.e., train speed trajectories). Train speed is considered variable, and the blocking time of a train on a block section dynamically depends on its real speed. To formulate the integrated problem, we first propose an MINLP problem (P NLP), which is solved by a two-level approach. This MINLP problem is then reformulated by approximating the nonlinear terms with piecewise affine functions, resulting in an MILP problem (P PWA). Moreover, we consider a preprocessing method to generate the possible speed profile options for each train on each block section, one of which is further selected by a proposed MILP problem (P TSPO) with respect to safety, capacity, and speed consistency constraints. This problem is solved by means of a custom-designed two-step approach, in order to speed up the solving procedure. Numerical experiments are conducted using data from the Dutch railway network to comparatively evaluate the effectiveness and efficiency of the three proposed approaches with heterogeneous traffic. According to the experimental results, the MILP approach (P TSPO) yields the best overall performance within the required computation time. The experimental results demonstrate the benefits of the integration, i.e., train delays can be reduced by managing train speed.

The current paper is composed of two parts. In the first part, we present the analytical and semi-analytical models to estimate mold filling time in Liquid Composite Molding processes. Their accuracy and efficiency are examined through a comparison with Control Volume / Finite Element simulations. In the second part, we propose an integrated optimization of structural performance and manufacturing cost. The simple models are incorporated into the optimization procedure to investigate the couplings between structural performance and manufacturing costs. By considering manufacturing at the early stage of product design, excessive manufacturing costs which sometimes arise for the best structural performance can be avoided. In order to be cost effective, different manufacturing routes need to be selected depending on part dimensions, loading conditions and design criteria.

In today’s world everything is digitized but nature is analog, so it is necessary to have such a device which converts analog signal into digital and for this analog to digital converter is required. Now a day’s ADC’s require lesser power, better slew rate, high speed and less offset. Performance limiting component for ADC’s are amplifiers and comparators in which comparator is the most important.This paper presents the design of low offset low power dissipation and high speed  comparator. The proposed comparator consists of a preamplifier stage, decision stage and self biased output buffer stage. The proposed design uses a low power current mirror circuitry for providing a highly biased current. The circuit is designed using 90nm CMOS process for a supply voltage of 1V and reference voltage of 0.5V and power consumption is approximately 300?W. Keywords: CMOS Comparator, Current Mirror, Pre Amplifier, Output Buffer

Current mirror is basic building block of amplifier, oscillator and comparator circuit. An ideal current mirror is independent of input power and temperature. The output current is constant mirrored image of input current. In order to avoid wrong equilibrium it must have high output impedance. This can be achieved by using super cascode formation. The single electron coulomb blockade structure provides low voltage operation and scaling of transistor to 10 nm. The Single Electron Transistor (SET) based CM is modeled and analyzed by simulation and the results shows improved performance of CM.

Operational Ttransconductance Amplifier is very popular in analog electronics industry due to its vast applications. Analog integrated circuits have been widely used for high frequency applications. OTA has number of applications like filters, analog multipliers and analog dividers. Double gate MOSFETs (DG-MOSFETs) are strong contenders for nano scale region due its better control over short channel effects. DG-MOSFET can be used in analog circuit applications as a four-terminal device. Back gate bias can be used for better tunability. The double gate based circuits provide additional gains in terms of area, power and speed. This paper presents double gate based OTA which has high gain over a wide bandwidth. The simulation results shows gain of 9.32 dB and bandwidth is 7GHz.The simulations are done using Tanner EDA Software Tool at 90nm technology.

In this paper is presented, for the first time, the design of a single-stage operational transconductance amplifiers (OTA) implemented with Graded-Channel (GC) SOI nMOSFETs. Different design conditions were taken in account such as similar power dissipation, transconductance over drain current ratio and die area. Comparisons with OTA made with conventional SOI transistors are performed showing that the GC OTAs present

In this paper a new 8-bit 50-M sample/s CMOS digital-to-analog converter (DAC) is presented. The circuit employs 9 operational transconductance amplifiers (OTAs) and CMOS transistors as switching circuit. The proposed DAC is simulated using SPICE simulation program with 1.2 µm CMOS technology. Simulation results verify good performance of the circuit.

In this paper, the problem of sizing an Operational Transconductance Amplifier (OTA) is addressed. The Pareto front is introduced as a useful analysis concept in order to explore the design space of such analog circuit. A genetic algorithm (GA) is employed to automatically detect this front in a process that efficiently finds optimal parameterizations and their corresponding values in an aggregate fitness space. Measures of the amplifier's transconductance, slew rate, linear range and input capacitance are used as fitness functions, since the problem is treated as a multi-objective optimization task. Finally, simulation results are presented, using a standard 0.5 µm CMOS technology.

In this paper, the problem of sizing an Operational Transconductance Amplifier (OTA) is addressed. The Pareto front is introduced as a useful analysis concept in order to explore the design space of such analog circuit. A genetic algorithm (GA) is employed to automatically detect this front in a process that efficiently finds optimal parameterizations and their corresponding values in an aggregate fitness space. Measures of the amplifier's transconductance, slew rate, linear range and input capacitance are used as fitness functions, since the problem is treated as a multi-objective optimization task. Finally, simulation results are presented, using a standard 0.5 µm CMOS technology.

In this paper a new 8-bit 50-M sample/s CMOS digital-to-analog converter (DAC) is presented. The circuit employs 9 operational transconductance amplifiers (OTAs) and CMOS transistors as switching circuit. The proposed DAC is simulated using SPICE simulation program with 1.2 μm CMOS technology. Simulation results verify good performance of the circuit.

In this paper, the problem of sizing an Operational Transconductance Amplifier (OTA) is addressed. The Pareto front is introduced as a useful analysis concept in order to explore the design space of such analog circuit. A genetic algorithm (GA) is employed to automatically detect this front in a process that efficiently finds optimal parameterizations and their corresponding values in an aggregate fitness space. Measures of the amplifier's transconductance, slew rate, linear range and input capacitance are used as fitness functions, since the problem is treated as a multi-objective optimization task. Finally, simulation results are presented, using a standard 0.5 μm CMOS technology.