On-chip Interconnection Networks

In the Information Technology era information plays vital role in every sphere of the human life. It is very important to gather data from different data sources, store and maintain the data, generate information, generate knowledge and disseminate data, information and knowledge to every stakeholder. Due to vast use of computers and electronics devices and tremendous growth in computing power and storage capacity, there is explosive growth in data collection. The storing of the data in data warehouse enables entire enterprise to access a reliable current database. To analyze this vast amount of data and drawing fruitful conclusions and inferences it needs the special tools called data mining tools. This paper gives overview of the data mining systems and some of its applications.

The increasing complexity of integrated circuits drives the research of new on-chip interconnection architectures. Networks-on-chip (NoCs) are a candidate architecture to be used in future systems, due to its increased performance, reusability and scalability. A NoC is a set of interconnected switches, with IP cores connected to these switches. Four main components compose a switch: a router, to define a path between input and output switch ports; an arbiter, to grant access to a given port when multiple input requests arrive in parallel; buffers, to store intermediate data, and a flow control module to regulate the data transfer to the next switch. The goal of this work is to compare the performance of four routing algorithms for mesh based packet switching NoCs. Differently from the literature for generic networks, it is shown that deterministic algorithms can be superior to adaptive ones in NoCs.

Silicon interposer technology (“2.5D” stacking)
enables the integration of multiple memory stacks with a
processor chip, thereby greatly increasing in-package memory
capacity while largely avoiding the thermal challenges of 3D
stacking DRAM on the processor. Systems employing interposers
for memory integration use the interposer to provide
point-to-point interconnects between chips. However, these
interconnects only utilize a fraction of the interposer’s overall
routing capacity, and in this work we explore how to take
advantage of this otherwise unused resource.
We describe a general approach for extending the architecture
of a network-on-chip (NoC) to better exploit the additional
routing resources of the silicon interposer. We propose an
asymmetric organization that distributes the NoC across both
a multi-core chip and the interposer, where each sub-network
is different from the other in terms of the traffic types, topologies,
the use or non-use of concentration, direct vs. indirect
network organizations, and other network attributes. Through
experimental evaluation, we show that exploiting the otherwise
unutilized routing resources of the interposer can lead to
significantly better performance.

Multi-Processor Systems-on-Chip (MPSoCs) are increasingly popular in embedded systems. Due to their complexity and huge design space to explore for such systems, CAD tools and frameworks to customize MPSoCs are mandatory. Some academic and industrial frameworks are available to support bus-based MPSoCs, but few works target NoCs as underlying communication architecture. A framework targeting MPSoC customization must provide abstract models to enable fast design space exploration, flexible application mapping strategies, all coupled to features to evaluate the performance of running applications. This paper proposes a framework to customize NoC-based MPSoCs with support to static and dynamic task mapping and C/SystemC simulation models for processors and memories. A simple, specifically designed microkernel executes in each processor, enabling multitasking at the processor level. Graphical tools enable debug and system verification, individualizing data for each task. Practical results highlight the benefit of using dynamic mapping strategies (total execution time reduction) and abstract models (total simulation time reduction without losing accuracy).

We present a novel Partial Virtual channel Sharing (PVS) NoC architecture which reduces the impact of faults on performance and also tolerates faults within the routing logic. Without PVS, failure of a component impairs the fault-free connected components, which leads to considerable performance degradation. Improving resource utilization is key in enhancing or sustaining performance with minimal overhead when faults or overload occurs. In the proposed architecture, autonomic virtual-channel buffer sharing is implemented with a novel algorithm that determines the sharing of buffers among a set of ports. The runtime allocation of the buffers depends on incoming load and fault occurrence. In addition, we propose an efficient technique for maintaining the accessibility of a processing element (PE) to the network even if its router is faulty. Our techniques can be used in any NoC topology and for both, 2D and 3D NoCs. The synthesis results for an integrated video conference application demonstrate 22 % reduction in average packet latency compared to state-of-the-art virtual channel (VC) based NoC architecture. Extensive quantitative simulation has been carried out with synthetic benchmarks. Simulation results reveal that the PVS architecture improves the performance significantly in presence of faults, compared to other VC-based NoC architectures.

As the number of applications and programmable units in CMPs and MPSoCs increases, the Network-on-Chip (NoC) encounters unpredictable, heterogeneous and time dependent traffic loads. This motivates the introduction of adaptive routing mechanisms that balance the NoC's loads and achieve higher throughput compared with traditional oblivious routing schemes. An effective adaptive routing scheme should be based on a global view of the network state. However, most current adaptive routing schemes, following off-chip networks, are based on distributed reactions to local congestion. In this paper we leverage the unique on-chip capabilities and introduce a novel paradigm of NoC centralized adaptive routing. Our scheme continuously monitors the global traffic load in the network and modifies the routing of packets to improve load balancing accordingly. We present a specific design for the case of mesh topology, where XY or YX routes are adaptively selected for each source-destination pair. We show that while our implementation is lightweight and scalable in hardware costs, it outperforms oblivious and distributed adaptive routing schemes in terms of load balancing and average packet delay. †

As the number of modules grows, performance scalability of planar topology Networks-on-Chip (NoCs) becomes limited due to increasing hop-distances, since long paths involve more routers. The growing hop-distance affects both end-to-end network latency and overall network saturation. Hierarchical topologies provide routes with shorter hop-distances and therefore are more adequate for large systems. The introduction of hierarchical NoCs poses new challenges as they should provide the shortest hop-distance for as many as possible source–destination pairs with minimal interference among packets, at the lowest hardware and system costs.

In this paper, a framework for design and dynamic management of hierarchical NoCs is introduced. The design space of hierarchical NoCs is explored under cost and performance constraints. A dynamic management scheme termed DTrD (Dynamic Traffic Distribution) is proposed. DTrD enables to dynamically adapt the routing policy in hierarchical NoCs to varying traffic conditions. Finally, a set of guidelines is formulated for proper design and dynamic control of hierarchical NoCs.

—In multiprocessor system-on-chip (MPSoC), a CPU can access physical resources, such as on-chip memory or I/O devices. Along with normal requests, malevolent ones, generated by malicious processes running in one or more CPUs, could occur. A protection mechanism is therefore required to prevent injection of malicious instructions or data across the system. We propose a self-contained Network-on-Chip (NoC) firewall at the network interface (NI) layer which, by checking the physical address against a set of rules, rejects untrusted CPU requests to the on-chip memory, thus protecting all legitimate processes running in a multicore SoC. To sustain high performance, we implement the firewall in hardware, with rule-checking performed at segment-level based on deny rules. Furthermore, to evaluate its impact, we develop a novel framework on top of gem5 simulation environment , coupling ARM technology and an instance of a commercial point-to-point interconnect from STMicroelectronics (STNoC). Simulation tests include scenarios in which legitimate and malicious processes, running in different CPUs, request access to shared memory. Our results indicate that a firewall implementation at the NI can have a positive effect on network performance by reducing both end-to-end network delay and power consumption. We also show that our coarse-grain firewall can prevent saturation of the on-chip network and performs better than fine-grain alternatives that perform rule checking at page-level. Simulation results are accompanied with field measurements performed on a Zedboard platform running Linux, whereas the NoC Firewall is implemented as a reconfigurable, memory-mapped device on top of AMBA AXI4 interconnect fabric.

As the number of applications and programmable units in CMPs and MPSoCs increases, the Network-on-Chip (NoC) encounters diverse and time dependent traffic loads. This trend motivates the introduction of NoC load-balanced, adaptive routing mechanisms that achieve higher throughput as compared with traditional oblivious routing schemes that are perceived better suited for hardware implementations. However, an efficient adaptive routing scheme should base its decisions on the global state of the system rather than on local or regional congestion signals as is common in current adaptive routing schemes. In this paper we introduce a novel paradigm of NoC centralized adaptive routing, and a specific design for mesh topology. Our scheme continuously monitors the global traffic load in the network and modifies the routing of packets to improve load balancing accordingly. In our specific mesh-based design, XY or YX routes are adaptively selected for each source-destination pair. We show that while our implementation is scalable and lightweight in hardware costs, it outperforms distributed adaptive routing schemes in terms of load balancing and throughput.

We achieved robust bonding of a large area power chip (> 100 mm 2) with sintered Ag joint produced by the electrical current assisted sintering (ECAS) technique operating at low current (1.1 kA) and short sintering time (10 s). Our ECAS-ed Ag joint possessed low thermal resistance (∼0.18 °C/W), high density (89.6%), as well as good static and dynamic electrical properties during switching on and off of the power chip. Our TEM analysis explained that the good electrical and thermal performances of the power chip were attributed to the high density of twins formed in the ECAS-ed nano-Ag joint.

Flip chip nanobonding and interconnect system (NBIS) equipment with high precision alignment has been developed based on the surface activated bonding method for high-density interconnection and MEMS packaging. The 3σ alignment accuracy in the IR transmission system was approximately ±0.2 μm. The performance of the NBIS has been preliminarily investigated through bonding between relatively rough surfaces of copper through silicon vias (Cu-TSVs) and gold-stud bumps (Au-SBs), and smooth surfaces of silicon wafers. The Cu-TSVs of 55 μm diameter and the Au-SBs of 35 μm diameter with ∼6-10 nm surface roughness (RMS) were bonded at room temperature after surface activation using an argon fast atom beam (Ar-FAB) under 0.16 N per bump. Silicon wafers of 50 mm diameter with ∼0.2 nm RMS surface roughness were bonded without heating after surface activation. Void-free interfaces both in Cu-TSV/Au-SB and silicon/silicon with bonding strength equivalent to bulk fracture of Au and silicon, respectively, were achieved. A few nm thick amorphous layers were observed across the silicon/silicon interface that was fabricated by the Ar-FAB. This study in the interconnection and bonding facilitates the required three-dimensional integration on the same surface for high-density electronic and biomedical systems.

The popular hypercube interconnection network has high wiring(VLS1) complexity. The reduced hypercube (RH) is obtained by a uniform reduction in the number of channels for each hypercube node in order io reduce the VLSI complexity. It is known that the RH achieves performance comparable to that of the hypercube, at much lower hardware cost, through hypercube emulation. The reduced complexity of the RH permits the construction of powerful, massively parallel computers. This paper proposes algorithms for data broadcasting and reduction, prefix computation, and sorting on the RH. These operations are fundamental to many parallel algorithms. A worst case analysis of each algorithm is given and compared with that of equivalent algorithms for the hypercube. It is shown that the proposed algorithms for the RH yield performance comparable to that of the hypercube. , and DMI-9500260. 0167-8191/96/$15.00 0 1996 Elsevier Science B.V. All rights reserved SSDZ 0167-8191(96)00008-7 596 S.G. Ziavras, A. Mukherjee /Parallel Computing 22 (1996) 595406

A comprehensive investigation of the surfaces of copper through silicon vias �Cu-TSVs� and gold stud bumps is presented. These vias and stud bumps were bonded at room temperature using a nanobonding and interconnection equipment. The influence of heating on the bonded interface was also studied. In order to achieve an intimate contact between the Au-stud bumps and Cu-TSVs, the stud bumps were flattened under an external force of 20 N before bonding. The surface roughness of the flattened area was improved due to deformation of the bumps. Specimens with high deformation provided better alignment accuracy than those with low deformation. The Cu-TSV surface showed inhomogeneous behavior due to the influence of electroplating and chemical mechanical polishing. Tensile pulling test of the bonded interfaces showed three fractures modes in the bulk of the Au bump and the Au pad. The electrical resistance of the bonded interface was dependent on the surface morphology of the bumps and TSVs, the distance between the bumps and TSVs, the locations of the bumps and TSV with respect to the argon fast atom beams, and the distribution of external force during bonding. Heating at 200 °C for 60 h in air increased the electrical resistance of the bonded interface. This investigation shows that the vertical integration of Au/Cu at room temperature and low bonding force can be applied to three-dimensional interconnections for low cost miniaturized systems.

—In the future almost every consumer electronics device will be connected to an ecosystem of third-party partners providing services such as payment, streaming content, and so on. Present work aims to expose the foundations of a secure environment by ensuring security on the edge devices. MPSoCs are widely used in edge devices due to their capability to execute multiple applications in single-chips. To achieve the targeted security level against physical adversaries, all communications between the MPSoC and its environment must be protected. In an MPSoC multiple processing elements such as CPUs send requests to different on-chip memories. Network-on-chip has been proposed for MPSoC design, aiming at increasing performance and reducing power compared to on-chip buses. Tailoring the NoC to application(s) takes place usually at design-time. The selection of NoC parameter values affects both performance and power, while configuring them unwisely can result in unnecessary area overhead and chip cost. In the present work we concentrate on a commercial interconnect called STNoC from STMicroelectronics. We keep the NoC parameters fixed, and we explore the effects from the variation of other parameters, such as the injection rate of the packets transmitted by the CPUs, and the activation/deactivation of a security mechanism integrated in the network interface of the NoC, for multiple traffic scenarios with each one representing different amount of legal and malicious requests, for different mappings, and for different node setups. Experimental results, reveal the conditions under which the NoC starts experiencing saturation phenomena.

In this paper, we address the performance of MPSoC platforms with homogeneous processing nodes, where the cores generate and consume the large amount of data, thus the system approaches congestion. Mostly, the time dependent media applications are time critical, where traffic must be delivered on time in order to operate properly. Proper task allocation or placement of IP cores at layout time is very important to meet such application requirements. Apart from meeting the application requirements, it also lowers the traffic congestion, power consumption and Average Packet Latency (APL). For task allocation or IP placement, the prioritization criteria has been proposed, which is used in next step to map the application on MPSoC platform. The proposed technique shows significant improvement in system performance and reduction in power consumption. To estimate the efficiency, the video conference encoding application and MPEG4 video encoder were mapped to 5×5 and 4×4 NoC mesh. Up to 11% reduction in power consumption and 20% reduction in APL has been observed as compared to other proposed mapping techniques.

As the number of modules grows, performance scalability of planar topology Networks-on-Chip (NoCs) becomes limited due to the increasing hop-distances. The growing hopdistance affects both end-to-end network latency and overall network saturation. Hierarchical topologies provide better traffic hop distance and therefore are more adequate for large systems. However, the introduction of hierarchical NoCs offers new challenges. In particular, how to distribute the traffic among the hierarchy levels to effectively utilize the hierarchical structure.

Networks  on  chip  (NoCs)  are  efficient  infrastructures  to  enable  communication  among  the  large  number  of IPs  that  compose  modern  systems  on  chip  (SoCs).  However, even if recent technologies allow the construction of such complex  systems,  they  increase  the  cost  and  effort  of  designing  a correct  and  efficient  chip-wide  clock  delivery  network  for  a fully synchronous system. Asynchronous NoCs are an attractive alternative, as they allow each IP to operate on an independent clock domain, eliminating the need for a global clock network and producing  globally  asynchronous  locally  synchronous  (GALS) systems. This paper details the design of a low power NoC router that is asynchronous and employs a transition-signaling bundled-data  design  style.  Results  show  reductions  of  27%  in  energy consumption  when  compared  to  a  similar  synchronous  router.

Network on chip architecture provides a way to design complex integrated circuits with an objective to reduce connection issues, design productivity, and energy utilization. Network performance of a network is calculated by various factors but throughput is the most dominant characteristic for measuring network performance. So, this work includes investigation of various NoC topologies and analysis is done on basis of average throughput and average latency for ensuring network performance.

Network-on-Chip (NoC) is known as a scalable and high performance interconnect in Systems-on-Chip (SoCs) with multiple processing elements (PEs). Recently, the design paradigm of SoCs has shifted from static to dynamic run-time reconfigurable system. In these systems, the PEs can be loaded/unloaded on demand. Therefore, the NoC should be able to adapt as quickly as possible to the changes to maintain the performance of the systems. In this work, we present a non-intrusive runtime reconfigurable time-division-multiplexed circuit-switched NoC, XNoC, which offers the following benefits (1) it switches between different routes within a predictable latency that is strictly determined by the length of the route and the number of time slots; (2) the configuration process can be masked effectively by overlapping with communication and (3) the multi-cast service is supported with aggregate feedback from sink nodes. We propose an XSwitch which requires 3.5X less resource than the conventional switch with similar features. The overall resource cost of XNoC is also smaller than the most known NoC and the clock timing is up to 50% better. We also propose a novel distributed control plane to accelerate the reconfiguration process and to improve the scalability of NoC. The achieved reconfiguration speedup compared to the centralized control unit is up to 7.6X in certain conditions. On average, it takes only 74 clock cycles to activate a 12-hop connection.

The architecture of networks on chip (NOC) highly affects the overall performance of the system on chip (SOC). A new topology for chip interconnection called Torus connected Rings is proposed. Due to the presence of multiple disjoint paths between any source and destination pair, this topology exhibits high fault tolerance capability. The proposed routing method can tolerate faults adaptively. TCR is simple in design and highly scalable. The detailed design and topological parameters are compared with alternate topologies.

A evolução das redes de computadores deve levar à uma arquitetura onde soluções heterogêneas para o HW/SW deverão ser conectáveis e interoperáveis de maneira à viabilizar as Rede Corporativas. Neste contexto, os equipamentos de interconexão de redes desempenham um papel importante e o conhecimento de suas características e de suas aplicabilidades é fundamental para o projetista e o gerente de redes. Neste artigo, são introduzidos a conceituação básica de uma Rede Corporativa e dos equipamentos de interconexão de redes, juntamente com uma discussão sobre o escopo das aplicações cobertas pelos mesmos.

The design of more complex systems becomes an increasingly difficult task because of different issues related to latency, design reuse, throughput and cost that has to be considered while designing. In Real-time applications there are different communication needs among the cores. When NoCs (Networks on chip) are the means to interconnect the cores, use of some techniques to optimize the communication are indispensable. From the performance point of view, large buffer sizes ensure performance during different applications execution. But unfortunately, these same buffers are the main responsible for the router total power dissipation. Another aspect is that by sizing buffers for the worst case latency incurs in extra dissipation for the mean case, which is much more frequent. Reconfigurable router architecture for NOC is designed for processing elements communicate over a second communication level using direct-links between another node elements. Several possibilities to use the router as additional resources to enhance complexity of modules are presented. The reconfigurable router is evaluated in terms of area, speed and latencies. The proposed router was described in VHDL and used the ModelSim tool to simulate the code. Analyses the average power consumption, area, and frequency results to a standard cell library using the Design Compiler tool. With the reconfigurable router it was possible to reduce the congestion in the network, while at the same time reducing power dissipation and improving energy.

The Network on Chip (NoC) has developed as a substitute for wired or interconnection network for System on Chip (SoC). It acts as a way to reduce existing problems of interference, bandwidth desideratum, and potential and makes clock distribution work easier. The performance of the network can be evaluated by numerous factors but latency and throughput are primary characteristics of measurement. So, this paper contains study and evaluation of various existing topologies and their operational evaluation is done on the basis of latency and throughput.

This study proposes a new router architecture to improve the performance of dynamic allocation of virtual
channels. The proposed router is designed to reduce the hardware complexity and to improve power and
area consumption, simultaneously. In the new structure of the proposed router, all of the controlling
components have been implemented sequentially inside the allocator router modules. This optimizes
communications between the controlling components and eliminates the most of hardware overloads of
modular communications. Eliminating additional communications also reduces the hardware complexity.
In order to show the validity of the proposed design in real hardware resources, the proposed router has
been implemented onto a Field-Programmable Gate Array (FPGA). Since the implementation of a
Network-on-Chip (NoC) requires certain amount of area on the chip, the suggested approach is also able
to reduce the demand of hardware resources. In this method, the internal memory of the FPGA is used for
implementing control units. This memory is faster and can be used with specific patterns. The use of the
FPGA memory saves the hardware resources and allows the implementation of NoC based FPGA.

In deep sub-micrometer (DSM) regime the on-chip interconnect delay is significantly more dominating than the gate delay. Several approaches have been proposed to capture the interconnect delay accurately and efficiently. By interpreting the impulse response of a linear circuit as a Probability Distribution Function (PDF), Elmore first estimated the interconnect delay. Several other approaches like PRIMO, AWE, h-Gamma, WED, D2M etc. have been reported so far, which are shown to be more accurate delay estimation compared to Elmore delay metric. But they suffer from computational complexity when using in the total IC design processes. On the other hand slew rate determines the ability of a device to handle the varying signals. Determination of the slew rate to a good proximity is thus essential for efficient design of high speed CMOS integrated circuits. This in turn estimates the output switching surges in the device. Interconnect slew has become a crucial bottleneck for any high density and high speed VLSI circuits as increased slew results in the increase in delay. Our work presents a closed form formulae for interconnect delay and slew calculation. The proposed metrics are derived by matching circuit moments to the Weibull distribution. This avoids use of complex look-up tables. Experiments validate the effectiveness of our metrics for nets from a real industrial design. We have achieved an average relative error as low as 15% in the delay calculation (compared to the true delay) and 4% in the slew calculation (compared to the true slew value).