On-chip Interconnection Networks

A comprehensive investigation of the surfaces of copper through silicon vias (Cu-TSVs) and gold stud bumps is presented. These vias and stud bumps were bonded at room temperature using a nanobonding and interconnection equipment. The influence of heating on the bonded interface was also studied. In order to achieve an intimate contact between the Au-stud bumps and Cu-TSVs, the stud bumps were flattened under an external force of 20 N before bonding. The surface roughness of the flattened area was improved due to deformation of the bumps. Specimens with high deformation provided better alignment accuracy than those with low deformation. The Cu-TSV surface showed inhomogeneous behavior due to the influence of electroplating and chemical mechanical polishing. Tensile pulling test of the bonded interfaces showed three fractures modes in the bulk of the Au bump and the Au pad. The electrical resistance of the bonded interface was dependent on the surface morphology of the bumps and TSVs,...

In the late years many different interconnection networks have been used with two main tendencies. One is characterized by the use of high-degree routers with long wires while the other uses routers of much smaller degree. The latter rely on two-dimensional mesh and torus topologies with shorter local links. This paper focuses on doubling the degree of common 2D meshes and tori while still preserving an attractive layout for VLSI design. By adding a set of diagonal links in one direction, diagonal networks are obtained. By adding a second set of links, networks of degree eight are built, named king networks. This research presents a comprehensive study of these networks which includes a topological analysis, the proposal of appropriate routing procedures and an empirical evaluation. King networks exhibit a number of attractive characteristics which translate to reduced execution times of parallel applications. For example, the execution times NPB suite are reduced up to a 30%. In addition, this work reveals other properties of king networks such as perfect partitioning that deserves further attention for its convenient exploitation in forthcoming high-performance parallel systems.

The majority of the system on chip (SoC) uses the network on chip (NoC) as routing ports for data transfer from node-to-node with minimal power consumption and low latency and high throughput. This paper concentrates on the ability to model the asynchronous NoCs on the asynchronous circuits on field programmable gate arrays (FPGAs). A 3×3 NoC and its universal asynchronous receiver transmitter (UART) protocol is designed and its simulation of the Verilog hardware description language (VHDL) code is done and tested on the Artix-7 FPGA kit, the testing processes in done using the Chipscope tool. In order to meet target requirements in terms of power consumption and latency, the label switching (LS) technique is used as routing. The proposed LS-NoC with level-encoded dual-rail (LEDR) encoding technique provides throughput by registering the packet between the different routers and it helps to improve throughput and speed. The effectiveness of the data transfer is measured and analyzed through a synthesis summary in terms of lookup table's (LUT's), slice registers, flip flops's (FF's), latency, and packet delivery ratio (PDR) for the traffic pattern generator. The proposed NoC is designed for 8×8 and each port size is 21 bits including ID's of source and destination routers. The results can be justified by following results: improvement of LUTs is about 12%, flip-flops are 7%, improvement of throughput is 23% and delay is reduced by 26%.

Abstract—The thermal challenge of 3D Network-on-Chip (NoC) is severer than 2D NoC. To ensure thermal safety and avoid huge performance back-off from temperature constraint, Runtime Thermal Management (RTM) is required. However the regulation of temperature ...

Precise data & information is the lifeblood for the operation of Wireless Sensor Networks (WSNs). Incorrect (faulty data) information may lead to the wrong decision; it decreases the reliability in communication and overall operation of WSN. Fault tolerance is one of the issues in WSNs. Proposed fault-tolerant data aggregation scheme for identifying the faulty data sent by the sensors to the cluster head, where the aggregation is performed. Faulty information or data is discarded before aggregation. It would help to improve the accuracy of data aggregation. Consequently, the transmission overhead reduces, since erroneous data is eliminated. The proposed solution gives better performance by detecting and eliminating faulty data providing nodes

This paper presents the Hybrid Scalable-Minimized-Butterfly-Fat-Tree (H-SMBFT) topology for on-chip communication. Main aspects of this work are the description of the architectural design and the characteristics as well as a comparative analysis against two established indirect topologies namely Butterfly-Fat-Tree (BFT) and Scalable-Minimized-Butterfly-Fat-Tree (SMBFT). Simulation results demonstrate that the proposed topology outperforms its predecessors in terms of performance, area and power dissipation. Specifically, it improves the link interconnectivity between routing levels, such that the number of required links isreduced. This results into reduced router complexity and shortened routing paths between any pair of communicating nodes in the network. Moreover, simulation results under synthetic as well as real-world embedded applications workloads reveal that H-SMBFT can reduce the average latency by up-to35.63% and 17.36% compared to BFT and SMBFT, respectively. In addition, the power dissipation of the network can be reduced by up-to33.82% and 19.45%, while energy consumption can be improved byup-to32.91% and 16.83% compared to BFT and SMBFT, respectively.

We analyze the scalability of the Release Consistency (RC) and Sequential Consistency (SC) models which are realized in the Network-on-Chip (NoC) based distributed shared memory multicore systems. The analysis is performed on the basis of workloads mapped on the different sizes of networks with different data sets. The experiments use a configurable platform based on a 2D mesh NoC using deflection routing algorithm. The results show that under the synthetic workloads using different distributed locks, the performance of the RC model is increased by 17.6% to 54.6% over the SC model in the 64-cores system. For the application workloads, as the network size grows from 1 to 64 cores, the execution time under the RC model decreases relative to the SC model which depends on the application and its match to the architecture. The performance improvement of the RC model over the SC model tends to be higher than 50% observed in the experiments, when the system is further scaled up.

Continuous technology scaling in semiconductor industry makes the system reliability as a serious concern in the area of nanoscale computing. In this paper, a fully adaptive routing algorithm is proposed to overcome faults in NoCs (Network-on-Chip). This algorithm called DINRA-NoC (DIstiributed and New Routing Algorithm for NoC) is distributed, fault tolerant and congestion-aware. First, each node selects the appropriate output to route packets to neighbor routers according to the state of each link and router. Secondly, the proposed routing algorithm takes in account the status of adjacent routers traffic to update the congestion metric. DINRA-NoC does not use any VCs (Virtual Channels) and is deadlock-free. A simulation of the proposed routing algorithm has been carried out using Noxim simulator. The results show that DINRA ensures a good reliability rate despite of the presence of many faulty routers/links. In other hand, the simulation results indicate that the performance of the proposed routing algorithm surpasses the performance of existing algorithms in terms of lowering the congestion, improving average latency and increasing throughput.

appears that similar needs and constraints are emerging for the embedded HPC domain, in transport applications for instance with autonomous driving, avionics, etc. All these application domains require highly optimized and energy efficient functions: generic ones such as cores, GPUs, embedded FPGAs, dense and fast memories, and also more specialized ones, such as Machine Learning and Neuroaccelerators to efficiently implement the greedy computing demand of Big Data and AI applications. Circuit and system designers are in need of a more affordable, scalable and efficient way of integrating those heterogeneous functions, to allow more reuse, at circuit level, while focusing on the right innovations in a sustainable manner. Due to the slowdown of advanced CMOS technologies (7nm and below), with yield issues, design and mask costs, the innovation and differentiation through single die solution is not viable anymore. Mixing heterogeneous technologies using 3D is a clear alternative [2][3]. Partitioning the system into multiple chiplets 3D-stacked onto large-scale interposersorganic substrate [4], 2.5D passive interposer [5] or silicon bridge [6]leads to large modular architectures and cost reduction in advanced technologies using a Known Good Die (KGD) strategy and yield management. Nevertheless, the current passive interposer solutions still lack flexible and efficient long distance communication, smooth integration of chiplets with incompatible interfaces, and easy integration of less-scalable analog functions, such as power management and system IOs. We present the first CMOS Active Interposer, measured on silicon, integrating power management, distributed interconnects, enabling an innovative scalable cache coherent memory hierarchy. Six chiplets are 3Dstacked onto the active interposer, offering a total of 96 cores.

Table-based routing is a common approach for a fault-tolerant Network-on-Chip (NoC). This approach is hard to scale, since the table size tends to grow according to the NoC size. To surpass this problem, some works, such as the Region-Based Routing (RBR), have proposed techniques for saving routing tables area. This work proposes an alternative routing technique finding among communication pairs selected by the RBR technique, shrinking the amount of bits used for setting up regions. The experimental results have shown that the proposed technique reduces the maximum and mean number of regions, decreasing the space used by routing tables, providing more scalable and efficient routing NoC.

Silicon photonics have emerged as a promising solution to meet the growing demand for high-bandwidth, low-latency, and energy-efficient on-chip and off-chip communication in many-core processors. However, current silicon-photonic interconnect designs for many-core processors waste a significant amount of power because (a) lasers are always on, even during periods of interconnect inactivity, and (b) microring resonators employ heaters which consume a significant amount of power just to overcome thermal variations and maintain communication on the photonic links, especially in a 3D-stacked design. The problem of high laser power consumption is particularly important as lasers typically have very low energy efficiency, and photonic interconnects often remain underutilized both in scientific computing (compute-intensive execution phases underutilize the interconnect), and in server computing (servers in Google-scale datacenters have a typical utilization of less than 30%). We address the high laser power consumption by proposing EcoLaser+, which is a laser control scheme that saves energy by predicting the interconnect activity and opportunistically turning the on-chip laser off when possible, and also by scaling the width of the communication link based on a runtime prediction of the expected message length. Our laser control scheme can save up to 62-92% of the laser energy, and improve the energy efficiency of a manycore processor with negligible performance penalty. We address the high trimming (heating) power consumption of the microrings by proposing insulation methods that reduce the impact of localized heating induced by highly-active components on the 3D-stacked logic die.

This paper presents the Hybrid Scalable-Minimized-Butterfly-Fat-Tree (H-SMBFT) topology for on-chip communication. Main aspects of this work are the description of the architectural design and the characteristics as well as a comparative analysis against two established indirect topologies namely Butterfly-Fat-Tree (BFT) and Scalable-Minimized-Butterfly-Fat-Tree (SMBFT). Simulation results demonstrate that the proposed topology outperforms its predecessors in terms of performance, area and power dissipation. Specifically, it improves the link interconnectivity between routing levels, such that the number of required links isreduced. This results into reduced router complexity and shortened routing paths between any pair of communicating nodes in the network. Moreover, simulation results under synthetic as well as real-world embedded applications workloads reveal that H-SMBFT can reduce the average latency by up-to35.63% and 17.36% compared to BFT and SMBFT, respectively. In addition, the power dissipation of the network can be reduced by up-to33.82% and 19.45%, while energy consumption can be improved byup-to32.91% and 16.83% compared to BFT and SMBFT, respectively.

Network‐on‐Chip (NoC) is a key component in chip multiprocessors (CMPs) as it supports communication between many cores. NoC is a network‐based communication subsystem on an integrated circuit, most typically between modules in a system on a chip (SoC). Designing a reliable NoC against failures that can prevent failure using some measures or preventing error or system failure while failure happens and proper performance became a significant concern. For a reliable design against failures, first, the system should be analysed to discover the critical points. Hence, in this research, it is tried first to investigate the scale of fault tolerance effect on the mechanism in the router on the network by injecting simulated errors, and then these errors are prevented. As the major novelty, the authors implemented a router on a synchronised network and calculated the network buffering fault tolerance by injecting error in the buffer. Specifically, a new method for improving fault tolerance ...

In the future almost every consumer electronics device will be connected to an ecosystem of third-party partners providing services such as payment, streaming content, and so on. Present work aims to expose the foundations of a secure environment by ensuring security on the edge devices. MPSoCs are widely used in edge devices due to their capability to execute multiple applications in single-chips. To achieve the targeted security level against physical adversaries, all communications between the MPSoC and its environment must be protected. In an MPSoC multiple processing elements such as CPUs send requests to different on-chip memories. Network-on-chip has been proposed for MPSoC design, aiming at increasing performance and reducing power compared to on-chip buses. Tailoring the NoC to application(s) takes place usually at designtime. The selection of NoC parameter values affects both performance and power, while configuring them unwisely can result in unnecessary area overhead and chip cost. In the present work we concentrate on a commercial interconnect called STNoC from STMicroelectronics. We keep the NoC parameters fixed, and we explore the effects from the variation of other parameters, such as the injection rate of the packets transmitted by the CPUs, and the activation/deactivation of a security mechanism integrated in the network interface of the NoC, for multiple traffic scenarios with each one representing different amount of legal and malicious requests, for different mappings, and for different node setups. Experimental results, reveal the conditions under which the NoC starts experiencing saturation phenomena.

In the future almost every consumer electronics device will be connected to an ecosystem of third-party partners providing services such as payment, streaming content, and so on. Present work aims to expose the foundations of a secure environment by ensuring security on the edge devices. MPSoCs are widely used in edge devices due to their capability to execute multiple applications in single-chips. To achieve the targeted security level against physical adversaries, all communications between the MPSoC and its environment must be protected. In an MPSoC multiple processing elements such as CPUs send requests to different on-chip memories. Network-on-chip has been proposed for MPSoC design, aiming at increasing performance and reducing power compared to on-chip buses. Tailoring the NoC to application(s) takes place usually at designtime. The selection of NoC parameter values affects both performance and power, while configuring them unwisely can result in unnecessary area overhead and chip cost. In the present work we concentrate on a commercial interconnect called STNoC from STMicroelectronics. We keep the NoC parameters fixed, and we explore the effects from the variation of other parameters, such as the injection rate of the packets transmitted by the CPUs, and the activation/deactivation of a security mechanism integrated in the network interface of the NoC, for multiple traffic scenarios with each one representing different amount of legal and malicious requests, for different mappings, and for different node setups. Experimental results, reveal the conditions under which the NoC starts experiencing saturation phenomena.

In multiprocessor system-on-chip (MPSoC), a CPU can access physical resources, such as on-chip memory or I/O devices. Along with normal requests, malevolent ones, generated by malicious processes running in one or more CPUs, could occur. A protection mechanism is therefore required to prevent injection of malicious instructions or data across the system. We propose a self-contained Network-on-Chip (NoC) firewall at the network interface (NI) layer which, by checking the physical address against a set of rules, rejects untrusted CPU requests to the onchip memory, thus protecting all legitimate processes running in a multicore SoC. To sustain high performance, we implement the firewall in hardware, with rule-checking performed at segmentlevel based on deny rules. Furthermore, to evaluate its impact, we develop a novel framework on top of gem5 simulation environment, coupling ARM technology and an instance of a commercial point-to-point interconnect from STMicroelectronics (STNoC). Simulation tests include scenarios in which legitimate and malicious processes, running in different CPUs, request access to shared memory. Our results indicate that a firewall implementation at the NI can have a positive effect on network performance by reducing both end-to-end network delay and power consumption. We also show that our coarse-grain firewall can prevent saturation of the on-chip network and performs better than fine-grain alternatives that perform rule checking at page-level. Simulation results are accompanied with field measurements performed on a Zedboard platform running Linux, whereas the NoC Firewall is implemented as a reconfigurable, memory-mapped device on top of AMBA AXI4 interconnect fabric.

Network on Chip (NoC) is an up-coming worldview that adapts to the expanding many-sided quality and correspondence prerequisite of future System on Chip (SoC). Numerous topologies with various capacities have been proposed for NoCs, various topologies and parameters are chosen based on different NoC applications. In this paper, we have modeled the Mesh topology for 4X4 and 8X8 ,16x16,32x32,64x64 nodes for varying packets size (0.1 and 16000Kbytes), queue size(5-200), link bandwidth(10-200Mbps), link propagation delay(10-200ms), over CBR(5 and 10Mbps) and FTP applications. The performance of throughput and propagation delay of packets from given source node to destination node is studied for low(0.512Kbytes) and high load(64Kbytes) applications. Point by point similar investigation of the reproduction brings about terms of latency and throughput are displayed. The outcomes can be utilized as a rule for NoC architects to settle on fitting decisions keeping in mind the end goal to accomplish ideal execution for respective applications of future wireless communications systems is to provide sensor data transmission high-data-rate,quality of service (QoS),low cost,speed of wireless access .Multiple-input multipleoutput (MIMO) wireless technology meet these demands spectral efficiency, and improved link reliability.

Network on Chip (NoC) is an up-coming worldview that adapts to the expanding many-sided quality and correspondence prerequisite of future System on Chip (SoC). Numerous topologies with various capacities have been proposed for NoCs, various topologies and parameters are chosen based on different NoC applications. In this paper, we have modeled the Mesh topology for 4X4 and 8X8 ,16x16,32x32,64x64 nodes for varying packets size (0.1 and 16000Kbytes), queue size(5-200), link bandwidth(10-200Mbps), link propagation delay(10-200ms), over CBR(5 and 10Mbps) and FTP applications. The performance of throughput and propagation delay of packets from given source node to destination node is studied for low(0.512Kbytes) and high load(64Kbytes) applications. Point by point similar investigation of the reproduction brings about terms of latency and throughput are displayed. The outcomes can be utilized as a rule for NoC architects to settle on fitting decisions keeping in mind the end goal to acco...

Many intellectual property (IP) modules are present in contemporary system on chips (SoCs). This could provide an issue with interconnection among different IP modules, which would limit the system's ability to scale. Traditional bus-based SoC architectures have a connectivity bottleneck, and network on chip (NoC) has evolved as an embedded switching network to address this issue. The interconnections between various cores or IP modules on a chip have a significant impact on communication and chip performance in terms of power, area latency and throughput. Also, designing a reliable fault tolerant NoC became a significant concern. In fault tolerant NoC it becomes critical to identify faulty node and dynamically reroute the packets keeping minimum latency. This study provides an insight into a domain of NoC, with intention of understanding fault tolerant approach based on the XY routing algorithm for 4×4 mesh architecture. The fault tolerant NoC design is synthesized on field programmable gate array (FPGA).

Many intellectual property (IP) modules are present in contemporary system on chips (SoCs). This could provide an issue with interconnection among different IP modules, which would limit the system's ability to scale. Traditional bus-based SoC architectures have a connectivity bottleneck, and network on chip (NoC) has evolved as an embedded switching network to address this issue. The interconnections between various cores or IP modules on a chip have a significant impact on communication and chip performance in terms of power, area latency and throughput. Also, designing a reliable fault tolerant NoC became a significant concern. In fault tolerant NoC it becomes critical to identify faulty node and dynamically reroute the packets keeping minimum latency. This study provides an insight into a domain of NoC, with intention of understanding fault tolerant approach based on the XY routing algorithm for 4×4 mesh architecture. The fault tolerant NoC design is synthesized on field programmable gate array (FPGA).

Contemporary silicon technology enables integrating billions of transistors and allows the creation of complex systems-on-chip. At the same time, strict power dissipation budgets and growing interest in high performance battery-powered devices drive the need for energy-efficient high performance circuits. Bundled-data asynchronous circuits are good candidates for high performance low power systems, as they operate with average-case delays and present reduced switching activity when compared to other asynchronous templates. The correct operation of bundled-data circuits relies on constraints that describe the timing relationships between data and control signals. However, commercial EDA frameworks do not offer an encompassing support to ensure the closure of such constraints, making implementation challenging. This paper proposes a synthesis flow to enable the description and enforcement of relative timing constraints at both logic and physical synthesis levels, using the Synopsys framework and a set of in-house scripts. Two case studies illustrate the flow: a pipelined multiplier and a network on chip input buffer FIFO, the latter comprising a non-linear pipeline and complex control circuits. Both case studies target the STMicroelectronics 28nm FDSOI technology, and validation occurs with post-layout simulations. Overall, the flow provides an automatic approach to meet relative timing constraints in a template-agnostic manner for bundled-data circuits design.

Networks on chip (NoCs) are efficient infrastructures to enable communication among the large number of IPs that compose modern systems on chip (SoCs). However, even if recent technologies allow the construction of such complex systems, they increase the cost and effort of designing a correct and efficient chip-wide clock delivery network for a fully synchronous system. Asynchronous NoCs are an attractive alternative, as they allow each IP to operate on an independent clock domain, eliminating the need for a global clock network and producing globally asynchronous locally synchronous (GALS) systems. This paper details the design of a low power NoC router that is asynchronous and employs a transition-signaling bundleddata design style. Results show reductions of 27% in energy consumption when compared to a similar synchronous router.

This paper presents a new NoC architecture to improve flexibility and area consumption using a centralized controller. The idea behind this paper is improving SDN concept in NoC. The NoC routers are replaced with small switches and a centralized controller doing the routing algorithm and making control decisions. As one of the main desirable property of NoC is flexibility, in this work with the help of centralized controller, having different topologies and also having two separate networks in a single platform is possible. The other effects of this new scheme are power and area consumption which are investigated. Performance of the NoC is also studied with an analytical model and compared with the traditional NoC. The proposed NoC is implemented in VHDL, simulated and tested with ISE Xilinx.

Network-on-Chip (NoC) is an efficient on-chip communication architecture specifically for System-on-a-Chip (SoC) design. However, the input buffers of a NoC router often take a significant portion of the silicon area and power consumption. Besides, the performance of a NoC is also greatly affected by the buffer size. In this article, a static buffer merging and resource sharing method is proposed for the application-specific SoC minimizing the NoC buffer. When given an application-specific task graph and the dataflow distribution, the proposed method statically merges rarely used buffers and generates the suitable number of input buffers for each router at design timely. The merged buffer is shared by several input directions. The experimental result shows that the buffer can be utilized more effectively after the resource sharing. Based on the synthesized design with TSMC 90nm technology, the proposed method reduces an average of 42.23% area and 35.13% power while providing similar...

Network‐on‐Chip (NoC) is a key component in chip multiprocessors (CMPs) as it supports communication between many cores. NoC is a network‐based communication subsystem on an integrated circuit, most typically between modules in a system on a chip (SoC). Designing a reliable NoC against failures that can prevent failure using some measures or preventing error or system failure while failure happens and proper performance became a significant concern. For a reliable design against failures, first, the system should be analysed to discover the critical points. Hence, in this research, it is tried first to investigate the scale of fault tolerance effect on the mechanism in the router on the network by injecting simulated errors, and then these errors are prevented. As the major novelty, the authors implemented a router on a synchronised network and calculated the network buffering fault tolerance by injecting error in the buffer. Specifically, a new method for improving fault tolerance ...

In the late years many different interconnection networks have been used with two main tendencies. One is characterized by the use of high-degree routers with long wires while the other uses routers of much smaller degree. The latter rely on two-dimensional mesh and torus topologies with shorter local links. This paper focuses on doubling the degree of common 2D meshes and tori while still preserving an attractive layout for VLSI design. By adding a set of diagonal links in one direction, diagonal networks are obtained. By adding a second set of links, networks of degree eight are built, named king networks. This research presents a comprehensive study of these networks which includes a topological analysis, the proposal of appropriate routing procedures and an empirical evaluation. King networks exhibit a number of attractive characteristics which translate to reduced execution times of parallel applications. For example, the execution times NPB suite are reduced up to a 30%. In addition, this work reveals other properties of king networks such as perfect partitioning that deserves further attention for its convenient exploitation in forthcoming high-performance parallel systems.

In this paper we propose two new topologies for on-chip networks that we have denoted as king mesh and king torus. These are a higher degree evolution of the classical mesh and torus topologies. In a king network packets can traverse the networks using orthogonal and diagonal movements like the king on a chess board. First we present a topological study addressing distance properties, bisection bandwidth and path diversity as well as a folding scheme. Second we analyze different routing mechanisms. Ranging from minimal distance routings to missrouting techniques which exploit the topological richness of these networks. Finally we make an exhaustive performance evaluation comparing the new king topologies with their classical counterparts. The experimental results show a performance improvement, that allow us to present these new topologies as better alternative to classical topologies.

We demonstrate a low-cost colorless optical network unit (ONU) utilizing silicon photonic components for wavelength division multiplexed passive-optical-networks. At the ONU, a waveguide-coupled microring works as a demultiplexer for separating the downstream signal from the centrally distributed continuous-wave (CW) light. The 10-Gb/s downstream signal is received using a waveguide-integrated germanium photodetector while the CW light is further modulated at 5 Gb/s using a silicon microring modulator for upstream signal generation. Error-free transmission over 25-km single mode fiber is achieved with 0.2-and 0.4-dB power penalties for the downstream and upstream signals, respectively. Complementary metal-oxide semiconductor-compatible silicon photonic technology offers the potential for monolithic integration and mass production.

Integrated photonics offers the possibility of compact, low energy, bandwidth-dense interconnects for large port count spatial optical switches, facilitating flexible and energy efficient data movement in future data communications systems. To achieve widespread adoption, intimate integration with electronics has to be possible, requiring switch design using standard microelectronic foundry processes and available devices. We report on the feasibility of a switch fabric comprised of ubiquitous silicon photonic building blocks, opening the possibility to combine technologies, and materials towards a new path for switch fabric design. Rather than focus on integrating all devices on a single silicon chip die to achieve large port count optical switching, this work shifts the focus towards innovative packaging and integration schemes. In this work, we demonstrate 1 × 8 and 8 × 1 microring-based silicon photonic switch building blocks with software control, providing the feasibility of a full 8 × 8 architecture composed of silicon photonic building blocks. The proposed switch is fully non-blocking, has path-independent insertion loss, low crosstalk, and is straightforward to control. We further analyze this architecture and compare it with other common switching architectures for varying underlying technologies and radices, showing that the proposed architecture favorably scales to very large port counts when considering both crosstalk and architectural footprint. Separating a switch fabric into functional building blocks via multiple photonic integrated circuits offers the advantage of piece-wise manufacturing, packaging, and assembly, potentially reducing the number of optical I/O and electrical contacts on a single die.

We demonstrate a compact and low-power wavelength-division multiplexing transmitter near a 1550-nm wavelength using silicon microrings. The transmitter is implemented on a silicon-on-insulator photonics platform with a compact footprint of 0.5 mm 2. The transmitter incorporates 8 wavelength channels with 200-GHz spacing. Each channel achieved error-free operation at 40 Gb/s, resulting in an aggregated data transmission capability of 320 Gb/s. To our knowledge, this is the highest aggregated data rate demonstrated in silicon wavelength-division multiplexing transmitters. Owing to the small device capacitance and the efficient pn-junction modulator design, the transmitter achieves low energy-per-bit values of 36 fJ/bit under 2.4 V pp drive and 144 fJ/bit under 4.8 V pp drive. Comparisons are made to a commercial lithium niobate modulator in terms of bit-error-rate versus optical signal-to-noise ratio.

In this paper we report on experimental techniques for the thermal characterization of IGBT power modules. Three different systems have been used: the first one performs "in-time" characterization in order to control the most significant device parameters during normal operation or stress tests; the second one is for a complete and dynamic thermal characterization; finally, infrared optical analysis has been performed to validate the results.

The increasing complexity of integrated circuits drives the research of new intra-chip interconnection architectures. A network-on-chip adapts concepts originated in the distributed systems and computer networks subject areas to connect IP cores in a structured and scalable way, pursuing the goal of achieving superior bandwidth to conventional intra-chip bus architectures. This paper presents the design of a switch targeted to a mesh interconnection topology. Each switch has 5 bi-directional ports, connecting 4 neighbor switches and a local IP core. They employ a XY routing algorithm, with input queue buffers. The main objective is to develop a switch with a small area, enabling its immediate practical use. The switch and a 2x2 mesh network were validated through functional simulation. Also the network has been successfully prototyped in hardware, using a million-gate FPGA.

Networks-on-Chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a methodology to automatically synthesize an architecture where a few application-specific long-range links are inserted on top of a regular mesh network. This way, we can better exploit the benefits of both complete regularity and partial customization. Indeed, our experimental results show that inserting application-specific long-range links significantly increases the critical traffic workload at which the network state transits from a free to a congested regime. This, in turn, results in a significant reduction in the average packet latency and a major improvement in the achievable network throughput.

Received: 16 April, 2017 Accepted: 4 September, 2019 Abstract— The Micro Packet Switched based Network on Chip (NoC) is emerged to address traditional non-scalable buses-based Systems on Chip (SoC) challenges such as out of order transactions, flow control and higher latencies. The NoC is disposable to a different of defects in its life which cause of such drawbacks as data missing, efficiency reduction, and eventually, entire system overwhelm. This paper is amid to propose a new Offline-Structural Distributed Test Mechanism (OSDTM) to discovering and emplacing shorts on the data links in NoC. The projected test approach encompasses three main component namely Test Pattern Producer (TPP), Test Response Compiler (TRC) that are implanted in the Network Adapter (N) as well as a Flit Comparator Block (FCB) located in the Routers(R). The FCB concern is to detect dissimilar Flits through comparison the entrance Flits. The OSDTM leads to 100% Test Coverage (TC), 82.3% Discovering Capabilit...

Currently the industry moves to smaller process nodes even if the cost for yielding large dies continues to increase, moving to the 5nm and even 3nm nodes. Hence a chipletbased design has been initiated and quickly gain attention from industry, academia and government agencies. This cutting edge approach became advantageous to break down a large die into smaller chiplets in order to improve yield and binning. In order to exploit this new approach the interconnect fabric connecting the nodes of the entire system should be of high importance to enable the properly distribution of the data. Each individual chiplet may contain its own local Network on Chip (NoC), which operates for intra-chiplet traffic. However the communication over chipletbased systems is complicated enough, due to various routing algorithms and NoC topologies and an alternative solution is needed. In this paper we introduce an SDNoC(Software Define Network on Chip)-based communication protocol for chipletbased systems, called MicroLET, which consists of a flexible and modular SDNoC architecture and 3 main phases: Handshake, Network Monitoring, Routing. An implementation of the SDNoC architecture and an evaluation of the proposed routing algorithm compared to the XY and the Odd-Even algorithms within different traffic scenarios is presented. Through the evaluation of the MicroLET protocol, it is proven that it could be a good candidate for the future chiplet-based systems.

Network-on-Chip (NoC) is used as the communication network in many applications that use multiple cores or Processing Elements (PEs). Routers play a crucial role as connectors since a faulty router can degrade the NoC's performance and cause miscommunication between the network's components. Thus a faulty router may cause the system to fail. To avoid failure in routers in NoCs, a novel self-healing technique is proposed. Self-healing serves to recover hardware faults, and it is defined as the ability of a system to recover from its faults without any external intervention. The proposed self-healing method is to heal faulty routers and their port buffers of faults as they occur. The proposed method uses the neighboring routers of a faulty router for computation. The data packet includes three bits for routing. A neighbor's active router updates these bits according to the destination of the packet. A self-healing block is added inside each router. The proposed method also covers faulty buffers, and it uses active buffers to store the packet of a faulty one. It has been implemented and tested using VHDL and Altera Arria 10 GX FPGA. It has been found to attain improved reliability and Mean Time to Failure (MTTF) at an area overhead of 27%. It has been tested for complex NoC structure, and the results show it is practical, scalable, stable, and robust. INDEX TERMS NoC, self-healing, hardware faults, fault tolerance, neural network, FPGA architecture. KASEM KHALIL (Member, IEEE) received the B.Sc. and M.Sc. degrees in electrical engineering and electronics and communications engineering from Assiut University, Asyut, Egypt, in 2009 and 2014, respectively, and the second M.Sc. degree in computer engineering and the Ph.D. degree from the Center of Advanced Computer Studies, University of Louisiana at Lafayette, USA, in 2017 and 2021, respectively. His research interests include VLSI, microelectronics, reconfigurable hardware, self-healing hardware systems, machine learning, hardware accelerators, network-on-chip, intelligent hardware systems, and the Internet of Things.

Networks-on-Chip (NoCs) are now being used to provide inter-core communication for manycore Systems-on-Chip (SoCs). This is because traditional on-chip interconnects do not scale with increasing number of cores. Typical NoCs dedicate a set of buffers to their input and/or output ports. This can lead to buffer under-utilization for applications with non-uniform traffic characteristics. In order to provide improved buffer utilization for performance gains and energy efficiency, we have proposed the Roundabout-NoC (R-NoC) concept. R-NoC is inspired by real-life multi-lane traffic roundabouts. It consists of lanes shared by multiple input/output ports. This allows the buffers to be exploited for performance gains by data-flows from multiple input ports. This work extends the asynchronous evaluation of the R-NoC, named R-NoC-A. The router is evaluated using 45nm CMOS technology. The R-NoC-A router achieves a throughput of 465M f lit/sec and a network saturation throughput of 129Gbps on a 4x4 mesh network. R-NoC-A results, in terms of performance, area and power consumption, are highly competitive to existing solutions (synchronous and asynchronous). It provides good topological trade-offs for significantly improving network performance without corresponding area overhead.

Simultaneous all-optical switching of 20 continuouswave wavelength channels is achieved in a microring resonator-based silicon broadband 1 2 2 comb switch. Moreover, single-channel power penalty measurements are performed during active operation of the switch at both the through and the drop output ports. A statistical characterization of the drop-port insertion losses and extinction ratios of both ports shows broad spectral uniformity, and bit-error-rate measurements during passive operation indicate a negligible increase in signal degradation as the number of wavelength channels exiting the drop port are scaled from one to 16, with peak powers of 06 dBm per channel. A high-speed broadband switching device, such as the one described here, is a crucial element for the deployment of interconnection networks based on silicon photonic integrated circuits.

As size of chip is becoming smaller with growth in technology, and due to increase in number of cores, system-on-chip (SoC) becomes very complex. Networkon-chip (NoC) provides best solution to SoC by reducing communication overhead. The basic concern of NoC is the speed, performance and accuracy along with the small size of chip. The existing NoC topologies such as mesh topology, bus topology, torus topology, fat tree topology does not provide optimized performance. In this paper, we have proposed communication-based cluster topology (CBCT), which is based on 2H, i.e., heterogeneous and hybrid, proves to be more efficient topology by providing better performance due to reduction in latency, link utilization and energy consumption involved during communication. In experimental result, CBCT approach is compared with 2D mesh topology and CBCT proves to provide better results in terms of an end-to-end latency, network latency, packet latency, sink bandwidth, loss probability, link utilization and energy consumption of a topology.

Here, we address the orthogonalization of communication versus computation-in particular, separating the design of the block functionalities from communication architecture development. An essential element of communicationbased design is the encapsulation of predesigned functional modules within automatically generated interface structures. Such a strategy ensures a correct-by-construction composition of the system. Latency-insensitive design and the recycling paradigm are a step in this direction.

This work attempts to compare size and cost of two network topologies proposed for large-radix routers: concentrated torus and dragonflies. We study and compare the scalability, cost and fault tolerance of each network. On average, we found that a concentrated torus can be a cost-efficient option for middle-range networks.

In deep sub-micrometer (DSM) regime the on-chip interconnect delay is significantly more dominating than the gate delay. Several approaches have been proposed to capture the interconnect delay accurately and efficiently. By interpreting the impulse response of a linear circuit as a Probability Distribution Function (PDF), Elmore first estimated the interconnect delay. Several other approaches like PRIMO, AWE, h-Gamma, WED, D2M etc. have been reported so far, which are shown to be more accurate delay estimation compared to Elmore delay metric. But they suffer from computational complexity when using in the total IC design processes. On the other hand slew rate determines the ability of a device to handle the varying signals. Determination of the slew rate to a good proximity is thus essential for efficient design of high speed CMOS integrated circuits. This in turn estimates the output switching surges in the device. Interconnect slew has become a crucial bottleneck for any high density and high speed VLSI circuits as increased slew results in the increase in delay. Our work presents a closed form formulae for interconnect delay and slew calculation. The proposed metrics are derived by matching circuit moments to the Weibull distribution. This avoids use of complex look-up tables. Experiments validate the effectiveness of our metrics for nets from a real industrial design. We have achieved an average relative error as low as 15% in the delay calculation (compared to the true delay) and 4% in the slew calculation (compared to the true slew value).

Emerging data-driven applications such as graph processing applications are characterized by their excessive memory footprint and abundant parallelism, resulting in high memory bandwidth demand. As the scale of datasets for applications is reaching orders of TBs, performance limitation due to bandwidth demands is a major concern. Traditional on-chip electrical networks fail to meet such high bandwidth demands due to increased energy-per-bit or physical limitations with pin counts. Silicon photonic networks have emerged as a promising alternative to electrical interconnects, owing to their high bandwidth density and low energy-per-bit communication with negligible data-dependent power. Wide-scale adoption of silicon photonics at chip level, however, is hampered by their high sensitivity to process and thermal variations, high laser power due to losses along the network, and power consumption of the electrical-optical conversion. Device-level technological innovations to mitigate these issues are promising, yet they do not consider the system-level implications of the applications running on manycore systems with photonic networks. This work aims to bridge the gap between the system-level attributes of applications with the underlying architectural and device-level characteristics of silicon photonic networks to achieve energy-efficient computing. We particularly focus on graph applications, which involve unstructured yet abundant parallel memory accesses that stress the on-chip communication networks, and develop a crosslayer framework to evaluate 2.5D systems with silicon photonic networks. We demonstrate 38% power savings through systemlevel management using wavelength selection policies with only 1% loss in system performance and further evaluate architectural design choices on 2.5D systems with photonic networks.

Recent remarkable advances in nanoscale siliconphotonic integrated circuitry specifically compatible with CMOS fabrication have generated new opportunities for leveraging the unique capabilities of optical technologies in the on-chip communications infrastructure. Based on these nano-photonic building blocks, we consider a photonic network-on-chip architecture designed to exploit the enormous transmission bandwidths, low latencies, and low power dissipation enabled by data exchange in the optical domain. The novel architectural approach employs a broadband photonic circuit-switched network driven in a distributed fashion by an electronic overlay control network which is also used for independent exchange of short messages. We address the critical network design issues for insertion in chip multiprocessors (CMP) applications, including topology, routing algorithms, path-setup and teardown procedures, and deadlock avoidance. Simulations show that this class of photonic networks-on-chip offers a significant leap in the performance for CMP intrachip communication systems delivering low-latencies and ultra-high throughputs per core while consuming minimal power.

Recently, the demand for features such as shrinkable sizes, and the concurrent need to pack increasing numbers of transistors into a single chip, have led to the utilization of hundreds of CMPs as processer elements for significant data processing, such as cloud computing systems with high performance and minimum latency-power consumption. A 3D NoC is introduced as a promising solution for the next generations of CMPs. However, there are different design issues, as selecting an efficient routing algorithm is a process which still faces some challenges. In this paper, to handle the deficiencies of the selection of the optimal routing algorithms, artificial intelligence technology is used to predict the efficient routing algorithm with higher throughput and lower power consumption. Experimental results based on the 3D NOXIM simulator are presented, and illustrate that the performance of the proposed system can predict, with high accuracy, optimal routing algorithms by switching between existing 3D routing algorithms, depending on the traffic load rate for the NoC system. The NN-prediction approach is tested under PARSEC workloads to validate the effectiveness of 3D NoC throughput, energy consumption and hotspot distribution metrics.

This paper discusses the architecture and provides performance studies of a silicon photonic chip-scale optical switch for scalable interconnect network in high performance computing systems. The proposed switch exploits optical wavelength parallelism and wavelength routing characteristics of an Arrayed Waveguide Grating Router (AWGR) to allow contention resolution in the wavelength domain. Simulation results from a cycle-accurate network simulator indicate that, even with only two transmitter/receiver pairs per node, the switch exhibits lower end-to-end latency and higher throughput at high (>90%) input loads compared with electronic switches. On the device integration level, we propose to integrate all the components (ring modulators, photodetectors and AWGR) on a CMOS-compatible silicon photonic platform to ensure a compact, energy efficient and cost-effective device. We successfully demonstrate proof-ofconcept routing functions on an 8 × 8 prototype fabricated using foundry services provided by OpSIS-IME.

Network on Chip Architecture (NoC) is considered as the next generation interconnects systems for multiprocessor systems-on-chip. Selection of the network architecture and mapping of IP nodes onto the NoC topology are two important research topics. In this paper, we proposed an implementation of a Ring and Star NoC architecture using store and forward technique.

The network-on-chip (NoC) is an intra-communication on the chip extended from system-on-chip (SoC). The NoC design suffers from high failure rates due to the problem of routing in the traffic conditioning. In this paper, a realistic traffic pattern is used to verify the proposed routing scheme of the NoC with the novel design topology. Here a topology named mixed-torus topology is designed with the combination of processing block and the nonprocessing block that has the information about the processing block, which are associated with its torus block. The designed topology is presented with the encoder application model, and the set of tasks are mapped and scheduled to the processing block by the spider monkey optimization algorithm. Then the routing of data through the non-processing block is done by the pathfinder based traffic and thermal aware adaptive routing protocol (PFTTAR), which will perform the path diversity phase and the path selection phase for better routing. The designed NoC is then treated with the statistical traffic pattern generation for the analytical study of the proposed work and is implemented in Xilinx.