Networks on Chip (NoC)

In this paper, we present a generic router and a tool that allow the designer to easily and quickly customise a NoC in order to meet the requirements of a set of applications. Our router addresses what we consider as the main features of a realistic and useful NoC. Firstly, it supports the management of different levels quality of service (QoS) allowing guaranteed throughput service in addition to the classical best effort service. Secondly, it is associated to a CAD tool, which can fully configure and generate the NoC VHDL code at the RTL level. The paper presents the router architecture and its various custom characteristics as well as their impacts on the performance of the system.

Emerging non-volatile memory technologies open new perspectives for original computing architectures. In this paper, we propose a new type of flexible and energy-efficient architecture that relies on power-gated distributed Magnetoresistive Random-Access Memory (MRAM). The proposed architecture uses a Network-on-Chip (NoC) to interconnect MRAM-based clusters, processing elements, and managers. The NoC distributes application-specific commands to MRAM devices by means of packets. Configurable Network Interfaces (NI) allow to transform MRAM devices into smart units able to respond to incoming commands. In this context, three types of MRAM designs are proposed with different power-gating policies and granularities. A relevant database search engine case study is considered to illustrate the benefits of this proposed architecture. It is implemented with a Sparse-Neural-Network (SNN) approach and simulated in SystemC with different scenarios including hundreds of database queries. Hardware designs and accurate power estimations have been conducted. The obtained results demonstrate important power reduction with database hit rates of about 94%. Targeting 65nm technology, energy savings reach 87% when compared with an SRAM-based implementation. Moreover, a new asymmetric read/write MRAM type provides from 39% to 50% energy reduction with respect to the other fixed-granularity models. This results in a low-power, highly scalable and configurable implementation of memory-based computing.

In recent years distributed storage systems have been the object of increasing interest by the research community. They promise improvements on information availability, security and integrity. Nevertheless, at this point in time, there is no a predominant approach, but a wide spectrum of proposals in the literature. In this paper we report our findings with a combination of redundancy techniques intended to simultaneously provide fault tolerance and load balance in a small-scale distributed storage system. Based on our analysis, we provide general guidelines for system designers and developers under similar conditions.

The alignment of millions of short DNA fragments to a large genome is a very important aspect of the modern computational biology. However, software-based DNA sequence alignment takes many hours to complete. This paper proposes an FPGA-based hardware accelerator to reduce the alignment time. We apply a data encoding scheme that reduces the data size by 96 percent, and propose a pipelined hardware decoder to decode the data. We also design customized data paths to efficiently use the limited bandwidth of the DDR3 memories. The proposed accelerator can align a few hundred million short DNA fragments in an hour by using 80 processing elements in parallel. The proposed accelerator has the same mapping quality compared to the software-based methods.

This paper develops path concepts for the execution of different algorithms on a reconfigurable architecture. New architecture concepts demand for permanent evaluation of such extensions, also including validating case studies. The recently patented synchronous bit-serial pipelined architecture, which we investigate in this paper, comprises synchronous and systematic bit-serial processing without a central controlling instance. It targets future high speed applications due to the abdication of long wires. The application specificity of the basic version of the architecture can be overcome by so called routers, achieving a reconfigurable system. This paper focuses on the difficulty to conceptualize these routers and proposes several variations for implementation. The case study, which comprises a combined version of the FDCT/IDCT algorithm, serves as an application example for the reconfigurability of the architecture. The example-implementing both algorithms in one operator network-broadens the application area of the architecture significantly.

Multiple Voltage Supply (MSV) chip fabrication is considered a viable technique for addressing the power and thermal challenges of modern many-core systems. Efficiency of this technique has been demonstrated in application specific Network-on-Chips (NoCs) which have lots of cores and various operating voltages/frequencies. In this paper, a four-phase synthesis toolchain is proposed and evaluated for the design of multi-voltage application specific NoCs. The proposed synthesis toolchain performs (i) core to router allocation, (ii) voltage islanding to match voltages of cores connected to the same router, (iii) hierarchical floorplanning to reduce the complexity of power delivery network, and (iv) path allocation to connect routers based on the application requirements. The distinguishing feature of the proposed toolchain is that, for the first time, the router allocation phase is performed prior to voltage islanding. This approach offers more flexibility and more efficiency in the multi-voltage NoC synthesis process. Experimental results on real benchmarks show that the toolchain (a) provides 63% less energy consumption and (b) produces twice as much alternative designs satisfying the benchmarks requirements when compared to existing approaches. Index Terms-application-specific chip, custom NoC synthesis, partitioning, islanding, floorplanning.

In recent years, Multi-Processor System-on-Chips (MPSoCs) are widely deployed in safety-critical embedded systems. The Cloud-of-Chips (CoC) is a scalable MPSoC architecture comprised of a large number of interconnected Integrated Circuits (IC) and Processing Clusters (PC) destined for critical systems. While many researches have focused on addressing the hardware issues of MPSoCs, the communication over them has not been very well explored. Following the SDN concept, we propose a new protocol in order to secure the communication and efficiently manage the routing within the CoC. The SSPSoC includes a private key derivation phase, a group key agreement (GKA) phase, and a data exchange phase in order to ensure that basic security primitives are preserved and provide secure communication. Furthermore, a network of 1-30 nodes is set in order to validate the proposed protocol and measure the network performance and memory consumption of the proposed protocol.

Precise data & information is the lifeblood for the operation of Wireless Sensor Networks (WSNs). Incorrect (faulty data) information may lead to the wrong decision; it decreases the reliability in communication and overall operation of WSN. Fault tolerance is one of the issues in WSNs. Proposed fault-tolerant data aggregation scheme for identifying the faulty data sent by the sensors to the cluster head, where the aggregation is performed. Faulty information or data is discarded before aggregation. It would help to improve the accuracy of data aggregation. Consequently, the transmission overhead reduces, since erroneous data is eliminated. The proposed solution gives better performance by detecting and eliminating faulty data providing nodes

Genome Informatics (GI) involves accurate computational investigations of strongly correlated subsystems that demands inter-disciplinary approaches for problem solving. With the growing volume of genomic sequencing data at an alarming rate, High Performance Computing (HPC) solutions offer the right platform to address the computational needs. GI requires algorithm-architecture co-design of parallel and accelerated biocomputing involving reconfigurable hardware like FPGAs and graphics accelerators or GPUs, to bridge the gap between growing data volumes and compute capabilities. Such platforms offer high degrees of parallelism and scalability, while accelerating the multi-stage GI computational pipeline. Amidst such high computing power, it is the choice of algorithms and implementations in the entirety of the GI pipeline that decides the precision of bio-computing in revealing biologically relevant information. Through this paper, we present ReneGENE-GI, an innovatively engineered GI pipeline. This paper details the performance analysis of ReneGENE-GI's Comparative Genomics Module (CGM), the compute intensive stage of the pipeline. This module comes in two flavours, designed to run on GPUs and FPGAs respectively, hosted on HPC platforms. The pipeline uses a very efficient reference indexing algorithm based on the dynamic Monotonic Minimal Perfect Hashing Function (MMPH), allowing an absolute indexing for the reference genome, thus avoiding heuristics. Alignment time for our FPGA version is about one-tenth the time taken by our single GPU implementation, which itself is 2.62x faster than CUSHAW2-GPU (the GPU CUDA implementation of CUSHAW). With the single-GPU implementation demonstrating a speed up of 150+ x over standard heuristic aligners in the market like BFAST, the FPGA version of our CGM is several orders faster than the competitors, offering precision over heuristics.

With the advent of ultra high-throughput DNA sequencing technologies used in Next-Generation Sequencing (NGS) machines, we are facing a daunting new era in petabyte scale bioinformatics data. The enormous amounts of data produced by NGS machines lead to storage, scalability, and performance challenges. At the same time, cloud computing architectures are rapidly emerging as robust and economical solutions to high performance computing of all kinds. To date, these architectures have had limited impact on the sequence alignment problem, whereby sequence reads must be compared to a reference genome.

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We analyze the scalability of the Release Consistency (RC) and Sequential Consistency (SC) models which are realized in the Network-on-Chip (NoC) based distributed shared memory multicore systems. The analysis is performed on the basis of workloads mapped on the different sizes of networks with different data sets. The experiments use a configurable platform based on a 2D mesh NoC using deflection routing algorithm. The results show that under the synthetic workloads using different distributed locks, the performance of the RC model is increased by 17.6% to 54.6% over the SC model in the 64-cores system. For the application workloads, as the network size grows from 1 to 64 cores, the execution time under the RC model decreases relative to the SC model which depends on the application and its match to the architecture. The performance improvement of the RC model over the SC model tends to be higher than 50% observed in the experiments, when the system is further scaled up.

Highly parallel systems are receiving significant attention to solve the large and complex problems. This has resulted in the emergence of many attractive interconnection network topologies. This paper introduces a new processor interconnection topology called STH (Scalable Twisted Hypercube) to counter the poor scalability of twisted hypercube. Its suitability for use as multiprocessor interconnection networks has also been explored. The various properties of the proposed topology have been analyzed and it has been compared with some other highly scalable topologies of interest on a number of interconnection networks evaluation parameters. With reduced diameter, better average distance, low traffic density, low cost, maximum number of links, high bisection width and tremendous scalability, STH is more suitable for Massively Parallel Systems. Procedures for routing and broadcasting on the proposed topology have also been discussed and a simple routing algorithm has been presented. The proposed interconnection network provides a great architectural support for parallel computing due to the concurrent existence of multiple LST(m) and TQn.

In this paper, a novel voter design is presented which allows the voting of asynchronous network streams in flow-controlled networks. The voter synchronises incoming data streams automatically and is able to handle failure modes that typically occur in streaming applications. The voter degrades to a comparator if one of the redundant channels has failed and reintegrates the channels once they are functional again. While the voter is mainly intended to be connected to a routing switch of the network, it also comprises a broadcast mechanism that enables a stand-alone operation. The design has been successfully implemented in hardware and evaluated by means of fault injection experiments.

Continuous technology scaling in semiconductor industry makes the system reliability as a serious concern in the area of nanoscale computing. In this paper, a fully adaptive routing algorithm is proposed to overcome faults in NoCs (Network-on-Chip). This algorithm called DINRA-NoC (DIstiributed and New Routing Algorithm for NoC) is distributed, fault tolerant and congestion-aware. First, each node selects the appropriate output to route packets to neighbor routers according to the state of each link and router. Secondly, the proposed routing algorithm takes in account the status of adjacent routers traffic to update the congestion metric. DINRA-NoC does not use any VCs (Virtual Channels) and is deadlock-free. A simulation of the proposed routing algorithm has been carried out using Noxim simulator. The results show that DINRA ensures a good reliability rate despite of the presence of many faulty routers/links. In other hand, the simulation results indicate that the performance of the proposed routing algorithm surpasses the performance of existing algorithms in terms of lowering the congestion, improving average latency and increasing throughput.

Network-on-Chip (NoC) has been proposed as an attractive alternative to traditional dedicated wires to achieve high performance and modularity. Power efficiency is one of the most important concerns in NoC architecture design. The choice of network topology is important in designing a low-power and high-performance NoC. In this paper, we propose the use of the WK-recursive networks to be used as the underlying topology in NoC. We have implemented VHDL hardware model of mesh and WK-recursive topologies and measured the latency results using simulation with these implementation. We also propose a novel approach in high level power modeling based on latency for these topologies and show that the power consumption of WK-recursive topology is less than that of the equivalent mesh on a chip.

Este artigo análisa o desempenho dos algoritmos de roteamento determinístico e adaptativo em sistemas multicomputadores baseados em malhas tridimensionais, sob vários padrões de tráfego. Para realizar este estudo foi desenvolvido um simulador denominado SIM3D. Os resultados obtidos nas simulações são comparados considerando-se a latência e o throughput. Entre os fatores utilizados na avaliação do desempenho temos: o tipo de algoritmo de roteamento, o padrão de tráfego e o tamanho das mensagens.

Network on Chip (NoC) is an approach to designing communication subsystem between intelligent property (IP) cores in a system on chip (SoC). Packet switch ed networks are being proposed as a global communication architecture for future system-on-chip (SoC) design s. In this project, we propose a design and impleme nt a wormhole router supporting multicast for Network-on-chip. Wormhole routing is a network flow control mechanism which decomposes a packet into smaller flits and delivers the flits in a pipelined fashion. It has good performance and small buffering requirements. The i mplementations are at the RT level using VHDL and they are synthesizable. First, based on virtual cut thro ugh router model, a unicast router is implemented a nd validated and based on the wormhole switching mode the multicast router architecture is designed and implemented . A Wormhole input queued 2-D mesh router is created to verify the capability of our router.

Network‐on‐Chip (NoC) is a key component in chip multiprocessors (CMPs) as it supports communication between many cores. NoC is a network‐based communication subsystem on an integrated circuit, most typically between modules in a system on a chip (SoC). Designing a reliable NoC against failures that can prevent failure using some measures or preventing error or system failure while failure happens and proper performance became a significant concern. For a reliable design against failures, first, the system should be analysed to discover the critical points. Hence, in this research, it is tried first to investigate the scale of fault tolerance effect on the mechanism in the router on the network by injecting simulated errors, and then these errors are prevented. As the major novelty, the authors implemented a router on a synchronised network and calculated the network buffering fault tolerance by injecting error in the buffer. Specifically, a new method for improving fault tolerance ...

In the future almost every consumer electronics device will be connected to an ecosystem of third-party partners providing services such as payment, streaming content, and so on. Present work aims to expose the foundations of a secure environment by ensuring security on the edge devices. MPSoCs are widely used in edge devices due to their capability to execute multiple applications in single-chips. To achieve the targeted security level against physical adversaries, all communications between the MPSoC and its environment must be protected. In an MPSoC multiple processing elements such as CPUs send requests to different on-chip memories. Network-on-chip has been proposed for MPSoC design, aiming at increasing performance and reducing power compared to on-chip buses. Tailoring the NoC to application(s) takes place usually at designtime. The selection of NoC parameter values affects both performance and power, while configuring them unwisely can result in unnecessary area overhead and chip cost. In the present work we concentrate on a commercial interconnect called STNoC from STMicroelectronics. We keep the NoC parameters fixed, and we explore the effects from the variation of other parameters, such as the injection rate of the packets transmitted by the CPUs, and the activation/deactivation of a security mechanism integrated in the network interface of the NoC, for multiple traffic scenarios with each one representing different amount of legal and malicious requests, for different mappings, and for different node setups. Experimental results, reveal the conditions under which the NoC starts experiencing saturation phenomena.

In the future almost every consumer electronics device will be connected to an ecosystem of third-party partners providing services such as payment, streaming content, and so on. Present work aims to expose the foundations of a secure environment by ensuring security on the edge devices. MPSoCs are widely used in edge devices due to their capability to execute multiple applications in single-chips. To achieve the targeted security level against physical adversaries, all communications between the MPSoC and its environment must be protected. In an MPSoC multiple processing elements such as CPUs send requests to different on-chip memories. Network-on-chip has been proposed for MPSoC design, aiming at increasing performance and reducing power compared to on-chip buses. Tailoring the NoC to application(s) takes place usually at designtime. The selection of NoC parameter values affects both performance and power, while configuring them unwisely can result in unnecessary area overhead and chip cost. In the present work we concentrate on a commercial interconnect called STNoC from STMicroelectronics. We keep the NoC parameters fixed, and we explore the effects from the variation of other parameters, such as the injection rate of the packets transmitted by the CPUs, and the activation/deactivation of a security mechanism integrated in the network interface of the NoC, for multiple traffic scenarios with each one representing different amount of legal and malicious requests, for different mappings, and for different node setups. Experimental results, reveal the conditions under which the NoC starts experiencing saturation phenomena.

In multiprocessor system-on-chip (MPSoC), a CPU can access physical resources, such as on-chip memory or I/O devices. Along with normal requests, malevolent ones, generated by malicious processes running in one or more CPUs, could occur. A protection mechanism is therefore required to prevent injection of malicious instructions or data across the system. We propose a self-contained Network-on-Chip (NoC) firewall at the network interface (NI) layer which, by checking the physical address against a set of rules, rejects untrusted CPU requests to the onchip memory, thus protecting all legitimate processes running in a multicore SoC. To sustain high performance, we implement the firewall in hardware, with rule-checking performed at segmentlevel based on deny rules. Furthermore, to evaluate its impact, we develop a novel framework on top of gem5 simulation environment, coupling ARM technology and an instance of a commercial point-to-point interconnect from STMicroelectronics (STNoC). Simulation tests include scenarios in which legitimate and malicious processes, running in different CPUs, request access to shared memory. Our results indicate that a firewall implementation at the NI can have a positive effect on network performance by reducing both end-to-end network delay and power consumption. We also show that our coarse-grain firewall can prevent saturation of the on-chip network and performs better than fine-grain alternatives that perform rule checking at page-level. Simulation results are accompanied with field measurements performed on a Zedboard platform running Linux, whereas the NoC Firewall is implemented as a reconfigurable, memory-mapped device on top of AMBA AXI4 interconnect fabric.

This work presents the design of high-gain directional microstrip patch antenna for operation at 2.45 GHz. Low cost of fabrication and low profile features of microstrip antennas, attract many researchers to investigate the performance of this antenna in various ways. The study includes of the development of a three-dimensional antenna model, antenna simulation, fabrication and analysis of results based on various outputs of the Ansoft–HFSS (High Frequency Structure Simulator) software package. Wideband operation and high gain was observed in designed microstrip patch antenna.

The design of integrated circuits will change a lot because of shorter time-to-market it is impossible to design all functional blocks from scratch. One proposed solution to this problem is to use Network-On-Chip (NOC) architectures,[18] which are built up from reusable interconnect IP blocks. In NOC 2D mesh is popular due to its simple implementation and scalability of simple XY routing, but due to long network diameter and extra hops makes it energy inefficient as the network grows on the other part Extended diametrical 2D mesh architecture reduces the network diameter up to 50 percent compared to 2D mesh at the cost of few extra links added to the architecture. Router is the main building block in NOC architecture and Router with XY algorithm is well known for its simplicity. In this project XY algorithm is changed to Extended XY algorithm where an extra diametrical link will be used which will reduce the number of hops considerably and helps in performance enhancement.

Emerging memory technologies, such as Gain Cell-embedded Dynamic Random Access Memory (GC-eDRAM), play an essential part in the process of improving the overall performance of current multi-processor systems. GC-eDRAM, on the other hand, has its own set of distinct issues, particularly with regard to refresh operations. The number of cores and threads in contemporary processors continues to expand, which in turn leads to an increase in the number of concurrent refresh requests. This might cause contention, which in turn can lead to a possible performance decrease. In this article, we present an efficient arbitration method that was developed in order to precisely address the issues that are associated with numerous requests for a refresh in GC-eDRAM. This method takes use of the inherent parallelism of GC-eDRAM modules to make it possible to execute simultaneous refresh operations. As a result, contention is effectively reduced, and the overall performance of the system is improved....

Network on Chip (NoC) is an up-coming worldview that adapts to the expanding many-sided quality and correspondence prerequisite of future System on Chip (SoC). Numerous topologies with various capacities have been proposed for NoCs, various topologies and parameters are chosen based on different NoC applications. In this paper, we have modeled the Mesh topology for 4X4 and 8X8 ,16x16,32x32,64x64 nodes for varying packets size (0.1 and 16000Kbytes), queue size(5-200), link bandwidth(10-200Mbps), link propagation delay(10-200ms), over CBR(5 and 10Mbps) and FTP applications. The performance of throughput and propagation delay of packets from given source node to destination node is studied for low(0.512Kbytes) and high load(64Kbytes) applications. Point by point similar investigation of the reproduction brings about terms of latency and throughput are displayed. The outcomes can be utilized as a rule for NoC architects to settle on fitting decisions keeping in mind the end goal to accomplish ideal execution for respective applications of future wireless communications systems is to provide sensor data transmission high-data-rate,quality of service (QoS),low cost,speed of wireless access .Multiple-input multipleoutput (MIMO) wireless technology meet these demands spectral efficiency, and improved link reliability.

Network on Chip (NoC) is an up-coming worldview that adapts to the expanding many-sided quality and correspondence prerequisite of future System on Chip (SoC). Numerous topologies with various capacities have been proposed for NoCs, various topologies and parameters are chosen based on different NoC applications. In this paper, we have modeled the Mesh topology for 4X4 and 8X8 ,16x16,32x32,64x64 nodes for varying packets size (0.1 and 16000Kbytes), queue size(5-200), link bandwidth(10-200Mbps), link propagation delay(10-200ms), over CBR(5 and 10Mbps) and FTP applications. The performance of throughput and propagation delay of packets from given source node to destination node is studied for low(0.512Kbytes) and high load(64Kbytes) applications. Point by point similar investigation of the reproduction brings about terms of latency and throughput are displayed. The outcomes can be utilized as a rule for NoC architects to settle on fitting decisions keeping in mind the end goal to acco...

A parallel processing system's most crucial part is a network interconnection that links its processors. The hypercube topology has interesting features that make it a great option for parallel processing applications. This paper presents two innovative configurations of interconnection networks based on fractal Sierpinski and a hypercube. These are called the Sierpinski Triangle Topology (STT) and Sierpinski Carpet Topology (SCT). Compared to a hypercube, the Sierpinski Triangle topology (STT) noticed a significant decrease in the number of nodes and links as large networks grew. Hence, it is considered a great way to reduce costs because it uses fewer nodes and links. The average distance is also shorter, which is better. Despite it having a smaller bisection width and a higher degree than a hypercube by one. The Sierpinski Carpet Topology (SCT) has the advantage of having a high bisection width compared to a hypercube. That is preferable because it places a lower restriction ...

Systems with multiple heterogeneous processing units, also known as Systems-on-Chip (SoC), have been used by the silicon industry as a solution to deliver the high performance demanded by modern applications. However, the integration of a large number of such processing units poses a challenge to the interconnection mechanisms. The industry has been using Networks-on-Chip (NoC) to solve this problem, an approach that uses routers and concepts from conventional computational networks to interconnect the processing units of a SoC. In general, a flow of these networks can be divided into two types: those of real-time coming from tasks that demand assurance of package delivery, quality of service, and hard execution time; best-effort flows that come from soft tasks, which does not demand such requirements. So far, many of the published NoCs aim to provide a minimum and predictable latency for real-time flows, such as the RTSNoC, a networkon-chip that gives throughput guarantee to real-time systems by using the technique of worst-case latency predictability. The RTSNoC does not offer a quality of service when used in applications with a higher amount of best-effort flows and only improves the average latency of those flows. To achieve a level of performance improvement on applications that have a best-effort flows dominance that NoC could use optimization methods, adaptive routing algorithms or reconfigurable computing by redistributing the interconnected processing units at runtime. Such methods need to be continuously fed with information about the network traffic obtained by a system able to monitor the packet delivery. Within that said, the present work aims to introduce to the RTSNoC project the concept of computational observability by developing a system who would be able to monitor and get information about the delivery of packages on that network.

Many intellectual property (IP) modules are present in contemporary system on chips (SoCs). This could provide an issue with interconnection among different IP modules, which would limit the system's ability to scale. Traditional bus-based SoC architectures have a connectivity bottleneck, and network on chip (NoC) has evolved as an embedded switching network to address this issue. The interconnections between various cores or IP modules on a chip have a significant impact on communication and chip performance in terms of power, area latency and throughput. Also, designing a reliable fault tolerant NoC became a significant concern. In fault tolerant NoC it becomes critical to identify faulty node and dynamically reroute the packets keeping minimum latency. This study provides an insight into a domain of NoC, with intention of understanding fault tolerant approach based on the XY routing algorithm for 4×4 mesh architecture. The fault tolerant NoC design is synthesized on field programmable gate array (FPGA).

Many intellectual property (IP) modules are present in contemporary system on chips (SoCs). This could provide an issue with interconnection among different IP modules, which would limit the system's ability to scale. Traditional bus-based SoC architectures have a connectivity bottleneck, and network on chip (NoC) has evolved as an embedded switching network to address this issue. The interconnections between various cores or IP modules on a chip have a significant impact on communication and chip performance in terms of power, area latency and throughput. Also, designing a reliable fault tolerant NoC became a significant concern. In fault tolerant NoC it becomes critical to identify faulty node and dynamically reroute the packets keeping minimum latency. This study provides an insight into a domain of NoC, with intention of understanding fault tolerant approach based on the XY routing algorithm for 4×4 mesh architecture. The fault tolerant NoC design is synthesized on field programmable gate array (FPGA).

Network-on-Chip (NoC) has been proposed as a solution for addressing the design challenges of future nanoscale architecture. This paper contribute in the enhancement of NOC architecture, a switch/router size 4x4 of 2-D mesh topology is targeted, the scheduler under consideration and Input module with efficient buffer to store the data packet while waiting for the scheduling are optimized at architecture level. The physical implementation of scheduler and the input module replacing D-Flip Flop based array by SRAM is carried out for area and power optimization. For further optimization of area and power, this paper also presents a low power design methodology-Gate Level Power Optimization to optimize dynamics & leakage power of the design and It has been observed that approximately 28% of Area and 68% of Power are optimized when compared with generic architecture of 2-D Mesh NoC D-Flip Flop based router.

The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed interconnection structure is a Network on Chip, or NoC. NoCs are emerging as a viable alternative to increasing demands on interconnection architectures, due to the following characteristics: (i) energy efficiency and reliability; (ii) scalability of bandwidth, when compared to traditional bus architectures; (iii) reusability; (iv) distributed routing decisions. An external host computer feeds MultiNoC with application instructions and data. After this initialization procedure, MultiNoC executes some algorithm. After finishing execution of the algorithm, output data can be read back by the host. Sequential or parallel algorithms conveniently adapted to the MultiNoC structure can be executed. The main motivation to propose this design is to enable the investigation of current trends to increase the number of embedded processors in SoCs, leading to the concept of "sea of processors" systems.

Many-core systems are envisioned to leverage the ever-increasing demand for more powerful computing systems. To provide the necessary computing power, the number of Processing Elements integrated onchip increases and NoC based infrastructures are adopted to address the interconnection scalability. The advent of these new architectures surfaces the need for more sophisticated, distributed resource management paradigms, which in addition to the extreme integration scaling, make the new systems more prone to errors manifested both at hardware and software. In this work, we highlight the need for Run-Time Resource management to be enhanced with fault tolerance features and propose SoftRM, a resource management framework which can dynamically adapt to permanent failures in a self-organized, workload-aware manner. Self-organization allows the resource management agents to recover from a failure in a coordinated way by electing a new agent to replace the failed one, while workload awareness optimizes this choice according to the status of each core. We evaluate the proposed framework on Intel Single-chip Cloud Computer (SCC), a NoC based many-core system and customize it to achieve minimum interference on the resource allocation process. We showcase that its workload-aware features manage to utilize free resources in more that 90% of the conducted experiments. Comparison with relevant state-of-the-art fault tolerant frameworks shows decrease of up to 67% in the imposed overhead on application execution. CCS Concepts: • General and reference → Cross-computing tools and techniques; • Computer systems organization → Multicore architectures; • Networks → Network on chip; • Computing methodologies → Self-organization;

Optical networks-on-chip (ONoCs) are gaining momentum as a way to improve energy consumption and bandwidth scalability in the next generation multicore and many-core systems. Although many valuable research works have investigated their properties, the vast majority of them lack an accurate exploration of the network interface architecture required to support optical communications on the silicon chip. The complexity of this architecture is especially critical for a specific kind of ONoCs: the wavelength-routed ones. These are capable of delivering contention-free all-to-all connectivity without the need for path reservation, unlike space-routed ONoCs. From a logical viewpoint, they can be considered as full nonblocking crossbars; thus, the control complexity is implemented at the network interfaces. To our knowledge, this paper proposes the first complete network interface architecture for wavelength-routed optical NoCs, by coping with the intricacy of networking issues such as flow control, buffering strategy, deadlock avoidance, serialization, and above all, their codesign in a complete architecture. The evaluation methodology spans from area and energy analysis via actual synthesis runs in 40-nm technology to RTL-equivalent (register-transfer level) SystemC modelling of the network architecture and aims at verifying whether the projected benefits of ONoCs versus their electrical counterparts are still preserved when the complexity of their network interface is considered in the analysis.

We explore on-chip network topologies for the Q100, an analytic query accelerator for relational databases. In such data-centric accelerators, interconnects play a critical role by moving large volumes of data. In this paper we show that various interconnect topologies can trade a factor of 2.5× in performance for 3.3× area. Moreover, standard topologies (e.g., ring or mesh) are not optimal. Significant prior work on network topology specialization augments generic topologies with additional dedicated links. In this paper, we present a network specialization algorithm that builds a specialized network first then introduces a generic network as a fallback. We find our algorithm produces networks that are 1.24× slower than the highest-performance generic topology considered (a fat tree), and 18% smaller than the least expensive (a double ring). Moreover, our method produces topologies that outperform those produced by others by 1.21× while being 25% smaller.

Effective and efficient routing is one of the most important parts of routing in NoC-based neuromorphic systems. In fact, this communication structure connects different units through the packets routed by routers and switches embedded in the network on a chip. With the help of this capability, not only high scalability and high development can be created, but by decreasing the global wiring to the chip level, power consumption can be reduced. In this paper, an adaptive routing algorithm for NoC-based neuromorphic systems is proposed along with a hybrid selection strategy. Accordingly, a traffic analyzer is first used to determine the type of local or nonlocal traffic depending on the number of hops. en, considering the type of traffic, the RCA and NoP selection strategies are used for the nonlocal and local strategies, respectively. Finally, using the experiments that performed in the simulator environment, it has been shown that this solution can well reduce the average delay time and power consumption.

This paper addresses elevator assignment in vertically-partially-connected 3-D-networks-on-chip (NoCs). Elevators are vertical links between dies. Because of yield issues, Through-Silicon-Via (TSV) cost, and heterogeneity in dimension, topology, and technology of different dies, verticallypartially-connected topologies seem unavoidable in the emerging 3-D-NoCs as opposed to fully-connected topologies. In such partially-connected topologies, as there are fewer elevators than routers, the assignment of elevators to routers becomes a new 3-D-specific optimization problem. An improper assignment can lead to dramatic network performance degradation. This paper proposes an elevator assignment method for best-effort wormhole 3-D-NoCs to improve the average network performance. Experimental results show an improvement of about 90% even compared to a greedy (intrinsically good) initial assignment. Index Terms-3D-integration, general assignment problem, heuristic methods, multi-processor system-on-chip, network-onchip, performance optimization, routing algorithm, taboo search. I. INTRODUCTION W ITH 3-D integration a large field of research has opened including topics from TSV technology to high-level system design and configuration issues. Now besides traditional design issues, designers must tackle with emerging 3-D-specific challenges too and many issues that have been already solved for 2-D (planar), need to be restudied in 3-D integrated systems. The incorporation of the third dimension in the design of systems-on-chip (SoCs) allows the use of 3-D networkson-chip (3-D-NoCs) and thus the exploitation of 3-D topologies [1]-[4] which result in a major improvement in the network performance [5]. Supposing a NoC with a complete 3-D-mesh topology, the number of vertical links is equal to 2(N − 3 √ N 2) where N is the number of network nodes. Since generally each NoC link consists of tens, and even in some architectures, hundreds of physical wires, networks with large number of nodes require huge number of TSVs. On the other hand, the yield and active area (and thus the cost) are function of the number of TSVs [6]. Thus, the Manuscript

In this paper, we propose a distributed routing algorithm for vertically partially connected regular 2D topologies of different shapes and sizes (e.g., 2D mesh, torus, ring). The topologies that are the target of this algorithm are of practical interest in the 3D integration of heterogeneous dies using Through-Silicon-Vias (TSVs). Indeed, TSV-based 3D integration allows to envision the stacking of dies with different functions and technologies, using as an interconnect backbone a 3D-NoC. Intrinsically, 3D topologies have better performances, but yield and active area (and thus the cost) are function of the number of TSVs; therefore, the designs tend to use only a subset of available TSVs between two dies. The definition of blockage free and low implementation cost distributed deterministic routing on this kind of topology is thus of theoretical and practical interests. We formally prove that independently of the shape and dimensions of the planar topologies and of the number and placement of the TSVs, the proposed routing algorithm using two virtual channels in the plane is deadlock and livelock free. We also experimentally show that the performance of this algorithm is still acceptable when the number of vertical connections decreases.

Modern parallel and distributed applications have a wide range of communication characteristics and performance requirements. These diverse characteristics affect the performance and suitability of particular routing and switching policies in multihop point-to-point networks. In this paper, we identify a core set of architectural features necessary for flexible selection and implementation of multiple routing and switching schemes. Using this, we present a flexible router whose routing and switching policies can be tailored to the application, allowing the network to meet these diverse needs. By dedicating a small programmable processor to each incoming link, we can implement wormhole, virtual cut-through, and packet switching, as well as hybrid switching schemes, each under a variety of unicast and multicast routing algorithms. In addition, a flexible router can support several applications or traffic types simultaneously, enabling better support of applications with multiple traffic classes. We have designed, implemented, and fabricated the Programmable Routing Controller (PRC). Cycle-level simulations of mesh-connected PRCs also demonstrate that flexible routing and switching can significantly enhance application performance.

Network coding is one of the important researches in multi-hop wireless networks domain and it widely participates in improving the performance of these networks, since it benefits from the broadcasting nature of transmission processes to transmit more than single packet in one broadcasting transmission. So it achieves double use of the available bandwidth, which can increase the throughput of the network and reduce the congestion. Our aim in this research is to verify the improvement that network coding presents to the performance of multi-hops wireless Ad Hoc networks . In this paper, we propose the Network Coding Routing (NC_ DSR) protocol modified from the DSR routing protocol with respect to the path discovery process and consists of a new set of coding conditions, and new routing metric that takes into consideration both coding opportunities and network workload. Comprehensive simulation studies showed that the proposed protocol gives good performance for this type of network.
Keywords: Wireless ad hoc networks, Network coding, Routing metrics, Coding conditions.

Network‐on‐Chip (NoC) is a key component in chip multiprocessors (CMPs) as it supports communication between many cores. NoC is a network‐based communication subsystem on an integrated circuit, most typically between modules in a system on a chip (SoC). Designing a reliable NoC against failures that can prevent failure using some measures or preventing error or system failure while failure happens and proper performance became a significant concern. For a reliable design against failures, first, the system should be analysed to discover the critical points. Hence, in this research, it is tried first to investigate the scale of fault tolerance effect on the mechanism in the router on the network by injecting simulated errors, and then these errors are prevented. As the major novelty, the authors implemented a router on a synchronised network and calculated the network buffering fault tolerance by injecting error in the buffer. Specifically, a new method for improving fault tolerance ...

The advent of the multicore era [1, 2] has made the execution of more complex software applications more efficient and faster. On-chip communication among the processing cores, in the form of packetized messages, is managed with the use of on-chip networks (NoCs) [3]. Routers handling on-chip communication are point-to-point topologically interconnected using parallel links laid onto the silicon surface comprising a number of individual parallel wires. With the underlying interconnect structure becoming denser, due to improvements in CMOS technology, parallel links become susceptible to wear-out [4], with permanent link failures inhibiting communication completely and indefinitely. It is hence critical to explore their failure patterns in the wires comprising these links and hence build mechanisms which can recover corrupted in-transit data [5, 6]; since no real data from chip manufacturers exist, the derivation of a mathematical model in aiding the understanding of the distribution of individual wire faults in parallel on-chip links becomes mandatory. This paper takes the first steps in such direction. First it is shown how the given problem reduces to an equivalent combinatorial problem through partitions and necklaces. Then a model that counts certain classes of necklaces is derived by making a separation between periodic and aperiodic cases. The model is tested against a brute-force algorithm to prove its exactness. Finally the obtained model is used in finding the probability distribution of the size of the fault segment of wires in a parallel NoC-based multicore chip.

Self-healing is increasingly becoming a promising approach to designing reliable digital systems, and it refers to the ability of a system to detect faults or failures and fix them through healing or repairing. Digital systems with architecture for self-healing are expected to compensate faults. However, there are a few research challenges that need to be overcome before self-healing becomes a mainstream approach. For example, current self-healing techniques face challenges such as scalability, reliability, area overhead, and mapping. This paper explains the self-healing concept and investigates the self-healing approaches related to digital design in the literature. It gives a general overview of the topic and explains levels of abstraction at which self-healing can be used: hardware level, application level, and system level. The paper presents multiple related works at each level of abstraction. In the faulted phase, different types of faults and fault detection methods are described. For the evaluation of a self-healing technique, this paper presents the parameters which can be used to evaluate a self-healing method. These parameters are redundancy rate, the maximum ratio of repair, self-healing time consumption, reliability, and area overhead. The paper also presents a comparison between previous works of self-healing in terms of evaluation techniques. Implementations using VHDL and ISE Xilinx Vertex-5 for self-healing on Embryonic Hardware (EmHW) and Network-on-Chip (NoC) are also presented. The simulation results show the contribution of self-healing to improve system reliability and mean time to failure.

This paper proposes a technique that mixes simulation and an analytical method to evaluate the characteristics of Networks-on-Chips (NoCs). The advantage of this technique is to reduce the simulation time by reducing the complexity of the NoC model while still obtaining accurate results for latency and throughput. The basis of this technique is: (i) to send the whole payload data at once in the packet header; (ii) to reduce the NoC simulation complexity by omitting the flit by flit payload forwarding; (iii) to use an algorithm for controlling the release of the packet trailer in order to close the connection at the right time. For the evaluation of this technique, an actor-oriented model of a NoC, JOSELITO, was created. Simulation results show that JOSELITO is in average 2.3 times faster in 88% of the executed case studies than the implementation without using the proposed technique. The worst case simulation results for latency and throughput have, respectively, 5.26% and 0.1% error compared to the corresponding Register Transfer Level (RTL) model. Categories and Subject Descriptors B.7.1 [Integrated Circuits]: Types and Design Styles-advanced technologies, VLSI (very large scale integration).

The increasing complexity of integrated circuits drives the research of new intra-chip interconnection architectures. A network-on-chip adapts concepts originated in the distributed systems and computer networks subject areas to connect IP cores in a structured and scalable way, pursuing the goal of achieving superior bandwidth to conventional intra-chip bus architectures. This paper presents the design of a switch targeted to a mesh interconnection topology. Each switch has 5 bi-directional ports, connecting 4 neighbor switches and a local IP core. They employ a XY routing algorithm, with input queue buffers. The main objective is to develop a switch with a small area, enabling its immediate practical use. The switch and a 2x2 mesh network were validated through functional simulation. Also the network has been successfully prototyped in hardware, using a million-gate FPGA.

Networks-on-Chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a methodology to automatically synthesize an architecture where a few application-specific long-range links are inserted on top of a regular mesh network. This way, we can better exploit the benefits of both complete regularity and partial customization. Indeed, our experimental results show that inserting application-specific long-range links significantly increases the critical traffic workload at which the network state transits from a free to a congested regime. This, in turn, results in a significant reduction in the average packet latency and a major improvement in the achievable network throughput.

Gunumuz haberlesme teknolojisinde kablosuz haberlesme sistemleri gun gectikce onem kazanmistir. Bir kablosuz mobil sistem dusunuldugunde, bu sistemin maliyet ve performansi one cikmaktadir. En onemli amaclardan bir tanesi de anteninin boyutu kuculdukce calisma frekansini degistirmeden verimli anten tasarimlari yapabilmektir. Bu baglamda, kucuk fiziksel boyutlarda verimli antenler yapmak gunumuzde onemli bir arastirma konusu olmustur. Bir anten tasariminda en onemli noktalardan bir tanesi fiziksel parametreleri ve kesit yontemleridir. Bu calismada toprak duzlem ve iletken duzlem uzerinde yapilan farkli ucgensel kesitlerle olusturulan 3,1 ve 14,1 GHz rezonans bant araliginda calisan bir ultra genis bant (UGB) mikroserit anten tasarimi sunulmustur. Tasarim asamasinda 1,59 mm kalinliginda 0,01 kayip tanjantli 4,4 dielektrik katsayili FR4 malzeme kullanilmistir. Tasarimin dort farkli evresi simulasyon sonuclari uzerinden S11 grafikleri ile karsilastirmali olarak analiz edilerek, ucgensel...