Multi-threading

Mobile devices continue to increase the number of cores in an attempt to meet the needs of performancedemanding applications. However, the increasing number of cores does not necessarily translate into performance gain and/or power reduction. In this paper we investigate how multi-core mobile devices are utilized by applications. Our results demonstrate that mobile applications are utilizing less than 2 cores on average, which shows that multi-cores are generally underutilized by today's mobile applications. Unless application developers can significantly improve core utilization, further increasing core counts will result in little gain.

Developing multithreaded programs in shared-memory systems is difficult. One key reason is the nondeterminism of thread interaction, which may result in one code input producing different outputs in different runs. Unfortunately, enforcing determinism by construction typically comes at a performance, hardware, or programmability cost. An alternative is to check during testing whether code is deterministic. This paper presents InstantCheck, a novel technique that checks determinism with a very small runtime overhead while requiring only a minor hardware extension. During code testing, Instant-Check can check whether the code under test ends up in a deterministic state in various runs. The idea is to compute a 64-bit hash of the memory state and compare the hashes of different test runs that have the same input. If two runs have different hashes, Instant-Check reports state nondeterminism. For efficient operation, In-stantCheck uses on-the-fly incremental hashing in hardware. The hash is kept in a per-core 64-bit register, which trivially supports virtualization, migration, and context switching. We use InstantCheck to understand the determinism properties of 17 popular applications, including Sphinx3, PBZip2, PARSEC, and SPLASH-2. InstantCheck incurs a negligible average runtime overhead of 0.3% over native testing runs. We also show how using InstantCheck programmers can find bugs and discuss other applications of fast memory-state hashing. While using InstantCheck, we found a real bug in the widely used PARSEC benchmark.

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In this paper we present a novel system for realtime, six degree of freedom visual simultaneous localization and mapping using a stereo camera as the only sensor. The system makes extensive use of parallelism both on the graphics processor and through multiple CPU threads. Working together these threads achieve real-time feature tracking, visual odometry, loop detection and global map correction using bundle adjustment. The resulting corrections are fed back into to the visual odometry system to limit its drift over long sequences. We demonstrate our system on a series videos from challenging indoor environments with moving occluders, visually homogenous regions with few features, scene parts with large changes in lighting and fast camera motion. The total system performs its task of global map building in real time including loop detection and bundle adjustment on typical office building scale scenes.

The ever decreasing transistor size has made it possible to integrate multiple cores on a single die. On the downside, this has introduced reliability concerns as smaller transistors are more prone to both transient and permanent faults. However, the abundant extra processing resources of a multicore system can be exploited to provide fault tolerance by using redundant execution. We have designed a library for multicore processing, that can make a multithreaded user-level application fault tolerant by simple modifications to the code. It uses the abundant cores found in the system to perform redundant execution for error detection. Besides that, it also allows recovery through checkpoint/rollback. Our library is portable since it does not depend on any special hardware. Furthermore, the overhead (up to 46% for 4 threads), our library adds to the original application, is less than other existing approaches, such as Respec. Creates/Starts on error/ Kills when taking next checkpoint Creates/Kills on error Creates/Signals Starts on timeout error Kills on timeout error Kills on error Kills on timeout error Reads Writes

In recent years, multi-core systems have become mainstream in computer industry. The design of multi-cores takes advantage of thread-level parallelism in emerging applications that are computationally intensive and highly parallel. Energy efficiency is one of the biggest challenges in the design of multi-core systems, and workload imbalance among parallel threads is one of sources of energy inefficiency. Many techniques based on dynamic voltage frequency scaling (DVFS) are proposed to save energy consumptions on multi-cores, but all of them assume that each core in a multi-core system contains only one hardware context and only one thread can execute on one core at a time. However, mainstream multi-core systems are moving to have simultaneous multithreading (SMT) support in cores, and existing DVFS-based techniques are not effective to achieve maximum energy savings. In this paper, we present a novel technique called thread shuffling, which combines thread migration and DVFS to achieve maximum energy savings and maintain performance on a multi-core system supporting SMT. Thread shuffling is implemented and simulated in a cycle-accurate x86 multicore system. The experiments show that it achieves up to 56% energy savings without performance penalty for selected Recognition, Mining and Synthesis (RMS) applications from Intel Labs.

In recent years, multi-core systems have become mainstream in computer industry. The design of multi-cores takes advantage of thread-level parallelism in emerging applications that are computationally intensive and highly parallel. Energy efficiency is one of the biggest challenges in the design of multi-core systems, and workload imbalance among parallel threads is one of sources of energy inefficiency. Many techniques based on dynamic voltage frequency scaling (DVFS) are proposed to save energy consumptions on multi-cores, but all of them assume that each core in a multi-core system contains only one hardware context and only one thread can execute on one core at a time. However, mainstream multi-core systems are moving to have simultaneous multithreading (SMT) support in cores, and existing DVFS-based techniques are not effective to achieve maximum energy savings. In this paper, we present a novel technique called thread shuffling, which combines thread migration and DVFS to achieve maximum energy savings and maintain performance on a multi-core system supporting SMT. Thread shuffling is implemented and simulated in a cycle-accurate x86 multicore system. The experiments show that it achieves up to 56% energy savings without performance penalty for selected Recognition, Mining and Synthesis (RMS) applications from Intel Labs.

Future generations of processors will exhibit an increase of faults over their lifetime, and it becomes increasingly expensive to solve the resulting reliability issues purely at the hardware level. We propose to model computations in terms of restartable task graphs in order to improve reliability at the software level. As a proof of concept, we present Cobra, a novel design for a shared-memory work-stealing scheduler that realizes this notion of restartable task graphs, and enables computations to survive hardware failures due to soft errors. A comparison with the work-stealing scheduler of Threading Building Blocks on the PARSEC benchmark suite shows that Cobra incurs no performance overhead in the absence of failures, and low performance overheads in the presence of single and multiple failures.

We present an extension of Astree to concurrent C software. Astree is a sound static analyzer for run-time errors previously limited to sequential C software. Our extension employs a scalable abstraction which covers all possible thread interleavings, and soundly reports all run-time errors and data races: when the analyzer does not report any alarm, the program is proven free from those classes of errors. We show how this extension is able to support a variety of operating systems (such as POSIX threads, ARINC 653, OSEK/AUTOSAR) and report on experimental results obtained on concurrent software from different domains, including large industrial software.

This thesis examines the parallelization techniques that can be used to speed up econometric computations. Specifically, Monte Carlo simulations implemented using the R programming language. Parallelized Monte Carlo simulations can use multiple processing elements simultaneously, thereby providing answers to computational problems quicker. Three Monte Carlo experiments were examined; a Monte Carlo estimation of the performance of a Bootstrap confidence interval, a Monte Carlo estimation of a Maximum Likelihood Estimation, and the Metropolis-Hastings Independence Chain algorithm. Each experiment was implemented using multiple parallelization techniques, which were tested using multiple parallelization distribution methods. Analysis of the parallel programs shows that parallel Monte Carlo simulations with coarsegrained subproblems, i.e., relatively large subproblems, perform better compared to programs with fine-grained subproblems. The impact of the granularity of the subproblems also appears to increase as the delay between processing elements increases.

With significant advances in network interfaces, I/O bus, and processor architecture of end node, innovative approaches are required to achieve high network bandwidth by fully utilizing available system resources. The issues related can be summarized into two: i) Utilizing I/O bus bandwidth for high bandwidth network connection and ii) Utilizing multiple cores for high packet processing throughput. In this paper, we conduct several experiments on a multi-core system with 10GigE and multi-port 1GigE network interfaces. We aim to show the impact of system configurations on the network performance and compare the performance of two different network interfaces. The experimental results show that, with the proper interrupt affinity configurations, the multi-port 1GigE can achieve comparable bandwidth to 10GigE. The peak bandwidth achieved by the multi-port 1GigE is 6.7Gbps, which is more than 80% of the theoretical maximum I/O bus bandwidth on the experimental system. We, however, also show that the multi-port 1GigE can consume much more processor resource than 10GigE. More importantly, we reveal that processing the packets on many cores can result in more resource consumption without much benefit. This can be because of locking overhead between softirqs running on different cores and lower cache efficiency. We show that the more tuning on the configuration cannot overcome this side effect.

Within the world of parallel programming, the quest for optimal performance results is an ongoing challenge. As modern computer systems continue to evolve with an increasing number of processor cores, the need for efficient parallelization becomes paramount. Multi-threaded programming emerges as a powerful tool in this context, offering a means to harness the full potential of multi-core processors. This essay explores the integration of multi-threaded programming techniques within the parallel programming paradigm to achieve the most efficient performance results. It will examine the principles of multi-threaded programming, its advantages, and challenges, and provide insights into best practices for its effective utilization that illustrate the benefits and complexities of such an approach.

Thread merupakan salah satu komponen fundamental dalam sistem operasi modern yang berfungsi untuk meningkatkan efisiensi dan performa dalam pemrosesan tugas secara paralel. Modul ini membahas konsep thread, perbedaan antara proses dan thread, serta model threading seperti multithreading, user-level threads, dan kernel-level threads. Selain itu, dibahas pula mekanisme manajemen thread, seperti pembuatan, penjadwalan, dan sinkronisasi, yang berperan penting dalam memastikan eksekusi tugas berjalan optimal tanpa terjadinya deadlock atau race condition. Melalui modul ini, pembaca diharapkan memahami bagaimana thread bekerja dalam konteks sistem operasi, penerapan thread dalam lingkungan komputasi modern, serta tantangan yang dihadapi dalam desain dan implementasi sistem berbasis thread.

Assalamua'alaikum wr. wb. Puji dan syukur senantiasa kami panjatkan ke hadirat Allah SWT atas limpahan nikmat, rahmat, dan karunia-Nya, sehingga kami dapat menyelesaikan penyusunan modul ini dengan baik. Shalawat serta salam senantiasa tercurah kepada junjungan kita Nabi Muhammad SAW, keluarganya, sahabatnya, serta seluruh umatnya hingga akhir zaman. Semoga kita semua mendapatkan syafa'at beliau di hari kiamat kelak. Aamiin Yaa Rabbal 'Alamin. Alhamdulillah, atas izin dan pertolongan Allah SWT, modul ini yang berjudul "Konkurensi" dapat terselesaikan dengan baik. Modul ini disusun untuk memberikan pemahaman yang mendalam mengenai konsep dan implementasi konkurensi, dengan harapan dapat menjadi bahan bacaan dan referensi yang bermanfaat bagi pembaca. Kami menyadari bahwa dalam penyusunan modul ini masih terdapat kekurangan dan keterbatasan, baik dari segi isi maupun penyajiannya. Oleh karena itu, kami dengan senang hati menerima kritik dan saran yang membangun untuk penyempurnaan modul ini di masa yang akan datang. Semoga modul ini dapat membantu pembaca dalam memahami topik yang disajikan dengan lebih mudah dan jelas. Akhir kata, kami berharap segala upaya yang telah kami curahkan dalam penyusunan modul ini mendapatkan ridha Allah SWT dan dapat memberikan manfaat bagi pembaca. Semoga Allah SWT senantiasa melimpahkan rahmat dan karunia-Nya kepada kita semua serta menjadikan amal ini bernilai ibadah di sisi-Nya. Aamiin Yaa Rabbal 'Alamin. Wassalamu'alaikum wr. wb.

Puji syukur kita panjatkan kehadirat Allah SWT yang telah memberikan kemudahan dan kesehatan kepada kami sehingga kami mampu menyelesaikan modul ini dengan tepat waktu. Tidak lupa, tim penyusun atau kelompok delapan ingin mengucapkan terima kasih kepada Bapak Mirza Sutrisno, S.SI., M.KOM selaku dosen mata kuliah Sistem Operasi yang sudah membantu kami dalam prosespembelajarannya. Modul yang berjudul "Thread" disusun oleh kami selaku kelompok enam untuk memenuhi modul pada mata kuliah Sistem Operasi. Harapan kami, modul ini bisa memberikan manfaat sebesar mungkin bagi siapa pun yang membacanya. Kami pun mengetahui jika modul yang sudah digarap masih jauh dari kata sempurna. Masih banyak kekurangan sehingga kami sangat berharap saran dan kritiknya kepada kami agar di kemudian hari kami bisa membuat suatu modul yang lebih berkualitas. Semoga para pembaca juga berkenan memaafkan jika dalam tugas besar ini terdapat kekurangan dan kesalahan. Terakhir, kami berharap semoga modul ini bisa memberi manfaat yang banyak bagi pembaca.

The goal of this research is to find out the effects of multithreading on the consumption of system resources and efficiency by examining CPU utilization, memory use, Input/Output operation, and power consumption in the multithreaded systems. In order to measure static, adaptive, and dynamic multithreading performance under different workloads, the study compares the three models both through theory and by applying it to various experiments. That is why the results show that, when multithreading is implemented, the general CPU load and I/O performance improve, especially for computational and data-consuming operations. However, some problems include memory contention, context-switching overhead and, higher energy consumption are noted especially when threading is over-provisioned for. Real-time threading control strategies were the most effective as they periodically reconfigured the number of threads in a way that optimizes performance while optimizing resources. In addition, while the asynchronous I/O models provided the best performance improvements, energy use went up when multithreading was incorporated, thus the need for implementing trade-offs between performance and power usage. It offers significant findings related to the tuning of multithreading strategies so as to maximize system performance but with an acceptable level of resource utilization, should be of significance for practitioners, who are working with multicore processors and dealing with high-performing systems.

To achieve stable and transparent telemanipulation, one needs to overcome the common communication problems and assure a compliant motion of the telemanipulator in the remote environments. This paper addresses i) stability conditions for the application in packet switched networks with time varying communication latencies and packet loss, as e.g. the Internet, and discusses the impact of the packet processing protocol on the stability and the performance, and ii) investigates the manipulation and control problems of a teleoperated redundant manipulator, equipped with a stiffness control algorithm. I. I NTRODUCTION The goal of multimodal telemanipulation also called telepresence systems is to enable a human operator to actively perform complex manipulation tasks in possibly distant or differently scaled remote environment. Application areas reach from telemanufacturing and telemaintenance to telesurgery and rescue applications. A multimodal telepresence system is shown in Fig. 1. The...

In the context of foreign economical relations, the main aim for the Republic of Moldova is the agri-food trade diversification without intermediaries that can transform it from a poor country in a prosperous one. The consumer's needs, preferences and their satisfaction require a higher effort that leads to strong competition on the agri-food markets. The above mentioned lead to positive changes on the agri-food market by being considerably diversified the assortment of products. As a result, Moldova's agri-food trade relations with the World requires the modernization of the given sector by increasing the amount of manufacturing products with high value-added, supply diversification of exported products and markets.

Recent safety standards set stringent requirements for the target fault coverage in embedded microprocessors, with the objective to guarantee robustness and functional safety of the critical electronic systems. This motivates the need for improving the quality of test generation for microprocessors. A new high-level implementationindependent test generation method for RISC processors is proposed. The set of instructions of the processor is partitioned into groups. For each group, a dedicated test template is created, to be used for generating two test programs, for testing the control and the data paths respectively. For testing the control part, a novel high-level control fault model is proposed. Using this model, a set of deterministic test data operands are generated for each instruction of the given group. The advantage of the high-level fault model is that it covers larger than SAF fault class including multiple fault coverage in the control part. For generating the data path test, pseudoexhaustive data operands are used. We investigated the feasibility of the approach and demonstrated high efficiency of the generated test programs for testing the execute module of the miniMIPS RISC processor.

Within the world of parallel programming, the quest for optimal performance results is an ongoing challenge. As modern computer systems continue to
evolve with an increasing number of processor cores, the need for efficient parallelization becomes paramount. Multi-threaded programming emerges as a
powerful tool in this context, offering a means to harness the full potential of multi-core processors. This essay explores the integration of multi-threaded
programming techniques within the parallel programming paradigm to achieve the most efficient performance results. It will examine the principles of
multi-threaded programming, its advantages, and challenges, and provide insights into best practices for its effective utilization that illustrate the benefits
and complexities of such an approach.

This paper proposes a concurrency model which integrates the asynchronous and event-driven nature of networked sensors with a more familiar programming style for the developer. We argue that coroutines can provide a basis for this integration and describe some details of its implementation, which was developed as an extension to the TinyOS operating system.

Field-programmable gate arrays (FPGA's) have come a long way from the days when they served primarily as glue logic and prototyping devices. Today's FPGA's have matured to the level where they can host a significant number of programmable gates and CPU cores to create complete System on Chip (SoC) hybrid CPU+FPGA devices. These hybrid chips promise the potential of providing a unified platform for seamless implementation of hardware and software co-designed components. Realizing the potential of these new hybrid chips requires a new high-level programming model, with capabilities that support a far more integrated view of the CPU and the FPGA components than is achievable with current methods. Adopting a generalized programming model can lead to programming productivity improvement, while at the same time providing the benefit of customized hardware from within a familiar software programming. Achieving abstract programming capabilities across the FPGA/CPU boundary requires adaptation of a high-level programming model that abstracts the FPGA and CPU components, bus structure, memory, and low-level peripheral protocol into a transparent computational platform [2]. This thesis presents research on extending the multithreaded programming model across the CPU/FPGA boundary. Our objective was to create an environment to support concurrent executing hybrid threads distributed flexibly across CPU and FPGA assets. To support this generalized model across the FPGA, we have developed a Hardware Thread Interface (HWTI) that encapsulates mechanisms to support synchronization for FPGA based threads. The HWTI enables custom threads within the FPGA to be created, accessed, and synchronized with all other system threads through library API's. Additionally, the HWTI is capable of managing "thread state", accessing data across the system bus, and executing independently without the need to use CPU. Current multithreaded programming models use synchronization mechanisms such as semaphores to enforce mutual exclusion on shared resources. Semaphores depend on atomic operations provided through the CPU assembler instruction set. In multiprocessor systems, atomic operations are achieved by combinations of processor condition instructions integrated within memory coherency protocol of snooping data caches. Since these current mechanisms do not extend well to FPGA based threads, we have developed new semaphore mechanisms that are processor family independent. We achieve a much simpler solution and faster mechanisms (8 I would like to express my sincere appreciation and gratitude to everyone who made this thesis possible. First and foremost, I would to thank my adviser Dr. David Andrews for his guidance, encouragement and patience throughout the tenure of this research. From him, I hope that I have learned enough to conduct research, to write and publish papers.

Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative optimization. As we move to a multicore hybrid design, fine grained conflicts for shared data can violate the atomicity requirement of these blocks and lead to expensive squashes and rollbacks. However, as these atomic regions differ from those used in checkpointing and transactional memory systems, the extent of this potentially prohibitive problem remains unclear, and mechanisms to mitigate these squashes dynamically may be critical to enable a highly performant multicore hybrid design. In this work, we investigate how multithreaded applications, both benchmark and commercial workloads, are affected by squashes, and present dynamic mechanisms for mitigating these squashes in hybrid processors. While the current wisdom is that there is not a significant number of squashes for smaller atomic regions, we observe this is not the case for many multithreaded workloads. With region sizes of just 200 -500 instructions, we observe a performance degradation ranging from 10% to more than 50% for workloads with a mixture of shared reads and writes. By harnessing the unique flexibility provided by the software subsystem of hybrid processor design, we present BlockChop, a framework for dynamically mitigating squashes on multicore hybrid processors. We present a range of squash handling mechanisms leveraging retrials, interpretation, and retranslation, and find that BlockChop is quite effective. Over the current response to exceptions and squashes in a hybrid design, we are able to improve the performance of benchmark and commercial workloads by 1.4x and 1.2x on average for large and small region sizes respectively.

Transactional Memory (TM) is a technique that aims to mitigate the performance losses that are inherent to the serialization of accesses in critical sections. Some studies have shown that the use of TM may lead to performance improvements, despite the existence of management overheads. However, the relative performance of TM, with respect to classical critical sections management depends greatly on the actual percentage of times that the same data is handled simultaneously by two transactions. In this paper, we compare the relative performance of the critical sections provided by OpenMP with respect to two Software Transactional Memory (STM) implementations. These three methods are used to manage concurrent data accesses in ATLaS, a software-based, Thread-Level Speculation (TLS) system. The complexity of this application makes it extremely difficult to predict whether two transactions may conflict or not, and how many times the transactions will be executed. Our experimental results show that the STM solutions only deliver a performance comparable to OpenMP when there are almost no conflicts. In any other case, their performance losses make OpenMP the best alternative to manage critical sections.

The threadblock size and shape choice is one of the most important user decisions when a parallel problem is coded to run in GPU architectures. In fact, threadblock configuration has a significant impact on the global performance of the program. Unfortunately, the programmer has not enough information about the subtle interactions between this choice of parameters and the underlying hardware. This paper presents uBench, a suite of micro-benchmarks, in order to explore the impact on performance derived from the combination of (1) the threadblock size and shape choice criteria, and (2) the GPU hardware resources and configurations. Each micro-benchmark has been designed as simple as possible to focus on a single effect derived from the hardware or threadblock parameter choice. As an example of the capabilities of this benchmark suite, this paper shows an experimental evaluation of the Fermi architecture, in terms of configuration parameters. This study confirms some previous experimental results and gives new insights on the influence of these parameters on the performance delivered by this GPU architecture.

This paper is the digital version of a chapter taken from his final thesis entitled "Compensation of Geodetic Networks". This is chapter V "Methods of Resolution " of the thesis. It concerns the methods for solving the equations of linear systems encountered during compensation calculations for geodetic networks using the least squares method.

This paper presents a novel microarchitecture to exploit trace-level speculation by means of two threads working cooperatively in a speculative and non-speculative way respectively. The architecture presents two main benefits: (a) no significant penalties are introduced in presence of a misspeculation and (b) any type of trace predictor can work together with this proposal. In this way, aggressive trace predictors can be incorporated since misspeculations do not introduce significant penalties. We describe in detail TSMA (Trace-Level Speculative Multithreaded Architecture) and present some initial results to show the benefits of this proposal. We show how simple trace predictors achieve significant speed-up in the majority of the cases. Concretely, results of a simple trace speculation mechanism results in an average speed-up of 16%.

Sinkronisasi proses adalah konsep dasar di bidang Sistem Operasi, yang penting untuk mengelola
beberapa proses atau thread secara bersamaan secara efektif. Sinkronisasi merupakan suatu proses secara
bersama-sama dan saling berbagi data bersama dapat mengakibatkan race condition atau inkosistensi data.
Dalam ilmu komputer, sinkronisasi mengacu pada salah satu dari dua proses yang berbeda tetapi terkait yaitu,
sinkronisasi proses dan sinkronisasi data.
Perangkat Sinkronisasi adalah intruksi Test-and-set adalah intruksi atomik yang dapat digunakan untuk
menangani masalah Critical Section. Salah satu syarat tercapainya sinkronisasi ialah harus tercipta suatu
kondisi yang mutual exclusive, yaitu kondisi dimana hanya ada sebuah proses yang sedang dieksekusi. Pada
pendekatan perangkat keras ini ditekankan bagaimana caranya agar kondisi mutual exclusive itu tercapai.
Pendekatan dari sisi perangkat keras dapat dibagi menjadi dua:
1. Processor Synchronous
2. Memory Synchronous
Manfaat Sinkronisasi adalah sebagai penyimpanan data sementara dan non sementara agar dapat
mempermudah pekerjaan. Jika suatu proses sedang menjalankan Crirical Section, maka proses lain tidak bisa
masuk kedalam Critical Section tersebut.
Dengan memahami proses dan perangkat sinkronisasi, diharapkan pembaca dapat mengapresiasi
kompleksitas dan pentingnya manajemen proses dalam sistem komputasi. Makalah ini bertujuan untuk
memberikan wawasan mendalam tentang bagaimana sinkronisasi dapat dicapai melalui penggunaan
perangkat sinkronisasi.

Robustness is a key issue on any runtime system that aims to speed up the execution of a program. However, robustness considerations are commonly overlooked when new software-based, thread-level speculation (STLS) systems are proposed. This paper highlights the relevance of the problem, showing different situations when the use of incorrect data can irreversibly alter the speculative execution of an algorithm, despite the efforts of a given STLS system to maintain sequential consistency. We show that the management of speculative exceptions is a common factor to these problems. Based on this fact, we propose a novel solution to handle speculative exceptions. Our solution eagerly tries to solve the issue before the non-speculative thread arrives to the instruction that rose the exception. We compare our solution to a more conservative approach found in the bibliography. The comparison is done both qualitatively, through a detailed analysis of the tradeoffs involved, and quantitatively, evaluating the effects of both solutions in the execution of three different benchmarks on a real system. Both studies conclude that our solution handles the occurrence of speculative exceptions more efficiently. Under heavy loads intended to push to its limits a STLS system, our solution leads to execution times reduced by up to 52.02% with respect to earlier proposals. Our solution does not affect the performance when speculative exceptions do not appear. We believe that our proposal makes STLS systems robust enough to be used in production environments.

We investigate a parallelization strategy for dense matrix factorization (DMF) algorithms, using OpenMP, that departs from the legacy (or conventional) solution, which simply extracts concurrency from a multithreaded version of BLAS. This approach is also different from the more sophisticated runtime-assisted implementations, which decompose the operation into tasks and identify dependencies via directives and runtime support. Instead, our strategy attains high performance by explicitly embedding a static look-ahead technique into the DMF code, in order to overcome the performance bottleneck of the panel factorization, and realizing the trailing update via a cache-aware multi-threaded implementation of the BLAS. Although the parallel algorithms are specified with a highlevel of abstraction, the actual implementation can be easily derived from them, paving the road to deriving a high performance implementation of a considerable fraction of LAPACK functionality on any multicore platform with an OpenMP-like runtime.

We propose two novel techniques for overcoming load-imbalance encountered when implementing so-called look-ahead mechanisms in relevant dense matrix factorizations for the solution of linear systems. Both techniques target the scenario where two thread teams are created/activated during the factorization, with each team in charge of performing an independent task/branch of execution. The first technique promotes worker sharing (WS) between the two tasks, allowing the threads of the task that completes first to be reallocated for use by the costlier task. The second technique allows a fast task to alert the slower task of completion, enforcing the early termination (ET) of the second task, and a smooth transition of the factorization procedure into the next iteration. The two mechanisms are instantiated via a new malleable thread-level implementation of the basic linear algebra subprograms, and their benefits are illustrated via an implementation of the LU factorization with partial pivoting enhanced with look-ahead. Concretely, our experimental results on an Intel-Xeon system with 12 cores show the benefits of combining WS+ET, reporting competitive performance in comparison with a task-parallel runtime-based solution. INDEX TERMS Solution of linear systems, multi-threading, workload balancing, thread malleability, basic linear algebra subprograms (BLAS), linear algebra package (LAPACK).

We investigate how to leverage the heterogeneous resources of an Asymmetric Multicore Processor (AMP) in order to deliver high performance in the reduction to condensed forms for the solution of dense eigenvalue and singular-value problems. The routines that realize this type of two-sided orthogonal reductions (TSOR) in LAPACK are especially challenging, since a significant fraction of their floating-point operations are cast in terms of memory-bound kernels while the remaining part corresponds to efficient compute-bound kernels. To deal with this scenario: 1) we leverage implementations of memory-bound and compute-bound kernels specifically tuned for AMPs; 2) we select the algorithmic block size for the TSOR routines via a practical model; and 3) we adjust the type and number of cores to use at each step of the reduction. Our experiments validate the model and assess the performance of our asymmetry-aware TSOR routines, using an ARMv7 big.LITTLE AMP, for three key operations: the reduction to tridiagonal form for symmetric eigenvalue problems, the reduction to Hessenberg form for non-symmetric eigenvalue problems, and the reduction to bidiagonal form for singular-value problems.

Dense linear algebra libraries, such as BLAS and LAPACK, provide a relevant collection of numerical tools for many scientific and engineering applications. While there exist high performance implementations of the BLAS (and LAPACK) functionality for many current multi-threaded architectures, the adaption of these libraries for asymmetric multicore processors (AMPs) is still pending. In this paper we address this challenge by developing an asymmetry-aware implementation of the BLAS, based on the BLIS framework, and tailored for AMPs equipped with two types of cores: fast/power hungry versus slow/energy efficient. For this purpose, we integrate coarsegrain and fine-grain parallelization strategies into the library routines which, respectively, dynamically distribute the workload between the two core types and statically repartition this work among the cores of the same type. Our results on an ARM R big.LITTLE TM processor embedded in the Exynos 5422 SoC, using the asymmetry-aware version of the BLAS and a plain migration of the legacy version of LAPACK, experimentally assess the benefits, limitations, and potential of this approach.

This research was sponsored by Microsoft, Intel, and IBM. The views and conclusions contained in this document are those of the author and should not be interpreted as representing the official policies, either expressed or implied, of any sponsoring institution, the U.S. government or any other entity.

Stream processing is becoming an area of active research in computer architecture. Many applications, including media and signal processing, image compression, and scientific applications can be speeded up by several orders of magnitude by processing them with stream processors[1][6]. However, compiling the applications efficiently in order to exploit the underlying architectural capabilities of stream processors is still an unsolved problem. Brook[2] and StreamC[5] are examples of two languages that are used to write stream applications. Brook is a general purpose streaming language that is capable of targeting any stream processor. Brook is very similar to C, making it easy to code and also cast other existing applications in C-like language to Brook. StreamC, on the other hand, is a special purpose streaming language that is specific to Imagine [1]. Applications written in StreamC are optimized to run efficiently on Imagine. Hence, an automatic compilation of Brook to StreamC will help to write a stream application in a high level language, and, at the same time, run an optimized version of the application on Imagine. The objective of this project is three-folds. First, develop a compiler framework for automatically compiling Brook to StreamC. Second, exercise the compiler framework on a scientific application (StreamMD) in order to test the correctness of the compiler. Finally, add optimizations to the compiler, in order to produce StreamC code that is optimized to run on the Imagine hardware.

Intrusion detection systems (IDS) are one way to tackle the increasing number of attacks that exploit software vulnerabilities. However, the construction of such a security system is a delicate process involving: (i) the acquisition of the monitored program behavior and its storage in a compact way, (ii) the generation of a monitor detecting deviances in the program behavior. These problems are emphasized when dealing with complex or parallel programs. This paper presents a new approach to automatically generate a dedicated and customized IDS from C sources targeting multi-threaded programs. We use Petri Nets to benefit from a formal description able to compactly describe parallel behaviors. Obtained models can then be enhanced with extra requirements such as resources usage limits or temporal execution bounds by means of observers. We illustrate the benefits of our approach on a recent class of attacks targeting web servers.

Take a multicore Digital Signal Processor (DSP) chip designed for cellular base stations and radio network controllers, add floating-point capabilities to support 4G networks, and out of thin air a HPC engine is born. The potential for HPC is clear: It promises 128 GFLOPS (single precision) for 10 Watts; It is used in millions of network related devices and hence benefits from economies of scale; It should be simpler to program than a GPU. Simply put, it is fast, green, and cheap. But is it easy to use? In this paper, we show how this potential can be applied to general-purpose high performance computing, more specifically to dense matrix computations, without major changes in existing codes and methodologies, and with excellent performance and power consumption numbers. Index Terms-Low-power architectures, DSPs, linear algebra.

Safety property checking is mandatory in the validation process of critical software. When formal verication tools fail to prove some properties, the automatic generation of counterexamples for a given loop depth is an important issue in practice. We investigate in this paper the capabilities of constraint-based bounded model checking for program verication and counterexample generation on real applications. We introduce DPVS (Dynamic Post-condition Variable driven Strategy), a new backjumping strategy we developed to handle an industrial application from a car manufacturer, the Flasher Manager. This backjumping strategy is used to search a faulty path and to collect the constraints of such a path. The simplied control ow graph (CFG) of the program is explored in a backward way, starting from the post-condition and jumping to the most promising node where the variables of the post-condition are dened. In other words, the constraints are collected by exploring the CFG in a dynamic and non-sequential backward way. The Flasher Manager application has been designed and simulated using the Simulink platform. However, this module is concretely embedded as a C program in a car computer, thus we have to check that the safety properties are preserved on this C code. We report experiments on the Flasher Manager with our constraint-based bounded model checker, and with CBMC, a state-ofthe-art bounded model checker. Experiments show that

This paper presents a model-driven environment for HW/SW co-design and analysis of embedded systems based on the Unified Modeling Language, UML profiles for SystemC/multithread C, and the Abstract State Machine formal method. The environment supports a model-driven design methodology which provides a graphical high-level representation of hardware and software components, and allows C/C++/SystemC code generation from models, a reverse engineering process from code to graphical UML models, and a transparent and tool-assisted system validation and verification based on ASMs.