Inter-process communication

Races in Message Sequence Charts may lead to a bad interpretation of described behaviours, and are often considered as a design error. While there is a quadratictime algorithm detecting races in Basic Message Sequence Charts (BMSCs), the problem is undecidable for High-level Message Sequence Charts (HMSCs). To improve this negative situation for HMSCs, we introduce two new notions: a new concept of race called trace-race and an extension of the HMSC formalism with open coregions, i.e. coregions that can extend over more than one BMSC. We present three arguments showing benefits of our notions over the standard notions of race and HMSC. First, every trace-race-free HMSC is also race-free. Second, every race-free HMSC can be equivalently expressed as a trace-race-free HMSC with open coregions. Last, the trace-race detection problem for HMSC with open coregions is decidable and PSPACE-complete (the problem is in P if the number of processes and gates is fixed).

This position paper outlines a new network architecture that is based on the fundamental principle that networking is interprocess communication (IPC). In this model, application processes (APes) communicate via an IPC facility. The IPC processes that make up this facility provide a protocol that implements an IPC mechanism, and a protocol for managing distributed IPC (routing, security and other management tasks). Our architecture is recursive in that the IPC processes can themselves be APes requesting services from lower IPC facilities. We present the repeating patterns and structures in our architecture, and show how the proposed model would cope with the challenges faced by today's Internet (and that of the future).

In this paper we describe LiveNet, a flexible wearable platform intended for long-term ambulatory health monitoring with real-time data streaming and context classification. Based on the MIT Wearable Computing Group's distributed mobile system architecture, LiveNet is a stable, accessible system that combines inexpensive, commodity hardware; a flexible sensor/peripheral interconnection bus; and a powerful, light-weight distributed sensing, classification, and inter-process communications software architecture to facilitate the development of distributed real-time multi-modal and context-aware applications. LiveNet is able to continuously monitor a wide range of physiological signals together with the user's activity and context, to develop a personalized, data-rich health profile of a user over time. We demonstrate the power and functionality of this platform by describing a number of health monitoring applications using the LiveNet system in a variety of clinical studies that are underway. Initial evaluations of these pilot experiments demonstrate the potential of using the LiveNet system for real-world applications in rehabilitation medicine.

In this paper we describe LiveNet, a flexible wearable platform intended for long-term ambulatory health monitoring with real-time data streaming and context classification. Based on the MIT Wearable Computing Group's distributed mobile system architecture, LiveNet is a stable, accessible system that combines inexpensive, commodity hardware; a flexible sensor/peripheral interconnection bus; and a powerful, light-weight distributed sensing, classification, and inter-process communications software architecture to facilitate the development of distributed real-time multi-modal and context-aware applications. LiveNet is able to continuously monitor a wide range of physiological signals together with the user's activity and context, to develop a personalized, data-rich health profile of a user over time. We demonstrate the power and functionality of this platform by describing a number of health monitoring applications using the LiveNet system in a variety of clinical studies th...

This paper describes interprocess communication and process dispatching on the Intel 432. The primary assets of the facility are its generality and its usefulness in a wide range of applications. The conceptual model, supporting mechanisms, available interfaces, current implementations, and absolute and comparative performance are described.

A unified facility for interprocess communication and processor dispatching on the Intel 432 is described. The facility is based on a queuing and binding mechanism called a port. The goals and motivations for ports, both abstract and implementation views of them, and their absolute and comparative performance are described.

The Intel iAPX 432 is an object-based microcomputer which, together with its operating system iMAX, provides a multiprocessor computer system designed around the ideas of data abstraction. iMAX is implemented in Ada and provides, through its interface and facilities, an Ada view of the 432 system. Of paramount concern in this system is the uniformity of approach among the architecture, the operating system, and the language. Some interesting aspects of both the external and internal views of iMAX are discussed to illustrate this uniform approach.

This paper describes interprocess communication and process dispatching on the Intel 432. The primary assets of the facility are its generality and its usefulness in a wide range of applications. The conceptual model, supporting mechanisms, available interfaces, current implementations, and absolute and comparative performance are described. The Intel 432 is an object-based multiprocessor. There are two processor types: General Data Processors (GDPs) and Interface Processors (IPs). These processors provide several operating system functions in hardware by defining and using a number of processor-recognized objects and high-level instructions. In particular, they use several types of processor-recognized objects to provide a unified structure for both interprocess communication and process dispatching. One of the prime motivations for providing this level of hardware support is to improve efficiency of these facilities over similar facilities implemented in software. With greater eff...

A unified facility for interprocess communication and processor dispatching on the Intel 432 is described. The facility is based on a queuing and binding mechanism called a port. The goals and motivations for ports, both abstract and implementation views of them, and their absolute and comparative performance are described.

This paper presents a proposal of a language, based on synchronous active objects that introduces the CSP primitives into Java. The proposal does not use channels to realise the inter-process communications, but is shown to offer the same expressive power as the channel based solutions. The paper also shows that the rendezvous defined by CSP or our synchronous objects are very well adapted to the industrial development of event driven applications, handling simultaneously GUIs and accesses to remote applications.

This paper aims at discussing several issues, both theoretical and practical, concerning family communication: theories, roles, rules, conflicts, negotiation. The authors stress the interconnection between the social, economic, psychological and cultural factors which can, through effective communication, lead to good, trust-based relationships within families/at the family level. The Literature review section approaches the concepts of communication and family, while the Case study shows the objectives, activities and outcomes of a program implemented in South Africa and focused on parents' roles and duties within the family. It tackles issues linked to fatherhood, low literacy, domestic abuse, father absence, unemployment, and a wide array of other social and cultural factors pertaining to the social and economic conditions in this country. The paper also includes some recommendations concerning the adequate and efficient use of certain family communication forms, channels and feedback strategies.

This paper proposes a novel inter-process communication, between a virtual world manager with slow update rate and a haptic controller with fast update rate, which incorporates the integrated force given from the user to the world. High-speed refresh rate, generally 1kHz, is required to present, stiff virtual objects that, have spring-damper characteristic with haptic display. On the other hand, the managing of an interactive and rich virtual world that takes a lot of computational time makes the refresh rate as low as 10Hz, which is enough for perceptual cycle. The dividing of the process into two has been proposed to interact with such a world and inter-process communication between the processes has been discussed. Although the methods proposed previously work well on condition that the virtual world is static, goes wrong on dynamic world. The importance of the force integration on the object, motion acquisition is described and an inter-process communication that cares about the...

This paper describes a new architecture for high performance distributed applications and a supporting framework. This architecture applies object-oriented design and im plementation techniques to build a framework for platform-independent distributed ap plication specification and implementation using existing programming languages and operating systems. It utilizes an efficient and extensible layering architecture that al lows new abstract data types, new presentation-layer protocols, and new interprocess communication mechanisms to be added as they become necessary. Experimental re sults are presented demonstrating that the multiple layers of abstraction used do not compromise efficiency.

The proposed work explores the interprocess communication across communicating parallel tasks in a mobile cluster. The process which is linked with specific mobile or static nodes will not be resilient to the changing conditions of the mobile cluster. The proposed Mobile Distributed Pipes (MDP) model enables the location independent intertask communication among the processes executing in static and mobile nodes. This novel approach enables the migration of communicating parallel tasks during runtime, which occurs according to the context and location requirements. A transparent programming model for a parallel solution to Iterative Mobile Grid Computations (IMGC) using MDP is also proposed. The proposed model is resilient to the heterogeneity of nodes such as static or mobile and the changing conditions in the mobile cluster because of mobility. The design of runtime and functional library support for the proposed model is also presented.

The proposed work explores the interprocess communication across communicating parallel tasks in a mobile cluster. The process which is linked with specific mobile or static nodes will not be resilient to the changing conditions of the mobile cluster. The proposed Mobile Distributed Pipes (MDP) model enables the location independent intertask communication among the processes executing in static and mobile nodes. This novel approach enables the migration of communicating parallel tasks during runtime, which occurs according to the context and location requirements. A transparent programming model for a parallel solution to Iterative Mobile Grid Computations (IMGC) using MDP is also proposed. The proposed model is resilient to the heterogeneity of nodes such as static or mobile and the changing conditions in the mobile cluster because of mobility. The design of runtime and functional library support for the proposed model is also presented.

Introduction This PhD Thesis is the result of a four-year research project conducted at the Department of Functional Programming, the Faculty of Mathematics and Informatics, at the University of Nijmegen as 'Assistent-in-Opleiding' under supervision of Professor M.J. Plasmeijer. In this chapter we give a survey of the research project and its theses. 1.1 Functional programming and the Clean project 3 we will encounter some of these cases which show up because of the complexity of the I/O system. The functional programming language we consider in this PhD.Thesis is pure and lazy. Due to strong normalisation lazy functional languages are preferable over their eager relatives. However, lazyness complicates their implementation. In general lazy languages are less time and space efficient than eager languages, or imperative languages. A lot of research has been conducted in this area in the last decades, and is still continuing. One specific approach to investigate and provide solutions to the problems of efficient implementations of functional languages is the (Concurrent) Clean project. Clean is a sequential lazy, purely functional programming language (

PORT is a real-time operating system designed to operate over a large set of computer systems. It can run on computers with different architectures. It makes use of a common high-level language for both the system and application programs. As the system is implemented by the identical software on different hardware, it will have the similar interface to user programs. Hence, application programs which use PORT are highly portable. PORT enables viewing programs as networks of communicating processes by providing efficient interprocess communication primitives.

There have been many proposals of shared memory systems, each one providing different types of memory coherence for interprocess communication. However, they have usually been defined using different formalisms. This makes it difficult to compare among them the different proposals put forward. In this paper we present a formal framework for specifying memory models with different coherency properties. We specify most of the known shared memory models using our framework, showing some of the relationships that hold among them.

The nature of product modeling systems and related application programs for design and manufacture makes it difficult to integrate them into a consistent and dynamic environment. This has been especially true for rule-based application programs. Through the use of standardized functional interfaces and UNIX interprocess communication, an environment has been developed that allows modelers and application programs to behave like objects within the integration environment. Each modeler and application (objects in the system) runs as a separate process. Each object has specific methods associated with it and also incorporates the concepts of data hiding and encapsulation. The object-oriented approach creates an environment that is service oriented vs. the traditional data-oriented approach. The software that creates and controls this environment is called the Information Services Exchange (ISX). ISX is currently being used to implement a project sponsored by Computer Aided Manufacturing-International (CAM-I) aimed at integrating a wide range of product development software. The approach developed within ISX could have a significant effect on design of diverse and large-scale product development systems.

In this paper we present a cost-effective, high bandwidth server I/O network architecture, named PaScal (Parallel and Scalable). We use the PaScal server I/O network to support data-intensive scientific applications running on very large-scale Linux clusters. PaScal server I/O network architecture provides (1) bi-level data transfer network by combining high speed interconnects for computing Inter-Process Communication (IPC) requirements and low-cost Gigabit Ethernet interconnect for global IP based storage/file access, (2) bandwidth on demand I/O network architecture without rewiring and reconfiguring the system, (3) Multi-path routing scheme, (4) reliability improvement through reducing large number of network components in server I/O network, and (5) global storage/file systems support in heterogeneous multi-cluster and Grids environments. We have compared the PaScal server I/O network architecture with the Federated server I/O network architecture (FESIO). Concurrent MPI-I/O performance testing results and deployment cost comparison demonstrate that the PaScal server I/O network architecture can outperform the FESIO network architecture in many categories: cost-effectiveness, scalability, and manageability and ease of large-scale I/O network.

This research provides an in-depth analysis of the development and significance of heterogeneous computing systems, focusing particularly on their implementation in the C programming language. The study reviews historical advancements in computing systems, such as parallel processing, load balancing, and RISC architectures, which played a pivotal role in the evolution of heterogeneous systems. It highlights key contributions from renowned figures like Gene Amdahl, John L. Hennessy, and David Patterson, whose work laid the foundations for efficient parallelism and multi-processor environments. Through practical C implementations, the research demonstrates critical concepts such as task distribution, core speed-up calculations, and inter-process communication. Networking and communication technologies, essential for heterogeneous systems, are also explored through examples of TCP/IP socket programming.

Fora variety ofreasons, distributed applications often must beimplemented using exist ing conventional programming languages and operating systems. Creating new high perfor mance distributed applications without high-level support from the programming language or operating system requires thatthe mechanism of distribution be selected early in the de sign stage, reducing the flexibility and/or efficiency of the design and subsequent imple mentation. Adding distribution to existing applications can result in an inordinate amount of reengineering duetothecomplexity andheterogeneity of interapplication communication mechanisms and their interfaces. This paper describes a new architecture for high performance distributed applications and a supporting framework. This architecture applies object-oriented design and imple mentation techniques tobuild a framework forplatform-independent distributed application specification and implementation using existing programming languages and operating sys tems. It utilizes an efficient and extensible layering architecture that allows new abstract data types, new protocols, and new interprocess communication mechanisms to be addedas they become necessary. h 6.

In this article we present the PAcceptor and SConnector frameworks that facilitate rapid deployment of applications that require both concurrency and inter-process communication system services. The PAcceptor and SConnector frameworks encapsulate both threads -primitive for concurrency --and sockets -primitive for inter-process communication --. These frameworks present a single interface to these disparate but essential services and thus promote the use of these abstractions in combination with ease. These frameworks may be customized to fabricate arbitrary applications by providing appropriate hotspot definitions. The frameworks obviate the need for explicit understanding and expertise over the underlying system servicessockets and threads -as well as the intricacies involved in combining the native socket and thread level services. The PAcceptors accept incoming connect requests using socket and provide service in parallel using threads while the SConnectors permit one or more threads to share a single connection to send data over the connection. Robust infrastructures for distributed and concurrent computing have been available for well over a decade and yet significant effort is required to exploit these services. As evidenced by a recent Technical Opinion column "Parallel Computing Still Not Ready for the Mainstream", in CACM the reason is neither due to the lack of infrastructures nor due to our cognitive ability to manage parallelism and concurrency. To the contrary parallelism and concurrency are quite innate and we thrive based on our ability to solve problems concurrently. The reason for the lack of use of these powerful technologies, we posit, is due to the combinatorial explosion of the conceptual difficulty in leveraging these abstract albeit powerful system services. Simplicity and maintainability is chosen over --better performance-and overwhelming complexity. Thus, in this article we present the PAcceptor and SConnector frameworks --which encapsulate these system level abstractions, hiding many of the difficult conceptual aspects--such that these high performance services may be leveraged sans their associated conceptual barriers. Programming with threads --an abstraction for concurrency --and sockets --an abstraction for inter-process communication --is anything but simple. Both conceptually { timing errors, race conditions, synchronization } and programmatically { thread attributes, socket options, and notational nuances } programming with these services is highly distractive in nature for application developers. Combining these two abstractions is even more complex. Understandably, more often than not engineers trade performance for simplicity and choose not to use these high performance devices solely due to the complexity involved. It is in this context that frameworks become highly relevant. Frameworks mitigate the barriers and promote the use of such complex abstractions by encapsulating them, while preserving the associated semantics [See 2 for examples].

In this paper we present StarFish, a highly-available geographically-dispersed block storage system built from commodity servers running FreeBSD, which are connected by standard high-speed IP networking gear. StarFish achieves high availability by transparently replicating data over multiple storage sites. StarFish is accessed via a host-site appliance that masquerades as a host-attached storage device, hence it requires no spe- cial hardware

Real-time operating system services are required to support multimedia systems that rely heavily of the workstation processor for control of the audio and video processors and movement of audio and video data. Such services are typically not available in existing workstation operating systems. This note comments on the requirements for such services and briefly describes the YARTOS kernel; an operating system kernel that provides real-time communication and computation services.

The design of general purpose operating systems impose constraints on the way one can structure real-time applications. This paper addresses the problem of minimizing the end-to-end latency of applications that are structured as a set of cooperating (real-time) tasks. When applications are structured as a set of cooperating tasks the time required for data to progress from an input task to an output task is a function of the number of the tasks that handle the data and the deadlines of individual tasks. We present an integrated inter-process communication and scheduling scheme that can be used to minimize the end-to-end latency of multi-threaded applications. Our approach is to provide the scheduler with information on the inter-process communication interconnections between tasks and to use this information to guarantee an end-to-latency to applications that is simply a function of the timing properties of the application and not its task structure. This scheme has been implemented within the YARTOS kernel and is presently being ported to the Real-Time Mach kernel.

On-line visualization and computational steering of parallel scientific applications has been widely recognized as the key to better insight and understanding of the observed simulation. From the parallel program developer's point of view, further problems arise and need to be solved. The behavior and performance of parallel programs does not only depend on the input data but also on inter-process communication. To reflect this fact we propose a novel combination of on-line visualization, computational steering of parallel High Performance Computing applications and controlled deterministic execution. Both, the visualization and the classical part of steering is based on the VIPER tool. For the control of the communication we rely on a tool called codex, which was developed to test and control communication by the use of control patterns. Finally, VIPER and codex form a environment for tuning, steering and testing based on VIPER's extended programming model.

SystemC and Transaction Level Modeling (TLM) have become the de-facto standard for Electronic System Level (ESL) design. For the costly task of verification at ESL, simulation is the most widely used and scalable approach. Besides the Design Under Test (DUT), the TLM verification environment typically consists of stimuli generators and checkers where the latter are responsible for detecting errors. However, in case of an error, the subsequent debugging process is still very timeconsuming. In this paper, we present a scalable fault localization approach for SystemC TLM designs. The approach targets the described standard TLM verification environment and can be easily integrated into one. Our approach is inspired by software diagnosis techniques. We extend the concept of execution profiles of software programs, also known as program spectra, to handle the TLM simulation. The whole simulation consists of several runs; each run corresponds to the request-DUT-response path. During simulation our approach individually collects spectra for each run. Then, based on analyzing the differences of passed and failed runs we determine possible fault locations. We demonstrate the quality of our approach by several experiments including TLM-2.0 designs. As shown in the experiments, the fault locations are identified accurately and very fast.

The nature of product modeling systems and related application programs for design and manufacture makes it difficult to integrate them into a consistent and dynamic environment. This has been especially true for rule-based application programs. Through the use of standardized functional interfaces and UNIX interprocess communication, an environment has been developed that allows modelers and application programs to behave like objects within the integration environment. Each modeler and application (objects in the system) runs as a separate process. Each object has specific methods associated with it and also incorporates the concepts of data hiding and encapsulation. The object-oriented approach creates an environment that is service oriented vs. the traditional data-oriented approach. The software that creates and controls this environment is called the Information Services Exchange (ISX). ISX is currently being used to implement a project sponsored by Computer Aided Manufacturing-International (CAM-I) aimed at integrating a wide range of product development software. The approach developed within ISX could have a significant effect on design of diverse and large-scale product development systems.

In this Master thesis, I will introduce CommSensum, a community sensor network developed by CompNet research group. I will explain what are the needs that led to creating the platform, how is the platform until now and I will focus on the security issue. As it is a platform that is beginning its first deployment tests, security issues had been sidelined. But now, the first steps need to be done. Therefore, this thesis will analyze the various security options that exist, I will analyze which of these options are able to be adapted to the sensor network environment. Also, I will explain how the main bottleneck to provide of security to this type of platform ithe nodes own hardware limitation. I will analyze two main factors in the system to understand why there is no possibility to use HTTPS, RN171 WiFi module and mote's limitations. In addition I will compare already existing work, how other researchers design different wireless sensor network structures to give a solution. Some tricks can be done having a proxy or a intermediate router. Once immersed in the topic, I will analyze the components of CommSensum and see what security schemes I can develop. Finally, I will also provide the functions needed to implement secure connections between the nodes and the server. All of these function will run on the mote and with its hardware limitations. I will provide too, some function using RSA to use in future in a future Waspmote version or another Arduino board because in the actual version there is not enough SRAM. Finally, I presents some conclusions and future work possible to continuing implementation of the security in CommSensum platform.

, he has been in the computer field since 1950. At SRI Intemational, he directed the ERMA project that developed the first computer system for the banking industry in the 1950's and served as Executive Director of the Information Science and Engineering division from 1961 to 1968. He then served eight years as Chairman of Computer Science at the University of Washington. While at SRI he was a lecturer at Stanford, and during 1976-1977 he was a Visiting Professor at the Vrije Universiteit in Amsterdam. Dr. Noe is a member of Eta Kappa Nu, Tau Beta Pi, Sigma Xi, and the Association for Computing Machinery.

Rapid Prototyping has been proposed as a means to reduce development time and costs of real-time systems. Our approach uses a heterogeneous, tightly coupled multiprocessor system based on off-the-shelf components as target architecture for an executable prototype, which is generatedfrom the specification in an automated design process. Here, too, we aim to use existing tools and languages. But interface and communication synthesis, while being the key requirement of an automated translation of a abstract specification to a distributed system, is not yet state-of-the-art. The sensitivity of the overall performance of multiprocessor systems to overhead and latency introduced by communication on the other hand calls for an efficient interprocess communication (IPC). This paper presents concept and implementation of IPC functions which, implementing the message queue semantics of the specification language SDL, links the standard components of our multiprocessor system in an efficient manner, while at the same time providing the interface synthesis needed by the automated generation of a rapid prototype. The experiences gained when implementing a non-trivial, real-world CAN controller and monitor application on our rapid prototyping environment, are described as a first proof of concept.

Rapid Prototyping has been proposed as a means to reduce development time and costs of real-time systems. Our approach uses a heterogeneous, tightly coupled multiprocessor system based on off-the-shelf components as target architecture for an executable prototype, which is generatedfrom the specification in an automated design process. Here, too, we aim to use existing tools and languages. But interface and communication synthesis, while being the key requirement of an automated translation of a abstract specification to a distributed system, is not yet state-of-the-art. The sensitivity of the overall performance of multiprocessor systems to overhead and latency introduced by communication on the other hand calls for an efficient interprocess communication (IPC). This paper presents concept and implementation of IPC functions which, implementing the message queue semantics of the specification language SDL, links the standard components of our multiprocessor system in an efficient manner, while at the same time providing the interface synthesis needed by the automated generation of a rapid prototype. The experiences gained when implementing a non-trivial, real-world CAN controller and monitor application on our rapid prototyping environment, are described as a first proof of concept.

This paper reviews the design and operation of the VR Toolkit developed at IBM Research. Ease of use was emphasized both for the application builder and the toolkit extender. The system supports distributed processing, the building of multiuser shared environments, as well as a variety of specialized I/O devices such as gloves, 3-D position sensors, sound generation, speech recognition, and 3-D graphics displays, under an open and extensible architecture. Virtual world environments are created using a mixed object-oriented and event based paradigm for defining system behavior. Basic units, called modules, represent entities in the world such as objects, operations, functions or users. Modules communicate with each other by producing and consuming events, and are defined at a high-level using rules written in C++ that determine how events are handled. The VR Toolkit, designed to be run on one or more workstations, includes a development environment consisting of C++ class libraries for module construction, interprocess communication, device support, and hierarchical object-oriented graphics. The run-time environment includes an X Window System based control panel for dynamically constructing worlds from a collection of modules, allocating processes among hosts, editing modules, and monitoring operation, and a library of ready to use modules for various devices and common operations.

In this paper, we present a novel Adaptive Pre-task Assignment (APA) strategy for heterogeneous distributed raytracing system. The strategy has the following main features: i) the master pre-task assignment to each node/worker. The amount of sub-task size for each node is proportional to the node's performance. ii) Reduction in the inter-processes communication, nodes idle time cost overhead and load imbalance, when compared to the traditional Runtime Task Scheduling (RTS) strategies. The measured results of our proposed (APA) strategy have shown a significant improvement in speedup over RTS strategy.

Optimal utilization of cluster computing is partly dependent upon pre-emptive process migration. However, this migration involves a host of issues, one of them being the transfer of system-dependent resources. We focus on the overhead incurred by migrated processes using sockets. We then describe a solution that we devised and implemented to avoid this overhead through the use of 'migratable sockets'. Our studies show that the use of 'migratable sockets' considerably improves the execution time of a process using sockets as compared to the execution time of a process that uses standard sockets and thus bears the communication overhead.

We describe a multiprocessor system that attempts to enhance the system performance by incorporating into its architecture a number of key. operating system concepts. In particular:-the scheduling and synchronization of concurrent activities are built in at the hardware level,-the interprocess communication functions are performed in hardware, and,-a coupling between the scheduling and communication functions is provided which allows efficient implementation of parallel systems that is precluded when'the scheduling and communication functions are realized in software.

A simple, general, and well-formalized partial evaluation method for concurrent languages is proposed. In spite of many potential benefits, there are few partial evaluation techniques for concurrent languages. We choose a process calculus for the target language because it has theoretical clarity, and yet has expressive power enough to represent various high-level constructs in concurrent object-oriented languages. We realize effective optimization by allowing elimination of even nondeterministic interprocess communications. Furthermore, we prove correctness of our method with respect to barb-agreed simulation.

We summarize an implementation of a distributed sharedmemory system on a workstation cluster, in this paper, we introduce fast serial links called Serial Transparent Asynchronous First-in Firstout Link (STAFF-Link). By using these links we construct a parallel processing system based on the workstation cluster. In the workstation cluster, a distributed shared-memory mechanism is utilized for interprocess communication with software controlled cache. We evaluate the performance of the system for several applications.

Whereas emerging non-volatile memories (NVMs) are low power, dense, scalable alternatives to DRAM, the high latency and low endurance of these NVMs limit the feasibility of NVM-only memory systems. Smart hybrid memories (SHMs) that integrate NVM, DRAM, and on-module processor logic are an efficient means to bridge the latency and endurance gaps between NVM-only and DRAM-only memory systems. However, these SHMs are vulnerable to data confidentiality and integrity attacks that can be executed on the unsecure NVM, DRAM, and/or memory buses. STASH is the first comprehensive end-to-end SecuriTy Architecture for SHMs that integrates (i) counter mode encryption for data confidentiality, (ii) low overhead page-level Merkle Tree (MT) authentication for data integrity, (iii) recovery-compatible MT updates to withstand power/system failures, and (iv) page-migration-friendly security meta-data management. For security guarantees equivalent to the closest state-of-the-art security solution extensible to SHMs, STASH reduces memory overhead by 12.7×, increases system performance by 65%, and improves NVM lifetime by 2.5×.

This paper presents the Distributed InterProcess Communication System (DIPCS) as a framework for managing communication in a distributed multimedia system. Within DIPCS, connection level management is provided through a novel distributed process group model called ADP-Group communication. The ADP-Group paradigm defines a new type of group message passing, called qos-reliable. Qos-reliable semantics are appropriate to controlling real-time multimedia communication, by allowing a spectrum of performance and reliability specifications to co-exist within one group. DIPCS also provides an abstract programming model of multimedia devices, easing control of a heterogeneous multimedia system. Distributed multimedia applications can be rapidly developed using simple group operation primitives. We show how ADP-Group message delivery semantics can be directly mapped into an efficient Integrated Services Network support policy.

In this work we propose mTags, an efficient mechanism that augments microkernel interprocess messages with lightweight metadata to enable the development of new, system-wide functionality without requiring modification of the application source code. As such it is well suited for systems with a large legacy code base or third-party applications like phone and tablet applications. We explored mTags in a variety of different contexts in local and distributed system scenarios. For example, we detail use cases in areas including messaging-induced deadlocks and mode propagation. To demonstrate that mTags is technically feasible and practical, we implemented it in a commercial microkernel and executed multiple sets of standard benchmarks on two different computing architectures. The results clearly demonstrate that mTags has only negligible overhead and strong potential for many applications.

Multimedia has generated a widespread interest in real purpose operating systems. In addition to real-time support, muli n ts of data to be moved between devices and processes. "r*e M edi,' bed-at set of applications that suress consistent low-latency response efflciq-t interprmess cwti ication for large blocks of data. The Multimedia Testbed was to ft Mach3lAOpem•h System where perfomance was measured. Experiments were coniucted to conpam v•bt•A hniques for IPC and disk reads. Experience with fixed priority sch ';us-Iev e evtIqr"f and a high-resolution timer are also reported.

Studies have shown that understanding of interprocess communication patterns is an enabler to effective analysis of high performance computing (HPC) applications. In previous work, we presented an algorithm for recovering communication patterns from traces of HPC systems. The algorithm worked well on small cases but it suffered from low accuracy when applied to large (and most interesting) traces. We believe that this was due to the fact that we viewed the trace as a mere string of operations of inter-process communication. That is, we did not take into account program control flow information. In this paper, we improve the detection accuracy by using function calls to serve as a context to guide the pattern extraction process. When applied to traces generated from two HPC benchmark applications, we demonstrate that this contextual approach improves precision and recall by an average of 56% and 66% respectively over the non-contextual method.

This position paper outlines a new network architecture that is based on the fundamental principle that networking is interprocess communication (IPC). In this model, application processes (APes) communicate via an IPC facility. The IPC processes that make up this facility provide a protocol that implements an IPC mechanism, and a protocol for managing distributed IPC (routing, security and other management tasks). Our architecture is recursive in that the IPC processes can themselves be APes requesting services from lower IPC facilities. We present the repeating patterns and structures in our architecture, and show how the proposed model would cope with the challenges faced by today's Internet (and that of the future).

This paper proposes an algorithm for generating process specifications from communications service specifications described by a graph grammar. In this work, it is assumed that a communications system consists of homogeneous processes and that there is no global database. Processes that share a relationship form a global state, and a communications service defines global state transitions caused by inputs to the processes. A global state is represented by a labeled directed graph and a global state transition is described by a graph replacement rule. A process specification is regarded as a distributed algorithm whose purpose is to achieve the global state transitions described by the graph replacement rules. The communication time complexity of the generated distributed algorithm does not depend on the number of graph replacement rules.

This paper proposes an algorithm for generating process specifications from communications service specifications described by a graph grammar. In this work, it is assumed that a communications system consists of homogeneous processes and that there is no global database. Processes that share a relationship form a global state, and a communications service defines global state transitions caused by inputs to the processes. A global state is represented by a labeled directed graph and a global state transition is described by a graph replacement rule. A process specification is regarded as a distributed algorithm whose purpose is to achieve the global state transitions described by the graph replacement rules. The communication time complexity of the generated distributed algorithm does not depend on the number of graph replacement rules.

Ce travail doctoral n'aurait pu aboutir sans le soutien d'un grand nombre de personnes dont la générosité, la bonne humeur et l'intérêt manifestés à l'égard de ma recherche m'ont permis de progresser. Je voudrais remercier Anne qui a assuré le plan de formation des enseignants ayant participé à cette recherche et agrémenté ma quatrième partie de dessins permettant de mieux visualiser les propos évoqués. Merci aussi à Micheline qui m'a soutenu dans mon travail professionnel au quotidien me permettant ainsi de finaliser cette thèse de doctorat. Un merci tout particulier à Aline pour m'avoir rappelé l'usage de la virgule dans certaines parties de mes écrits. L'écriture d'un tel travail nécessite également une relecture précise et rigoureuse de manière à éviter toute coquille orthographique. C'est un travail long et fastidieux qu'Adèle a mené à bien avec une rigueur exemplaire. Qu'elle en soit remerciée bien chaleureusement. Cette recherche a nécessité un investissement financier pour la formation des enseignants. J'ai pu compter sur le soutien de la ville de Charleroi et d'une association oeuvrant dans la région de Chimay, la Wartoise. Mes remerciements les plus chaleureux leur sont adressés à tous deux. Un merci également à tous les enseignants rencontrés et qui ont parcouru un bout de chemin avec moi.

The operating system kernel of a multiprocessor system based on 16 bit microcomputers is described. The multiprocessor system constitutes a node of a local computer network dedicated to the control of continuous or discontinuous industrial processes. The kernel makes available a virtual machine where processes allocatedon dif ferent processors are executed in parallel, while processes which reside on the same processor are executed in a multitasking environment. The processes can cooperate by means of synchronization and message passing primitives; furthermore they can interact by means of short-term scheduling primitives which perform the creation, destruction, activation and termination of a process. The interprocessor communication mechanisms allow the primitives to make all the process interactions transparent to the physical allocation of the interacting processes. The system has been completely implemented in the PASCAL language, excepting only few functions of the lowest level, coded in the assembler language. The distributed kernel has been developed and tested on a conventional machine (a DEC PDP11/34 computer under RSXll-M Operating System). The processes allocated on the same processor have been implemented as a sil gle RSXll task, and interprocessor communications have been simulated by means of intertask system primitives.