Hard Real-Time

Failure of a safety-critical application on an embedded processor can lead to severe damage or even loss of life. Here we are concerned with two kinds of failure: stack overflow, which usually leads to runtime errors that are difficult to diagnose, and failure to ...

Fixed-priority scheduling with deferred preemption (FPDS) has been proposed in the literature as a viable alternative to fixed-priority pre-emptive scheduling (FPPS), that obviates the need for non-trivial resource access protocols and reduces the cost of arbitrary preemptions. This paper shows that existing worst-case response time analysis of hard real-time tasks under FPDS, arbitrary phasing and relative deadlines at most equal to periods is pessimistic and/or optimistic. The same problem also arises for fixedpriority non-pre-emptive scheduling (FPNS), being a special case of FPDS. This paper provides revised analysis, resolving the problems with the existing approaches. The analysis is based on known concepts of critical instant and busy period for FPPS. To accommodate for our scheduling model for FPDS, we need to slightly modify existing definitions of these concepts. The analysis assumes a continuous scheduling model, which is based on a partitioning of the timeline in a set of non-empty, right semi-open intervals. It is shown that the critical instant, longest busy period, and worst-case response time for a task are suprema rather than maxima for all tasks, except for the lowest priority task, i.e. that instant, period, and response time cannot be assumed. Moreover, it is shown that the analysis is not uniform for all tasks, i.e. the analysis for the lowest priority task differs from the analysis of the other tasks. To build on earlier work, the worst-case response time analysis for FPDS is expressed in terms of known worst-case analysis results for FPPS. The paper includes pessimistic variants of the analysis, which are uniform for all tasks.

In this paper we present a modification of the Dual Priority Scheduling Algorithm to work on shared memory multiprocessor systems improving the average-case schedulability. The proposal deals with global fixedpriority preemptive scheduling of periodic tasks on identical processors. The algorithm allows to schedule hard real-time periodic tasks using task migration between different processors. Using this approach we are able to schedule task sets that can not be scheduled via traditional partitioning methods. Extensive simulations show that the proposed algorithm gives higher success ratios than previous global scheduling schemes and traditional partitioning methods.

There exist certain systems which generate real-time data at high bandwidth, but do not necessarily require the long-term retention of that data in normal conditions. In some cases, the data may not actually be useful, and in others, there may be too much data to permanently retain in long-term storage whether it is useful or not. However, certain portions of the data may be identified as being vitally important from time to time, and must therefore be retained for further analysis or permanent storage without interrupting the ongoing collection of new data. We have developed a system, Mahanaxar, intended to address this problem. It provides quality of service guarantees for incoming real-time data streams and simultaneous access to already-recorded data on a best-effort basis utilizing any spare bandwidth. It has built in mechanisms for reliability and indexing, can scale upwards to meet increasing bandwidth requirements, and handles both small and large data elements equally well. We will show that a prototype version of this system provides better performance than a flat file (traditional filesystem) based version, particularly with regard to quality of service guarantees and hard real-time requirements.

In real-time task scheduling on multiprocessor systems, partitioning approach has received the attention of many researchers because of its higher least upper bound utilization of safe systems. Semi-partitioning allows some tasks to be split into subtasks and each subtask to be assigned to a different processor. Though task splitting improves the performance of systems, by counting each subtask as a separate task, it increases the effective number of tasks to be scheduled, which in turn, raises the execution overhead. This research is on semi-partitioning of tasks and assigning each partition to a separate processor to be scheduled by the well-known scheduler Rate-Monotonic (RM). Using our algorithm, we do not need to define release time for subtasks of a task to assure their nonconcurrent execution and the number of effective tasks, in turn, is reduced. It is theoretically proven that with the proposed semi-partitioning and RM scheduling algorithm, all processors may safely run their tasks according to their deadlines. Further, experimental results on 3000 randomly generated task-sets indicates that not only is utilization factor boosted, but the number of broken tasks also is decreased.

This paper considers the use of lock-free shared objects within hard r eal-time systems. As the name suggests, lock-free shared objects are distinguished by the fact that they are not locked. As such, they do not give rise to priority inversions, a key advantage over conventional, lock-based object-sharing approaches. Despite this advantage, it is not immediately apparent that lock-free shared objects can be employed if tasks must adhere to strict timing constraints. In particular, lock-free object implementations permit concurrent operations to interfere with each other, and repeated interferences can cause a given operation to take an arbitrarily long time to complete. The main contribution of this paper is to show that such interferences can be b ounded by judicious scheduling. This work pertains to periodic, hard r eal-time tasks that share l o ck-free objects on a uniprocessor. In the rst part of the paper, scheduling conditions are derived for such tasks, for both static and dynamic priority schemes. Based on these conditions, it is formally shown that lock-free object-sharing approaches can be expected to incur much less overhead than approaches based on wait-free objects or lock-based schemes. In the last part of the paper, this conclusion is validated experimentally through work involving a realtime desktop videoconferencing system.

Roll-call polling mechanisms are considered for fieldbus networks. Based on a producer/consumer communication model, two different protocols are presented, namely the standardized FIP (Factory Instrumentation Protocol) and a modified FIP protocol that we propose here. The modified protocol uses redundancy to eliminate local timers used by the FIP protocol. The two protocols are analyzed for efficiency, jitter and robustness. We compare the two protocols based on implementation and analytical results. Practical aspects concerning: clock precision; computing time; and hard real-time constraints are also discussed. The results show that: (1) the original FIP protocol is fractionally more efficient with respect to its execution time than the modified one; (2) the modifications proposed, however, reduce the jitter and improve the robustness considerably; (3) the slot time of the original FIP protocol has theoretical upper bound but the modified protocol has no such limitations.

We present an approach to bus access optimization and schedulability analysis for the synthesis of hard real-time distributed embedded systems. The communication model is based on a time-triggered protocol. We have developed an analysis for the communication delays proposing four different message scheduling policies over a time-triggered communication channel. Optimization strategies for the bus access scheme are developed, and the four approaches to message scheduling are compared using extensive experiments. Static non-preemptive scheduling of a set of processes on a multiprocessor architecture has been discussed in [4, 5]. Several approaches consider architectures consisting of a single programmable processor and an ASIC. Under such circumstances deriving a static schedule for the software component practically means the linearization of the dataflow graph [3]. Although different scheduling strategies have been adapted to accommodate distributed architectures, researchers have often ignored or very much simplified aspects concerning the communication infrastructure. One typical solution is to consider communication tasks as processes with a given execution time (depending on the amount of information transferred) and to schedule them as any other process [4, 20], without considering issues like communication protocol, bus arbitration, packaging of messages, and clock synchronization. Previous works related to communication synthesis, like [1, 2, 6, 10, 11], are dealing with lower level aspects of hardwaresoftware communication and are not addressing problems specific to distributed real-time embedded systems, based on particular communication protocols. Currently, more and more real-time systems are used in physically distributed environments and have to be implemented on distributed architectures in order to meet reliability, functional, and performance constraints. Thus, in order to guarantee that real-time requirements are fulfilled, schedulability analysis has 2. System Architecture 2.1 Hardware Architecture We consider architectures consisting of nodes connected by a broadcast communication channel. Every node consists of a TTP controller, a CPU, a RAM, a ROM and an I/O interface to sensors and actuators. A node can also have an ASIC in order to accelerate parts of its functionality. Communication between nodes is based on the TTP [7]. TTP was designed for distributed real-time applications that require predictability and reliability (e.g, drive-by-wire). It integrates all the services necessary for fault-tolerant real-time systems. The communication channel is a broadcast channel, so a message sent by a node is received by all the other nodes. The bus access scheme is time-division multiple-access (TDMA) (Figure 1). Each node N i can transmit only during a predetermined time interval, the so called TDMA slot S i. In such a slot, a node can send several messages packaged in a frame. A

This paper considers the use of lock-free shared objects within hard r eal-time systems. As the name suggests, lock-free shared objects are distinguished by the fact that they are not locked. As such, they do not give rise to priority inversions, a key advantage over conventional, lock-based object-sharing approaches. Despite this advantage, it is not immediately apparent that lock-free shared objects can be employed if tasks must adhere to strict timing constraints. In particular, lock-free object implementations permit concurrent operations to interfere with each other, and repeated interferences can cause a given operation to take an arbitrarily long time to complete. The main contribution of this paper is to show that such interferences can be b ounded by judicious scheduling. This work pertains to periodic, hard r eal-time tasks that share l o ck-free objects on a uniprocessor. In the rst part of the paper, scheduling conditions are derived for such tasks, for both static and dynamic priority schemes. Based on these conditions, it is formally shown that lock-free object-sharing approaches can be expected to incur much less overhead than approaches based on wait-free objects or lock-based schemes. In the last part of the paper, this conclusion is validated experimentally through work involving a realtime desktop videoconferencing system.

In this paper, we derive bounds on performance guarantees of online algorithms for real-time preemptive scheduling of jobs with deadlines on K machines when jobs are characterized in terms of their minimum stretch factor α (or, equivalently, their maximum execution rate r = 1/α). We consider two well known preemptive models that are of interest from practical applications: the hard real-time scheduling model in which a job must be completed if it was admitted for execution by the online scheduler, and the firm real-time scheduling model in which the scheduler is allowed not to complete a job even if it was admitted for execution by the online scheduler. In both models, the objective is to maximize the sum of execution times of the jobs that were executed to completion, preemption is allowed, and the online scheduler must immediately decide, whenever a job arrives, whether to admit it for execution or reject it. We measure the competitive ratio of any online algorithm as the ratio of the value of the objective function obtained by this algorithm to that of the best possible offline algorithm. We show that no online algorithm can have a competitive ratio greater than 1 − (1/α) + ε for hard real-time scheduling with K ≥ 1 machines and greater than 1 − (3/(4 α)) + ε for firm real-time scheduling on a single machine, where ε > 0 may be arbitrarily small, even if the algorithm is allowed to know the value of α in advance. On the other hand, we exhibit a simple online scheduler that achieves a competitive ratio of at least 1 − (1/α) in either of these models with K machines. The performance guarantee of our simple scheduler shows that it is in fact an optimal scheduler for hard real-time scheduling with K machines. We also describe an alternative scheduler for firm real-time scheduling on a single machine in which the competitive ratio does not go to zero as α approaches 1. Both of our schedulers do not know the value of α in advance.

Rapid Prototyping has been proposed as a means to reduce development time and costs of real-time systems. Our approach uses a heterogeneous, tightly coupled multiprocessor system based on off-the-shelf components as target architecture for an executable prototype, which is generatedfrom the specification in an automated design process. Here, too, we aim to use existing tools and languages. But interface and communication synthesis, while being the key requirement of an automated translation of a abstract specification to a distributed system, is not yet state-of-the-art. The sensitivity of the overall performance of multiprocessor systems to overhead and latency introduced by communication on the other hand calls for an efficient interprocess communication (IPC). This paper presents concept and implementation of IPC functions which, implementing the message queue semantics of the specification language SDL, links the standard components of our multiprocessor system in an efficient manner, while at the same time providing the interface synthesis needed by the automated generation of a rapid prototype. The experiences gained when implementing a non-trivial, real-world CAN controller and monitor application on our rapid prototyping environment, are described as a first proof of concept.

Rapid Prototyping has been proposed as a means to reduce development time and costs of real-time systems. Our approach uses a heterogeneous, tightly coupled multiprocessor system based on off-the-shelf components as target architecture for an executable prototype, which is generatedfrom the specification in an automated design process. Here, too, we aim to use existing tools and languages. But interface and communication synthesis, while being the key requirement of an automated translation of a abstract specification to a distributed system, is not yet state-of-the-art. The sensitivity of the overall performance of multiprocessor systems to overhead and latency introduced by communication on the other hand calls for an efficient interprocess communication (IPC). This paper presents concept and implementation of IPC functions which, implementing the message queue semantics of the specification language SDL, links the standard components of our multiprocessor system in an efficient manner, while at the same time providing the interface synthesis needed by the automated generation of a rapid prototype. The experiences gained when implementing a non-trivial, real-world CAN controller and monitor application on our rapid prototyping environment, are described as a first proof of concept.

Multi-core platforms represent the answer of the industry to the increasing demand for computational capabilities. From a real-time perspective, however, the inherent sharing of resources, such as memory subsystem and I/O channels, creates inter-core timing interference among critical tasks and applications deployed on different cores. As a result, modular per-core certification cannot be performed, meaning that: (1) current industrial engineering processes cannot be reused; (2) software developed and certified for single-core chips cannot be deployed on multi-core platforms as is. In this work, we propose the Single Core Equivalence (SCE) technology: a framework of OS-level techniques designed for commercial (COTS) architectures that exports a set of equivalent single-core virtual machines from a multi-core platform. This allows per-core schedulability results to be calculated in isolation and to hold when all the cores of the system are composed together. Thus, SCE allows each core of a multi-core chip to be considered as a conventional single-core chip, ultimately enabling industries to reuse existing software, schedulability analysis methodologies and engineering processes.

ITER Plant Systems I&C will be connected to CODAC System via Plant System Host (PSH) and High Performance Networks (HPN). Some functions of CODAC require deterministic, hard real-time communication and synchronization between distributed nodes. These requirements are addressed by the CODAC High Performance Networks. The CODAC network infrastructure is being defined including space allocation for backbone cable termination as well as housing network equipments in different ITER plant buildings, cable trenches, network topology and backbone. The ITER building design is in final stage so the activities in this direction are quite well in advance. Many prototyping and market survey activities leading to technology decisions for High Performance Networks (HPN) have been launched in late 2008. These activities are evaluating different commercial off-the-shelf (COTS) technologies as well as technologies being used in existing fusion and non-fusion experiments. In this paper we provide the current status of activities which are ongoing to define CODAC network infrastructure as well as a report on technology decisions. Finally we provide a plan and roadmap to complete this task of defining CODAC networks and network infrastructure.

Many tasks in safety-critical embedded systems have hard real-time characteristics. AbsInt's worst-case execution time analyzer aiT can estimate precise and safe upper bounds for the WCETs of program tasks, thus providing the basic input for verifying the real-time behavior of embedded applications.

We propose two novel heuristic search techniques to address the problem of scheduling tasks under hard timing constraints on a single processor architecture. The underlying problem is NP-hard in the strong sense and it is a fundamental challenge in feedback-control theory and automated cybernetics. The proposed techniques are a learning-based approaches and they take much less memory space. A partial feasible schedule is maintained and extended over a repeated problem solving trials, previously assigned priorities are refined according to the gained information about the problem to lead the convergence to a complete feasible schedule if one exists. First, we present the learning in hard-real-time with single learning (LHRTS-SL) algorithm where a single learning function is utilized, then we discuss its drawback and we propose the LHRTS with double learning algorithm in which a second learning function is integrated to cope up with LHRTS-SL drawback. Experimental results show the efficiency of the proposed techniques in terms of success ratio when used to schedule randomly generated problem instances.

This essay is to point out some of the basic differences between conventional and real-time applications of AI and to provoke discussion on whether or not a new paradigm would facilitate better understanding of these differences. Some of the listed differences are illustrated by examples from references. An attempt has been made to project existing AI methods onto the deduction-induction axis so as to find an analogy with human behaviour under hard real-time constraints, e.g. reflexes. The conclusion is that the developers of real-time AI methods might benefit by using a "reflex based" paradigm. Kevwords. Reasoning under hard real-time constraints; deduction and induction based approaches; reflex baaed paradigm of reasoning

This paper presents the PRIDE research project, developed by Intecs and co-funded by the Italian Space Agency. The project aims at providing an integrated software development environment for dependable systems based on UML, which integrates design activities with selected methods for formal verification and validation (V&V) and quantitative dependability attributes assessment, supported by appropriate tools. The PRIDE environment is built as an extension of the already existing environment for the modeling of Hard Real Time systems, HRT-UML, based on the Unified Modeling Language (UML) notation. The outcome is an advanced and integrated methodological solution for the design of complex embedded real-time systems and for their evaluation and verification, according to rigorous techniques based on formal theories, such as formal verification, model based dependability evaluation and schedulability analysis.

In this report we study hard real-time systems composed of dependent strictly periodic preemptive tasks in the monoprocessor case. Although preemptive scheduling algorithms are able to successfully schedule some systems that cannot be scheduled by any non preemptive scheduling algorithm, the cost of preemption may not be negligible. Therefore, its exact cost has to be explicitly considered in the schedulability conditions in order to avoid wasting resources and provide safety in terms of guaranteeing the right behavior of the system at run-time. Because we are interested in hard real-time systems with precedence and strict periodicity constraints where it is mandatory to satisfy these constraints, we have already shown in a previous work how to tackle this problem for systems composed of harmonic tasks. Two main contributions are presented in this report. First, we generalize our previous results to the case of systems with periods that are not necessarily harmonic. Second, we provide a necessary and sufficient schedulability condition which takes into account the exact number of preemptions for a system with such constraints when no idle time is allowed.

A challenging research issue of analyzing a real-time system is to model the tasks composing the system and the resource provided to the system. In this paper, we propose a probabilistic component-based model which abstracts in the interfaces both the functional and non-functional requirements of such systems. This approach allows designers to unify in the same framework probabilistic scheduling techniques and compositional guarantees that go from soft to hard real-time. We provide sufficient schedulability tests for task systems using such framework when the scheduler is either preemptive Fixed-Priority or Earliest Deadline First.

Algorithms based on semi-partitioned scheduling have been proposed as a viable alternative between the two extreme ones based on global and partitioned scheduling. In particular, allowing migration to occur only for few tasks which cannot be assigned to any individual processor, while most tasks are assigned to specific processors, considerably reduces the runtime overhead compared to global scheduling on the one hand, and improve both the schedulability and the system utilization factor compared to partitioned scheduling on the other hand. In this paper, we address the preemptive scheduling problem of hard real-time systems composed of sporadic constrained-deadline tasks upon identical multiprocessor platforms. We propose a new algorithm and a scheduling paradigm based on the concept of semi-partitioned scheduling with restricted migrations in which jobs are not allowed to migrate, but two subsequent jobs of a task can be assigned to different processors by following a periodic strategy.

This paper is a synthesis of different works [12, 9, 8, 13]. Problems addressed in this paper consist in assigning periodic tasks to distributed processors in the context of fixed priority preemptive scheduling. A cooperative technique using an accurate management of constraint programming is presented to solve these problems. The approach breaks down a problem into two subproblems: allocation and schedulability. Allocation problem is tackled with dynamic constraint programming whereas schedulability is analyzed with classical real-time techniques. Decomposition is used as a way of learning when the allocation subproblem yields a valid solution while the schedulability analysis of the allocation does not. The rationale of this approach is to learn from the failures of the schedulability analysis to reduce the search space. Additionally, different search strategies are proposed to increase efficiency of the resolution.

In this 25th year anniversary paper for the IEEE Real Time Systems Symposium, we review the key results in real-time scheduling theory and the historical events that led to the establishment of the current realtime computing infrastructure. We conclude this paper by looking at the challenges ahead of us.

Mobile robots are physical agents that move and interact continuously while embedded in a dynamic environment. Communications can be one of the most difficult parts of building robot architecture because of the increasing complexity of sensor and actuator hardware, and the interaction between intelligent features and real-time constraints. Currently, hybrid architectures offer the most widespread solutions for controlling intelligent mobile robots. This paper deals with the communications framework necessary to design and implement these architectures. The main goal of this work 1 is to design a modular and portable architecture that allows the development of robot control systems. A multi-level and distributed architecture based on the reactive/deliberative paradigm is presented. Its main components are mobile software agents that interact through a distributed blackboard communications framework. These agents can be run on onboard processors, as well as on fixed workstations depending on their real-time restrictions. The presented control architecture has been tested in a real mobile robot and results demonstrate the effectiveness of distributing software agents to guarantee hard real-time execution.

This paper addresses a control allocation method in order to compensate for the effect of thrusters' dead-zones, on the actuation system of an underwater vehicle. This solution concurrently considers dead-zone effect and actuation limitation, in order to increase system reactivity. Moreover the impact on energy consumption is also considered. Experimental results are given to demonstrate the effectiveness and correctness of the proposed method.

Fault tolerance has become more and more important in the development of autonomous systems with the aim to help the system to recover its normal activities even when some failures happen. Yet, one of the concerns is how to analyze the reliability of a fault tolerance mechanism with regards to the collaboration of multiple agents to complete a complicated task. To do so, an approach of fault tolerance analysis with the colored time Petri net framework is proposed in this work, where a task can be represented by a tree of different concurrent and dependent subtasks to assign to agents. Different subtasks and agents are modeled by color tokens in Petri network. The time values are added to evaluate the processing performance of the whole system with respect to its ability to solve a task with fault tolerance ability. The colored time Petri nets are then tested with simulation of centralized and distributed systems. Finally the experiments are performed to show the feasibility of the proposed approach. From the basics of this study, a generalized framework in the future can be developed to address the fault tolerance analysis for a set of agents working with a sophisticated plan to achieve a common target.

With the end of Moore's law and the breakdown of Dennard scaling, multicore processors are the standard way to continue improving performance while reducing Size, Weight and Power (SWaP). However, this performance is typically achieved at the cost of repeatability and predictability. Precision-timed (PRET) architectures have been shown to deliver high performance without sacrificing predictability. In this paper, we introduce InterPRET: an architecture consisting of FlexPRET cores interconnected via the S4NOC network-on-chip. Both the processor cores and the network-onchip are time-predictable, yielding an end-to-end time-predictable architecture suitable for real-time systems. CCS CONCEPTS • Computer systems organization → Multicore architectures; Real-time system architecture.

Several years before the popularization of the Internet, Mark Weiser proposed the concept of ubiquitous computing with the purpose of enhancing the use of computers by making many computers available throughout the physical environment, but making them effectively invisible to the user. Nowadays, such idea affects all areas of computing science, including both hardware and software. In this paper, a formal model for ubiquitous systems based on Petri nets is introduced and motivated with examples and applications. This simple model allows the definition of two-level ubiquitous systems, composed of a collection of processor nets providing services, and a collection of process nets requesting those services. The modeled systems abstract from middleware details, such as service discovery protocols, and security infrastructures, such as PKI's or trust policies, but not from mobility or component compatibility.

On-chip temperatures continue to rise, in spite of design efforts towards more efficient cooling and novel low-power technologies. Run-time thermal management techniques, such as speed scaling and system throttling, constitute a standard component in today's processors. One such technique is the feedback control of the processing speed based on the on-chip temperature. If suitably designed, such a controller can ensure that the temperature of the processor does not exceed a given bound, independent of the application. Such isolation of needs is encouraging. However, from the application's stand-point, such a processor must provide performance guarantees; in particular, the guarantee that real-time jobs do not have worst-case delays larger than their relative deadlines. For applications which exhibit variability, such as bursty arrival patterns, computing such guarantees is not apparent. As key enablers in such a computation, for the specific setting of First-Come-First-Serve...

We present a method for providing hard r eal-time guarantees for tra c through an Asynchronous Transfer Mode ATM network. Guaranteed delivery also implies that we have to guarantee that no cells are lost due to over-full bu ers in the network. By using priority queues in the output bu ers we allow urgent messages short end-to-end delays, while still guaranteeing end-to-end delays for low-priority messages. We can determine a priori if message deadlines will be met by calculating maximum end-to-end delays and bu er-needs. Analysis is based on CPU schedulability analysis, which means that it provides a framework for analysing an entire system, including both CPU and network scheduling.

CiteSeerX - Document Details (Isaac Councill, Lee Giles): This work presents an implementation of a digital PID (Proportional Integral Differential) controller in a PC machine running RTAI. PID controllers are well known and have a wide range of applications in the control of analog ...

The major research in the resource management literature focuses primarily on two directions: 1) specification languages for formulating resource requests and 2) constraint problems modelling allocation and scheduling. Both directions assume the knowledge of the underlying platform architecture and the dependencies it induces on the usage of the various resources. In this report we bridge this gap, by introducing Constraint-Flow Nets (cfNets). A cfNet is defined by a set of resources and dependencies between them, each dependency having an associated constraint. The model is inspired by Petri Nets, with resources corresponding to places and dependencies—to transitions. Given an architecture of dependent resources, an initial resource request is propagated through the dependencies. The generated constraints are then conjuncted into the global allocation constraint. We study the notion of conflicts in cfNets and prove that for conflict-free cfNets the global allocation constraint can ...

Generally, multiprocessor real-time scheduling algorithm fall into two basic approaches, partitioned and global. The hybrid solution that we proposed applies the partitioned scheduling approach to the task set until all processors have been filled. The remaining tasks are then scheduled using the global scheduling approach. The idea of a hybrid scheduling approach to ameliorate limitations of partitioned and global approaches. Studies have shown that most prior research on hybrid multiprocessor real-time scheduling has been confined to hard and soft real-time tasks. In fact, the implementation of hybrid approach and the performance of such algorithms in comparison to partitioned and global approaches have not been fully answered by previous studies. This paper performs experimental evaluation of our proposed hybrid multiprocessor scheduling approach, R-BOUND-MP-NFRNS and RM-US (m/3m-2) with multiprocessor response time test, with one of the best scheduling approach from partitioned ...

In this paper, we propose a state-based, modular model for automation systems enabling the calculation and optimization of switching strategies for energy-efficient operation. This concept is based on the model of networked (priced) timed automata that we call energy system model. It comprises structural, temporal and energetic information of automation subsystems' behavior providing a basis for automated analysis and calculation of feasible, energy-optimal switching strategies for the complete automation system. The presented real-world automation system enables proof-of-concept and allows discussing the arising, domain-specific complexity of the temporal and energetic analysis. By means of the energy system model, we provide a basis for calculating energy-optimal operation of modular automation systems and support the comparison of alternative, energetic switching strategies of subsystems. For this purpose, a symbolic reachability analysis complemented by solving a constrained optimization problem is applied in this approach.

Beagleboard can be used as rapid prototyping and product development platform, however the full computational and networking capability of its ARM processor AM3358 and programmable real time unit are not fully utilized due to the bandwidth limitations of the networking device used in the board. This paper presents the network performance evaluation of the board and compares it with the real time requirements of a networked commanding and data acquisition system. The feasibility of using this board for real time applications with a response latency of < 20 ms is studied. The observations from the timing analysis indicate that the timing constraints need to be implemented on the system for getting realtime performance.

This paper presents a Fast Forward MAC layer designed for hard real-time applications in wireless sensor networks. This protocol is an enhancement to the IEEE 802.15.4 standard MAC layer proposed for Low-Rate Personal Area Network. The energy conservation mechanism proposed by the current standard is quite efficient and very flexible. This flexibility comes from the ability to configure different duty cycles to meet specific application's requirements. However, this mechanism has a considerable impact on the end-to-end delay. Our approach resolves the energy delay trade-off by avoiding the storage of the real-time data in the coordinator during sleep time. A new superframe structure is adopted and a deterministic reception scheduling is used. All the simulations were done using the network simulator 2 'NS-2'. The simulations outcomes show that this new proposed protocol performs better than the current standard and reduces considerably the end-to-end delay even in low duty cycle networks. Our protocol can also provides a delay bound for all network configurations which allows a better choice of the duty cycle for the required delay.

An allocation of resources to a virtual machine specifies the maximum amount of each individual element of each resource type that will be utilized, as well as the aggregate amount of each resource of each type. An allocation is thus represented by two vectors, a maximum elementary allocation vector and an aggregate allocation vector. There are more general types of resource allocation problems than those we consider here. In this paper, we present an approach for improving the deadlock detection algorithm, to schedule the policies of resource supply for resource allocation on heterogeneous. Deadlock detection algorithm using two way has run time complexity of O(min(m 1/2 ,n 2/3), where m is the number of resources and n is the number of processes. We propose the algorithm for allocating multiple resources to competing services running in virtual machines on a heterogeneous distributed platform. The experiments also compare the performance of the proposed approach with other related work.

A new token-passing algorithm called AR-TP for avoiding the nondeterminism of some networking technologies is presented. This protocol-based on RT-EP, a research protocol also based on transmission control techniquesallows the schedulability analysis of the network, enabling the use of standard Ethernet hardware for Hard Real-Time behavior while adding congestion management. It is specially designed for High-Integrity Distributed Hard Real-Time Systems, being fully written in Ada and taking advantage of some of the new Ada 2005 features, like the Ravenscar Profile. Work supported by MEC, project TRECOM (TIC2002-04123).

An allocation of resources to a virtual machine specifies the maximum amount of each individual element of each resource type that will be utilized, as well as the aggregate amount of each resource of each type. An allocation is thus represented by two vectors, a maximum elementary allocation vector and an aggregate allocation vector. There are more general types of resource allocation problems than those we consider here. In this paper, we present an approach for improving the deadlock detection algorithm, to schedule the policies of resource supply for resource allocation on heterogeneous. Deadlock detection algorithm using two way has run time complexity of O(min(m 1/2 ,n 2/3), where m is the number of resources and n is the number of processes. We propose the algorithm for allocating multiple resources to competing services running in virtual machines on a heterogeneous distributed platform. The experiments also compare the performance of the proposed approach with other related work.

In most real-time applications, deadlines are artifices that need to be enforced to meet different performance requirements. For example, in periodic task sets, jitter requirements can be met by assigning suitable relative deadlines and guaranteeing the feasibility of the schedule. This paper presents a method (called minD) for calculating the minimum EDF-feasible deadline of a real-time task. More precisely, given a set of periodic tasks with hard real-time requirements, which is feasible under EDF, the proposed algorithm allows computing the shortest deadline that can be assigned to an arbitrary task in the set, or to a new incoming task (periodic or aperiodic), still preserving the EDF feasibility of the new task set. The algorithm has a pseudo polynomial complexity and handles arbitrary relative deadlines, which can be less than, equal to, or greater than periods.

Offline (cyclic executive) and online preemptive, priority-based scheduling are not exclusive options but rather complementary techniques that can be combined to improve analytically verifiable schedulability. Selective offline scheduling of periodic tasks improves online ...

In real-time systems, time is usually so critical that other parameters such as energy consumption are often not even considered. However, optimizing the worst energy consumption case can be a key factor in systems with severe power-supply limitations. In this paper we study several memory architectures using combined time and energy optimization models for real-time multitasking systems. Each task is modeled using Lock-MS, a method to optimize the WCET of a task, with an added set of constraints to model in the same way the WCEC (worst case energy consumption). Our tested hardware components focus on instruction fetching, including a lockable cache, a line buffer and a sequential prefetch buffer. We test a variety of instruction fetch alternatives optimizing time and energy consumption. Our results show that the accuracy of the estimation of the number of context switches in the worst case may affect very much the resulting WCEC (up to 8 times in our experiments) and that optimizing the WCEC may provide similar execution times than optimizing the WCET, with up to 5 times less energy consumption. Additionally optimization functions combining WCET and WCEC with different weights show very interesting WCET-WCEC trade-offs. This confirms that methodologies testing such optimizations at design time could be very helpful to provide a precise system setup .

In the last years industrial control systems have increased their complexity, using a great variety of hardware and software elements of all kinds. In larger systems a big number of different protocols, communication networks and architectures can be found. System components are not centralized but distributed over the plant and they communicate with each other through several channels. Industrial control systems are usually organized in layers, and information used within/among them needs to be integrated. The general trend is to develop heterogeneous and distributed control systems, where system integration is a hard issue. CORBA is an open standard that provides a flexible middleware capable of integrating complex applications in heterogeneous environments, and could be a good choice when developing a control system. Nevertheless, CORBA has some limitations regarding to hard real-time applications, so it is only suitable for developing soft real-time systems. This paper describes the Process Control Testbed (PCT) of the IST Hard Real-time CORBA project (HRTC), which has been used to analyze and evaluate CORBA advantages and disadvantages in distributed real-time control systems development. The PCT system has been designed and implemented using CORBA and RTCORBA. A new version is being implemented using CCM Technology in the IST COMPARE project.

Hard real-time embedded systems have stringent timing constraints that must be met in order to ensure the correct functioning of the system. In many cases, these systems are composed of several CPU-bound tasks, which may need to rely on multiple processors, since just a single processor may not allow meeting all timing constraints. In order to deal with stringent constraints, specialized operating system kernels are often adopted in real-time embedded systems. However, the operating system usage may introduce significant overheads in execution time as well as in memory requirement. Software synthesis is an alternative approach to operating systems usage, since it can generate tailored code that satisfy: (i) functional, performance, and resource constraints; and (ii) other features such as scheduling, resource management, communication and synchronization. In this paper, a software synthesis approach based on a formalism, namely, time Petri nets, is presented in order to generate pre...

The objective of this paper is to introduce the impact of faulty links on Quality of Service in Network-on-Chip (NoC) under different traffic pattern. NoC paradigm has made it possible to concurrently run multiple applications on IP-core based System on Chip. It is therefore necessary to predict the multi-processor systems-on-chip communication, which is a critical issue and needs to be addressed by the right mix of soft and hard real-time guarantees. To meet this requirement state of the art packet switched NoC provide different levels of quality of service (QoS) such as best effort (BE) and guaranteed throughput (GT). This paper presents a novel scheme which compares and evaluates the performance of guaranteed throughput and best effort traffic in Network-on-Chip under different synthetic traffic generators and highlights its dependence in terms of latency on the type of traffic patterns and number of link failures for mesh topology. It also explores the effect of robustness of a particular traffic pattern in terms of fault tolerance (variation in average latency as the number of link failures increases) for planar adapter routing function on latency of GT and BE traffic class for mesh topology.

The simple notion of soft real-time processing has fractured into a spectrum of diverse soft real-time types with a variety of different resource and time constraints. Schedulers have been developed for each of these types, but these are essentially point solutions in the space of soft real-time and no single scheduler has previously been offered that can simultaneously manage all types. More generally, no detailed unified definition of soft real-time has been provided that includes all types of soft real-time processing. We present a complete real-time taxonomy covering the spectrum of processes from best-effort to hard real-time. The taxonomy divides processes into nine classes based on their resource and timeliness requirements and includes four soft real-time classes, each of which captures a group of soft real-time applications with similar characteristics. We exploit the different features of each of the soft realtime classes to integrate all of them into a single scheduler together with hard real-time and best-effort processes and present results showing their performance.

Safety-critical automotive systems must fulfill hard real-time constraints to guarantee their reliability and safety requirements. In the context of network-based electronics systems, high-level timing requirements have to be carefully mastered and traced throughout the whole development process. In this paper, we outline the management of scheduling-specific timing information by the application of a steerby-wire design example. We apply the principles of the AUTOSARcompliant Timing Augmented Description Language (TADL) following the methodology introduced by the TIMMO project[2]. Focus of the example will be the identification of end-to-end timing constraints and their refinement by means of stimuli-response event chains.