Esta tese de doutorado apresenta, inicialmente, uma revisao sobre acopladores para power line communication (PLC), utilizados para acoplar o sinal dos transceptores PLC a rede de energia eletrica. As questoes predominantes para o projeto... more
This paper presents a generic architecture for programmable multi-modulus dividers (MMD) for lowpower and high-speed frequency synthesis applications. The proposed architecture uses cascaded divide by 2/3 cells in a ripple fashion with... more
This paper describes a 9-bit 6.2-GHz low power quadrature direct digital synthesizer (DDS) implemented in a 0.18-m SiGe BiCMOS technology. With a 9-bit pipeline accumulator and two 8-bit sine-weighted current steering DACs, this DDS is... more
Two low-power sine-output Direct Digital Frequency Synthesizers have been fabricated in 0.18 pm CMOS, tested and characterized. The first IC has a 16-bit phase accumulator and it generates a single phase sinusoidal digital sequence with... more
Dynamic voltage and frequency scaling (DVFS) has been studied for well over a decade. The state-of-the-art DVFS technologies and architectures are advanced enough such that they are employed in most commercial systems today. Nevertheless,... more
Clock multiplication is not possible with delay locked loops. However, ever increasing requirements for clock multiplication in analog integrated circuits has lead to the research in several avenues including ring oscillator and LC... more
This paper describes the design of a 3-10GHz frequency synthesizer for Multi-band OFDM Ultra-wideband (UWB) transceiver in the 90nm CMOS technology. The frequency synthesizer operates in the band group 1, group 3, group 4, and group 5... more
Richards immitance is a positive real function expressed in terms of the Richards variable where is the classical complex frequency. A Richards immittance can be synthesized as a lossless two port terminated in a resistance as in... more
In this letter, the synthesis of a three-band patch antenna working in E 5-L 1 Galileo and W i − M ax frequency bands is described. The geometry of the antenna is defined by performing a Koch-like erosion in a classical rectangular patch... more
This paper describes several phase noise suppression techniques for X-band (8-12 GHz) frequency synthesizer design in 65 nm CMOS technologies. A low noise voltage generator for varactor DC biasing is proposed to minimize its contribution... more
In this work we study a particular filter synthesis problem in order to minimize the reflection coefficient of the global system consisting of filter and antenna. The matching problem is formulated as an optimization problem involving the... more
This paper reviews the state of art of a polyphase complex filter for RF front-end low-IF transceivers applications. We then propose a multi-stage polyphase filter design to generate a quadrature I/Q signal to achieve a wideband precision... more
In the optical communication in a backbone infra-structure, flexibility means, for example, programmable bitrates requiring a PLL with robust operation over a wide range of frequency range. A wide range PLL could be used by different... more
This paper reports on an ultra-wideband (UWB) Schottky diode based balanced envelope detector for the L-, S-, C-and X-bands. The proposed circuit consists of a balun that splits the input signal into two 180º out of phase signals, a... more
The purpose of this work is to design a MSK modulator capable to work at a high data modulation. To achieve a low simulation runtime, the modulator is described in VHDL-AMS hardware description language. It is optimized by applying the... more
communication systems. The system is tested using Digital Storage Oscilloscope (DSO) (Model: Tektronix TDS 1012B; 1GS/Sec). We also simulate the system using Circuit Maker's Berkeley SPICE3f5/XSpice-based simulator. In this paper we are... more
In the emerging growth of digital systems, the role of developing self-repairing circuits are demandable. Error tolerance is highly important for such automated platforms to perform well. The heart of any digital system rely on the clock... more
This paper presents a modified high speed CMOS dynamic phase frequency detector (PFD) for high frequency phase-locked loop (PLL). Design miniaturizations in downscaling CMOS process lead to circuit malfunction due to intrinsic effects and... more
A 32-bit read-only memory (ROM)-based direct digital frequency synthesizer with a maximum operating frequency of 2 GHz is presented. The proposed ROMbased design is capable of increasing the operation speed of traditional ROM-based DDFS... more
In past 50 years, X-ray computed tomography (CT) has been developed to a relatively mature non-destructive evaluation (NDE) technology widely used in both medical diagnostics and industrial inspections. Historically, major improvements in... more
This paper is focused on the design and analysis of a fully on-chip frequency comparator (FC) implemented in 65 nm CMOS technology. The proposed FC employs a digital pre-processing stage followed by a rail-to-rail input and output (RRIO)... more
This paper presents a design exploration, at both system and circuit levels, of integrated transceivers for the upcoming fifth generation (5G) of wireless communications. First, a system level model for 5G communications is carried out to... more
A switchable differential voltage-controlled oscillator (VCO) has been fabricated in 65nm CMOS. It is a dual frequency VCO whose oscillation frequencies can be changed from 40GHz (VCO1) to 80GHz (VCO2). The tuning range for VCO1 is 1GHz... more
This paper presents the design of two high efficiency fundamental voltage controlled oscillators (VCO) for sub-THz applications. The design optimizes the transistor for voltage gain, swing and PAE at the operating frequency to achieve 21%... more
In this study, an efficient and practical approach is proposed to increase the bandwidth of narrow-band antennas by designing lossless impedance matching network with the simplified real frequency technique. Our algorithm does not require... more
The improved design procedure and experimental results for a practical helical resonator filter to be used at the output of a low power UHF land mobile transmitter are described. The adequate attenuation at more than three times the... more
A 5-GHz transceiver comprising the RF and analog circuits of an IEEE 802.11a-compliant WLAN has been integrated in a 0.25-m CMOS technology. The IC has 22-dBm maximum transmitted power, 8-dB overall receive-chain noise figure, and... more
This paper presents a low power 2.4-GHz fully integrated 1 MHz resolution IEEE 802.15.4 frequency synthesizer designed using 0.18um CMOS technology. An integer-N fully programmable divider employs a novel Truesingle-phase-clock (TSPC)... more
This paper investigates the impact of clock jitter induced by substrate noise on the performance of the oversampling ∆Σ modulators. First, a new stochastic model for substrate noise is proposed. This model is then utilized to study the... more
This paper presents a CMOS transceiver IC for a single-antenna frequency-modulated continuous wave (FMCW) radar. Since transmitter (Tx) leakage is critical in a single antenna radar with CMOS technology, a comprehensive leakage canceling... more
The purpose of this work is to design a MSK modulator capable to work at a high data modulation. To achieve a low simulation runtime, the modulator is described in VHDL-AMS hardware description language. It is optimized by applying the... more
![of the PA outputs. During transmit mode, a reflective switch at the input to the LNA steers the transmit signal to the antenna and protects the LNA from the large voltages associated with 100 mW to | W operation (when using the optional external 1 W PA IC). During receive, the transmitter outputs become reflective terminations so that the majority of the receive signal power is routed to the LNA, minimizing noise figure. These reflective terminations are represented by the open-circuit switches shown in Figure 4, although the actual implementations employ parallel-resonant tanks which are combined with impedance-matching circuits. Details of the resonant switch design can be found in reference [6]. Figure 4. Transceiver RFIC block diagram A. Receive-mode Operation](https://figures.academia-assets.com/109756629/figure_004.jpg)
The new Fractional-N synthesizer architecture will be presented. The synthesizer achieves low fractional spurs and quantization noise, which relaxes the trade-off between phase locked loop bandwidth and phase noise. Proposed architecture... more
This article presents a digital-intensive transmitter (TX) architecture for ultralow-power (ULP) wireless communication telemetry applications. A Type-I correction loop is proposed to adjust the frequency of the voltage-controlled... more
This paper presents an integrated ultra-low-power (ULP) wireless sensor system-on-chip (SoC) that can be used for voltage sensing in both Internet of Things applications and bio-potential monitoring. In order to increase the energy... more
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This study focuses on the structural design analysis of a cura baglama, a traditional Turkish string instrument that does not have in place a regulated set of manufacturing standards to follow. The aim therefore is to introduce a... more
An integral-path self-calibration scheme is introduced as part of a 20.1 GHz to 26.7 GHz low-noise PLL in 32 nm CMOS SOI. A dual-loop architecture in combination with an integral path measurement and correction scheme desensitizes the... more
![Fig. 16. Measured phase noise in a single frequency band. (a) Before enabling the calibration engine. (b) After enabling it. tone with their own internal PLLs. Such non-idealities must be accounted for if the PLL’s transfer function is to be accurately measured. similar to that described in [7] was used. First the reference clock is phase modulated at a fixed offset frequency. This intro- d ot £00 Cc uces a tone in the output spectrum of the PLL. The magnitude f this tone is measured using a spectrum analyzer, and the ratio f the magnitude of the output tone to the reference clock’s mod- ation index can be used to calculate the magnitude of PLL’s hase transfer function at a given offset frequency. Next, the ex- eriment is repeated at several modulation frequencies and the results are stitched together to estimate the PLL’s small signal osed loop transfer function. This experiment requires careful calibration of the amplitude of the modulation tone; we have found that several commercially available clock generators with p rogrammable phase modulation features filter the modulation The PLL’s loop transfer function, shown in Fig. 15, and in-band phase noise, shown in Fig. 16, were measured at 9 different frequencies, equally spaced from fastest to slowest in a single coarse tuning band. On the left side of these figures, the measurements without self-calibration are presented, showing significant variation in both phase noise and transfer function. On the right side of these figures are the transfer functions and phase noise measurements after self-calibration. As can be seen, a dramatic reduction in the variation of both loop transfer function and in-band phase noise is observed. In a second test](https://figures.academia-assets.com/108123306/figure_017.jpg)
![where Iopi_noise; Icpp_noise are the contributions from the inte- gral and proportional path charge pumps, J;, /,,, are the integral and proportional currents and Ky<op, Kycoi are the proportional path and integral path VCO gains. If we compare the noise con- tribution from the integral path charge pump current (the first term in (4)) to the charge pump noise in a single path PLL (3), we see that the contribution is the same up to the open loop zero of the PLL. However, for frequencies above the open loop zero, w,, the phase noise contribution is reduced by a factor of \(s + w,)/w,]|, as illustrated in Fig. 3. This characteristic miti- gates the problem of requiring an increase in capacitor area to reduce charge pump noise, at least above the first zero of the PLL. This advantage can be understood intuitively as follows: the noise from the integral path charge pump is converted to a voltage by the impedance at its output. In a dual path PLL, the integral path filter’s impedance is just a capacitor, as shown in Fig. 3(b), in contrast to a resistor in series with a capacitor in a single path PLL, in Fig. 3(a). Therefore, the voltage on the inte- gral path control voltage is less than that the same charge pump would produce in a single path PLL, resulting in lower noise at the PLL output. where K,¢ is the VCO gain in Hz/V, R, is the proportional path resistance, C; is the integrating capacitor, I, is the charge pump current and N is the division ratio. As s — 0, (3) reduces to (1), in agreement with [10]. In a dual path PLL, there are two charge pumps with two noise currents: one from the pro- portional charge pump [cpp noise and one in the integral path, Ipi_noise- It is straightforward to show that the phase noise con- tribution in a type II dual path PLL from the charge pumps is given by](https://figures.academia-assets.com/108123306/figure_003.jpg)
![Fig. 10. Overview of time till crossover measurement. (a) Circuits used to add phase step and count time until crossover. (b) The phase step is added by tem- porarily changing the divider’s count value from N1 to N2. The additional circuitry required to implement this scheme is of a digital nature, resulting in a minimal area penalty. In addition, the method measures the PLL’s small signal gain terms around its phase locked state, which means that it accounts for the small signal gain variation of non-linear components. The scheme works as follows: A phase step is added to the PLL by tem- porarily incrementing or decrementing the feedback divider’s count value, as illustrated in Fig. 10. A bang-bang phase de- tector, placed in parallel with the PLL’s phase detector, measures the time (in reference cycles) for the phase of the PLL to cross zero in response to the introduced phase step. This time-until- cross-over measurement, in conjunction with an over-shoot de- tector is used to calibrate the PLL’s transfer function. As dis- cussed in Section I, however, the PLL in the work described here features a limited frequency range on the proportional path, making the scheme proposed in [7] impractical.](https://figures.academia-assets.com/108123306/figure_011.jpg)
With the shift from traditional analog circuit designs to an all-digital intensive approach, the all-digital Phase-locked loops (ADPLLs) have become more attractive in digital communication systems. Digitally controlled oscillators (DCO)... more
This paper presents a 0.13 µm CMOS frequency divider for I/Q generation. To achieve a wide locking range, a novel topology based on a two stages injection-locking ring oscillator is adopted. This architecture can reach a larger input... more
This paper presents a low power divide-by-three injection locked frequency divider (ILFD) for the V-band implemented in 65nm CMOS technology. The divider achieves a locking range of 5.5% by using the proposed harmonic-boosting technique.... more
This paper presents 64-quadrature amplitude modulation (QAM) 60-GHz CMOS transceivers with four-channel bonding capability, which can be categorized into a one-stream transceiver and a two-stream frequency-interleaved (FI) transceiver.... more
This paper presents a 60-GHz CMOS transceiver targeting the IEEE 802.11ay standard. A calibration block for local oscillator feedthrough (LOFT) and I/Q imbalance featuring high accuracy and low power consumption is integrated with the... more
During the present paper, a PLL-based frequency synthesizer for WiMAX application is designed and simulated via MATLAB and ADS2008 using a 0.13umCMOS technology. Synthesizer with fractional-N structure is utilized to achieve high... more