FPGA implementation Research Papers

FPGA Design Methodology for Industrial Control Systems—A Review

2000, IEEE Transactions on Industrial Electronics

This paper reviews the state of the art of fieldprogrammable gate array (FPGA) design methodologies with a focus on industrial control system applications. This paper starts with an overview of FPGA technology development, followed by a... more

Fig. 1. Generic architecture of an FPGA. technology [6], [7], which is by far the most widespread [47]. However, the Flash-based technology [8], although it does not allow the same number of reconfiguration cycles by an order of magnitude, it is of interest for some stringent niche applications such as space and aircraft industries. Indeed, Flash technology preserves the configuration of the FPGA when the power is off, and as a consequence, the chip is ready to operate as soon as it is powered up. The generic architecture of an SRAM-based FPGA is presented in Fig. | [48].

By making the assumption that the studied three-phase sys- tem is balanced (no zero-sequence component), the transforma- tion can be simplified and expressed as electrical systems. The coordinate transformation is used to transform the actual quantities of a three-phase electrical sys- tem (%,,2p,2-) into a dq reference frame that is rotating at an arbitrary angle 9 while keeping the instantaneous power equivalent. It gives

Fig. 4. Reuse and IP module libraries. Fig.5. DFG of the coordinate transformation algorithm.

Fig. 6. ALU data paths of the coordinate transformation.

Fig. 7. Performance of the different ALU after synthesis.

Fig. 9. Timing distribution. (a) General-purpose microcontroller, (b) DSP controller, and (c) FPGA-based controller

Fig. 10. Block diagram of the DTC technique.

Fig. 14. Estimator architecture factorized by the use of A? methodology.

Fig. 16. Experimental results torque step response 0 to 4 nm, T’; = 50 ps. (a) DTC. (b) DTRFC

Fig. 19. Voltage response with control system. Fig. 18. Simulation results. The graph shows that the controller is successful in stabiliz- ing the generator system. Although there is a voltage drop of about 14% when the load resistance is decreased, this effect is counteracted by the controller, and the voltage level recovers

In this example, the rules state that the output signal wu is PB when the output condition is C!, C?, or C®. The dc output voltage is simulated during a step increase of the load current. The results in Fig. 18 show that the fuzzy logic control system is successfully correcting the tendency to fall of the output voltage Vqa-. The system is therefore able to cope with variations in V4. resulting from variable load and variable speed of operation. After the complete system was modeled and simulated using VHDL, the circuit design of the controller was synthesized and implemented into a Xilinx XC4010 FPGA for rapid prototyping. By adjusting the speed of the engine to the operating conditions, fuel consumption can be reduced while the same torque can be produced. Fig. 19 shows the voltage response when the controller is connected to the system. The desired dc voltage is set at 250 V.

FUNCTIONAL ALGORITHM DECOMPOSITION direct torque and rotor flux control (DTRFC) with the use of space vector modulation (SVM) for induction motor drives. Indeed, due to their similar structures but also their differences, these two algorithms are good examples to show the effective- ness of an FPGA-based functional modular approach to im- plement sensorless control induction motor drives. Therefore, the chosen solution is based on a custom hardware architecture designed by assembling a set of functional building blocks. These blocks are tested and organized in a library of IP modules for easy reuse [107]. Each block is geared toward a specific algorithm function (flux estimator, hysteresis controller, etc.). A special attention is given to the algorithm refinement, which allows finding the optimum fixed-point data word length for each internal variable of the algorithm. Finally, experimental results are shown, which validate the proposed approach. Fig. 11. Block diagram of SVM-DTRFC strategy.

is based on torque and rotor flux control [109]. Moreover, in this case, the voltage source inverter is controlled indirectly by using the SVM in a similar way with what was proposed in [110]. This technique allows a smoother behavior of the torque regulation at steady-state operation than basic DTC. Fig. 12. DFG of the a-axis stator flux estimator.

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64-bit floating-point FPGA matrix multiplication

by Georgi Gaydadjiev

2005

We introduce a 64-bit ANSI/IEEE Std 754-1985 floating point design of a hardware matrix multiplier optimized for FPGA implementations. A general block matrix multiplication algorithm, applicable for an arbitrary matrix size is proposed.... more

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A digital architecture for support vector machines: theory, algorithm, and fpga implementation

by Davide Anguita

2003, IEEE Transactions on Neural Networks

In this paper, we propose a digital architecture for support vector machine (SVM) learning and discuss its implementation on a field programmable gate array (FPGA). We analyze briefly the quantization effects on the performance of the SVM... more

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Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications

by Jean-jacques Quisquater

2004, International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004.

Hardware implementations of the Advanced Encryption Standard (AES) Rijndael algorithm have recently been the object of an intensive evaluation. Several papers describe efficient architectures for ASICs 1 and FPGAs 2 . In this context, the... more

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Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers

by piyush mishra

2002, IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems

Fault-based side-channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy-based concurrent error detection (CED) architectures can be used to... more

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A quantitative analysis of the speedup factors of FPGAs over processors

by Walid Najjar

2004, Proceeding of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays - FPGA '04

The speedup over a microprocessor that can be achieved by implementing some programs on an FPGA has been extensively reported. This paper presents an analysis, both quantitative and qualitative, at the architecture level of the components... more

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FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm

by Joseph R Cavallaro

2005, Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.

This paper presents a novel architecture for matrix inversion by generalizing the QR decomposition-based recursive least square (RLS) algorithm. The use of Squared Givens rotations and a folded systolic array makes this architecture very... more

ig. 1. Systolic Array for QR Decomposition. Let A be n xp matrix of full rank p. The QR decomposition is decomposing matrix A to a triangular matrix Rp.» and an orthogonal matrix Q using plane rotations.

Fig. 2. Systolic Array for 4x4 Matrix Inversion. The systolic array for inverting a 4 x 4 matrix is shown in Fig. 2. If we implement every single node in this diagram, it requires a large area and has very high throughput. In our approach, we combined similar nodes, added memory blocks and a scheduler that controls movement of data between nodes (See Fig.3). In this figure, boundary and internal cells are same as the ones in Fig. 1. The back substitution cell is a combination of four cells DJ1;, 012;, L[3;, DB;.

The block diagram of an internal cell is shown in Fig. 5. Inputs are the values for uoia,v,c,w and vz and outputs are the values for U, 0.

and outputs to each of the nodes and memory blocks of the system. VI. FPGA IMPLEMENTATION

NUMBER OF OPERATIONS USED BY SGR AND SDGR FOR INVERTING 4x4 MATRIX OF REAL NUMBERS numbers. TABLE I Another rotation algorithm which is very suitable for fixed- point calculations, is CORDIC (COordinate Rotation DlIgital Computer) [6]. It is an iterative algorithm for calculating trigonometric functions such as sine and cosine. This algorithm is a combination of shifts and adds and does not require any multiplications [7], [8], [9],.

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FPGA Implementation of Embedded Fuzzy Controllers for Robotic Applications

by Alejandro Cabrera

2007, Industrial Electronics …

Fuzzy-logic-based inference techniques provide efficient solutions for control problems in classical and emerging applications. However, the lack of specific design tools and systematic approaches for hardware implementation of complex... more

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Comparison of the FPGA Implementation of Two Multilevel Space Vector PWM Algorithms

by Oscar Lopez Lopez

2008, IEEE Transactions on Industrial Electronics

Multilevel converters can meet the increasing demand of power ratings and power quality associated with reduced harmonic distortion and lower electromagnetic interference. When the number of levels increases, it is necessary to control... more

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FPGA implementation of MD5 hash algorithm

by Ramachandran Venkatesan

2001, Electrical and Computer …

Data integrity assurance and data origin authentication are essential security services in financial transactions, electronic commerce, electronic mail, software distribution, data storage and so on. The broadest definition of... more

The output of the fourth round is added to the input of the first round (CV ,) to produce CV gy1.

Figure 4. Optimized operation tree MD5 algorithm is a block-chained hashing algorithm. The hash for a block depends on both the block data and the hash of its preceding block. As a result, blocks can not be hashed in parallel. Each step consists of four additions, three component logical operations, two table lookups and one rotation. The tree of operations can be optimized by performing operations, which involve items not dependent on the previous step, early. According to Figure 3, the item that depends on the previous step is word B and hence the result of logical operation has a considerable delay. The optimized tree of operation (assuming each operation takes one unit time) will be as given in Figure 4. According to this one time unit step can be reduced [7].

By implementing a generic step of the MD5 algorithm, a looping architecture with 64 iterations would seem to provide the greatest area optimized solution. The block diagram of the iterative design is shown in Figure 5.

Figure 5. Block diagram of MD5 iterative design (Iterate MD5).

Figure 8. Block diagram of full-loop-unrolling design (Fullun-MD5).

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RAMP gold

by Henry Cook and

2010, Proceedings of the 47th Design Automation Conference on - DAC '10

We present RAMP Gold, an economical FPGA-based architecture simulator that allows rapid early design-space exploration of manycore systems. The RAMP Gold prototype is a high-throughput, cycle-accurate full-system simulator that runs on a... more

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Functional DIF for Rapid Prototyping

by William Plishker

2008, 2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping

Dataflow formalisms have provided designers of digital signal processing systems with optimizations and guarantees to arrive at quality prototypes quickly. As system complexity increases, designers are expressing more types of behavior in... more

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FPGA Implementation of High Speed FIR Filters Using Add and Shift Method

by Ryan Kastner

2006, 2006 International Conference on Computer Design

We present a method for implementing high speed Finite Impulse Response (FIR) filters using just registered adders and hardwired shifts. We extensively use a modified common subexpression elimination algorithm to reduce the number of... more

An alternative to the above approach is Distributed Arithmetic (DA) which is a well known method to save resources. Using DA method, the filter can be implemented either in bit serial or fully parallel mode to trade bandwidth for area utilization. Assuming coefficients c[n] are known constants, equation (I) can be rewritten as follows: these multipliers i is typically limited. Furthermore, the size of these multipliers is limited to only 18 bits, which limits the precision of the computations for high speed requirements. The ideal implementation would involve a sharing of the Combinational Logic Blocks (CLBs) and these multipliers. In this paper, we present a technique that is better than conventional techniques for implementation on the CLBs.

Figure 2. A serial DA FIR filter block diagram Though the serial DA architecture is efficient by construction, its performance is limited by the fact that the next input sample can be processed only after every bit of the current input samples are processed. Each bit of the current input samples takes one clock cycle to process.

Figure 4. Replacing constant multiplication by multiplier block

Figure 3. A 2 bit parallel DA FIR filter block diagram

Performing subexpression elimination can sometimes increase the number of registers substantially, and the overall area could possibly increase. Consider the two expressions F, and F, which could be part of the multiplier block.

Figure 6. Unoptimized expression trees Figure 6 shows the original unoptimized expression trees. Both the expressions have a minimum critical path of two addition cycles. These expressions require a total of six registered adders for the fastest implementation, and no extra registers are required. From the expressions we can see that the computation A + B + C is common to both the expressions. If we extract this subexpression, we get the structure shown in Figure 7. Since both D and E need to wait for two addition cycles to be added to (A + B + C), we need to use two registers each for D and E, such that new values for A,B,C,D and E can be read in at each clock cycle. Assuming that the cost of an adder and a register with the same bitwidth are the same, the structure shown in Figure 7 occupies more area than the one shown in Figure 6. A more careful subexpression elimination algorithm would only extract the common subexpression A + B (or A+C or B + C). The number of adders is decreased by one from the original, and no additional registers are added. This is illustrated in Figure 8. The algorithm for performing this kind of optimization is described in the next section.

Figure 8. Extracting common subexpression (A+B)

Figure 12 compares power consumption for our add/shift method versus Coregen™. From the results we can observe up to 50% reduction in dynamic power consumption. We did not include the quiescent power into our calculation since that value is the same for both methods. The power consumption is the result of applying the same test stimulus to both designs and measuring the power using XPower tools provided by Xilinx ISE software.

Table 1b. Filter Synthesis using Coregen (PDA method)

Table la. Filter Synthesis using Add Shift method Figure 11 plots the reduction in the number of resources, in terms of the number of Slices, Look Up Tables (LUTs) and the number of Flip Flops (FFs). From the results, we can observe an average reduction of 58.7% in the number of LUTs, and about 25% reduction in the number of slices and FFs. Though our algorithm does not optimize for performance, the synthesis produces better performance in most of the cases, and for the 13 and 20 tap filters, we observe about 26% improvement in performance.

Table 2. Comparing with MAC filter on Virtex IV From the table, it can be seen that the MAC filter uses fewer number of slices compared to the add-shift method, but it also

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AF-QCN: Approximate Fairness with Quantized Congestion Notification for Multi-tenanted Data Centers

by Mohammad Ali Alizadeh

2010, 2010 18th IEEE Symposium on High Performance Interconnects

Data Center Networks represent the convergence of computing and networking, of data and storage networks, and of packet transport mechanisms in Layers 2 and 3. Congestion control algorithms are a key component of data transport in this... more

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Fault-Based Side-Channel Cryptanalysis Tolerant Rijndael Symmetric Block Cipher Architecture

by piyush mishra

2001

Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based Concurrent Error Detection (CED) architectures can be used to... more

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An Improved Unified Scalable Radix2 Montgomery Multiplier

by Steven Hsu

2005

Tenca-Koç unified scalable radix-2 Montgomery multiplier with half the latency for small and moderate precision o perands and half the queue memory requirement. Like the Tenca-Koç multiplier, this design is reconfigurable to accept any... more

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FPGA based Speeded Up Robust Features

by Jan Faigl

2009

We present an implementation of the Speeded Up Robust Features (SURF) on a Field Programmable Gate Array (FPGA). The SURF algorithm extracts salient points from image and computes descriptors of their surroundings that are invariant to... more

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A fixed-frequency quasi-sliding control algorithm: application to power inverters design by means of FPGA implementation

by Rafael Ramos

2003, IEEE Transactions on Power Electronics

In this paper a fixed-frequency quasi-sliding control algorithm based on switching surface zero averaged dynamics (ZAD) is reported. This algorithm is applied to the design of a Buck-based inverter, and implemented in a laboratory... more

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Real-time face detection and lip feature extraction using field-programmable gate arrays

by Dui Nguyen

2006, IEEE Transactions on Systems, Man, and Cybernetics

This paper proposes a new technique for face detection and lip feature extraction. A real-time field-programmable gate array (FPGA) implementation of the two proposed techniques is also presented. Face detection is based on a naive Bayes... more

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Networks on chip as hardware components of an os for reconfigurable systems

by Will Moffat

2003, … Logic and Applications

Abstract. In complex reconfigurable SoCs, the dynamism of applica-tions requires an efficient management of the platform. To allow run-time allocation of resources, operating systems and reconfigurable SoC plat-forms should be developed... more

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High Speed FPGA-Based Implementations of Delayed-LMS Filters

by Roger Woods

2000, The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology

A variation of the least means squares (LMS) algorithm, called the delayed LMS (DLMS) algorithm is ideally suited for highly pipelined, adaptive digital filter implementations. In this paper, we present an efficient method to determine... more

Figure 1. Adaptive filter in ESM receiver system. High Speed FPGA-Based Implementations of Delayed-LMS Filters

In these expressions, x,, y, and e, are the input, out- put and error samples respectively for the current time step n the ste of the FIR filter, d, is the desired signal, ju is p size of the coefficient adaptation, and w,, is the tap-weight vector. The adaptive FIR filter output y,, is com pared with the desired signal d,, to produce the error signal error signal e,. The error signal represents the dif output. ference between the desired signal and model The error e, is then used as the input to an adaptive control algorithm e.g. LMS algorithm, which correct s the individual tap weights of the filter. This process is repeated through several iterations until the error signal e, becomes sufficiently small. The feed- back of the error signal needed to update filter weights in the LMS algorithm imposes a critical limitation on the throughput of possible implementations [8, 9]. 3. Adaptive Delayed LMS Algorithm Adaptive filters have uses in a number of applications that require differing filter characteristics in respo to variable signal conditions, such as noise cance nse la- tion, linear prediction, adaptive signal enhancement, and adaptive control. The LMS algorithm is the most widely used adaptive filtering algorithm in practice The wide spectrum of applications of the LMS al [7]. g0o- rithm can be attributed to its simplicity and robustness to signal statistic. The LMS algorithm can be descri in three parts: bed

The main challenge now is to use these delays as a means of pipelining the LMS filter. This process firstly involves the determination of the number of Figure 4. An 8-tap DF-DLMS algorithm architecture.

Figure 3. Equivalent structure of the DLMS algorithm (mD is an m unit delay).

Figure 5. An 8-tap TF-DLMS algorithm architecture. High Speed FPGA-Based Implementations of Delayed-LMS Filters

Given the relatively equivalent performance of adders and multipliers in the Xilinx Virtex II FPGA family, each adder/subtractor and multiplier block is assumed to have a single pipeline stage. Firstly, the SFG is examined to determine if delay scaling is nec- essary [14]. Sixteen loops labelled ( ), were identified in the 8-tap predictor system with the TF-DLMS archi- tecture, as demonstrated by the heavy line paths shown in Fig. 6. The potential pipelining periods associated with the 9th loop to the 16th loop are equal to 1. The calculation of the 8th loop pipelining period ag is shown above. Bg is the total number of delays around the 8th loop given by summing the latency of the adders/subtractors and multipliers. Dg is the pure delay in the 8th loop be- fore the pipelined processors are considered and in- cludes the unknown amount of delays (mD) that offer the chance of reducing the clock period of the circuit by using retiming. The pipelining period wgis determined and equates to | cycle in order to generate a high-speed

Figure 6. Recursive loops in the 8-tap TF-DLMS predictor system.

Figure 7. A retimed 8-tap predictor system with the TF-RDLMS architecture. rd) =r(3) =r(5) =r) =rQ9) =r) =rd3) r(15) = 0; The TF-RDLMS N-tap filter has been constructed using a Processing Module (PM) structure that is shown can be used to obtain the retimed TF-DLMS filter (TF- RDLMS) in Fig. 7 where the numbers refer to the var- ious nodes (operations) as shown. For example, the r(16) = —1 means one delay is moved from each out- put edge of node 16 to each input edge. The r(15) = 0 means that no delay was pushed through node 15. The edge 15 — 16in the retimed circuit contains one delay because the original edge contains no delay, one delay is moved into the edge (r(16) = —1) and no delay is moved out (r(15) = 0). The SFG can be retimed by redistributing the 4 de- lays in the error feedback path (EFP) to the coefficient update loop (CU P) and filter feed-forward path (FFP). The positive retiming value r(v) is the number of de- lays drawn from pushed to each o retiming r(v) is t each of incoming edges of node v and f out-going edges. The negative value he number of delays drawn from each outgoing edge and pushed to each of incoming edges. The retiming values:

Figure 9. Recursive loops in the 8-tap predictor system with the DF-DLMS architecture. The same method is used to decide the optimal m values for DF-DLMS and TDF-DLMS circuits. The SFG of the 8-tap predictors with DF-DLMS and TDF-DLMS architectures also exhibit sixteen loops shown in Figs. 9 and 10. The optimal values of DF-DLMS architecture from m, tomg are 11D ,..., 4D. The optimal value m of DF-DLMS architecture is 11D. The SFG of retimed in Fig. 8. In this PM structure, the filter weights are updated locally, therefore the order of a TF-RDLMS filter can be increased by adding more PM elements. The cascaded structure of PMs also has the advantage that increasing the filter order does not increase the filter critical path. The latency of the error signal e(7), which is used to update the filter coefficient and affect the filter performance, is increased by 4 delays rather than by 3N delays as in the TF-FPDLMS [4] structure.

Figure 8. Transposed-Form fine-grain Retiming DLMS filter achicture.

Figure 11. A retimed 8-tap predictor system with the DF-RDLMS architecture. Figure 10. Recursive loops in the 8-tap predictor system with the TDF-DLMS architecture.

High Speed FPGA-Based Implementations of Delayed-LMS Filters

Figure 12. A retimed 8-tap predictor system with the TDF-RDLMS architecture. In order to allow a proper comparison, a number of FPGA implementations for an 8-bit/8-tap predictor system implemented on a Virtex-II XC2V250fg256-5 chip were undertaken. The post-layout information is given in Table 3. The 8-bit x 8-bit signed embedded multipliers and dedicated adders/subtractors were used and the 16-bit shift register (SRL16) was used to imple- ment multiple delays in order to decrease circuit area for anumber of the designs. In designs, a step size of the power of 2 was used in the filter to reduce the scaling multiplication in the filter to a simple shift operation. Wordlengths were determined for the application given in [4]. A number of important features can be highlighted from these results. Firstly, the implementation results obtained by the design tools show that the system per- formance can reach up to 182 MHz for the TF-RDLMS predictor with 8-bit input. Secondly, apart from the TF-LMS which has a larger critical path and is much slower, the new designs have a much smaller area usage as indicated by the slice numbers. Thirdly, the speedup for the retimed TF-RDLMS design is nearly 3 times that of the TF-LMS design. This is lower than the es- timated theoretical result in the previous section and is due to the interconnect delay which can often be up to as much as 60% of the total critical path in an FPGA. Table 1. Comparison of the characteristics of different architectures.

tem with the TF-RDLMS architecture was used. Us- ing a target throughput rate of 80 MHz, a pipelining period, a, of 2 cycles was used as the sampling rate which was less than half of the clock rate (180 MHz). n the 8-tap TF-RDLMS predictor (Fig. 7), all the de- ays were scaled by 2. Retiming was then used to give the retimed filter in Fig. 13. This implementation com- bines four taps into a single resource type (4Tapx), PMO to PM3 combined into one operation 4Tap0 and PM4 to PM7 combined into operation 4Tap1. The sys- tem cycle can be divided into two groups, one con- sisting of clock cycles 0,2,4,..., the other of cy- cles 1,3,5... The 4TapO and 4Tap1 functions were scheduled for the first and second groups respectively, thereby giving a direct throughput/area trade off. The N/2-tap TF-RDLMS (TF-RDLMS1/2) filter has been constructed using a Processing Module (PM) structure (Fig. 14). Three hardware shared transposed-form fine-grained retimed DLMS (HS-TF-RDLMS) filters were devel- oped to allow area/speed trade-off of the TF-RDLMS filter. This clearly opens up the possibility of devel- oping a parameterisable intellectual property (IP) core, where throughput rate can be used to dictate the amount of hardware folding needed. An 8-tap predictor sys- Figure 13. A retimed TF-RDLMS filter architecture (pipeline period a = 2).

Figure 15. TF-RDLMS1/2 filter critial path control dependency.

(C) N-order TF-FRDLMS1/4 Circuit (a=4 and sampling rate=40MHz)

(b) N-order TF-FRDLMS1/8 Circuit (o=8 and sampling rate=20MHz)

(b) N-order TF-RDLMS1/2-NEW Hardware Sharing Filter (a=2 and sampling rate=86MHz)

(b) N-order TF-FRDLMS 1/4-NEW Circuit (a=4 and sampling rate=47MHz)

(b) N-order TF-FRDLMS1/8-NEW Circuit (o=8 and sampling rate=25MHz)

Figure 21. Convergence behavior of the different LMS. Figure 20. TF-RDLMS1/8-NEW filter.

Ying Yi received a first honours B.Sc. degree in Computer and Ap- plication from the Harbin Engineering University, Harbin, China in 1996. She then joined the WuHan Institute of Mathematical Engi- neering, China, as a software engineer researching, developing and maintaining Intranet and Management Information Systems (MISI). From 1997 to 2000, she worked with China Ship Research & De- velopment Academy (CSRDA), Beijing, China involved in research, development and management of computer correlative problems. She received the degree of Ph.D. from the Queen’s University Belfast in 2003. Currently, she is a research fellow in the School of Engineering and Electronics at the University of Edinburgh. Her research inter- ests include architectural synthesis of FPGA-based circuit, adaptive signal processing and low power SoC systems. M. Yi@ed.ac.uk In this paper, three novel FPGA implementations of retimed DLMS filters have been presented. These are capable of achieving a 182 Msample/s sampling rate performance for an 8-bit TF-RDLMS predictor system with nearly 3 times faster speed and 31% increase in the area compared to an 8-bit TF-LMS predictor sys- tem. It has also been shown that system architecture can be implemented in a variety of ways because of different specifications (area and speed). These differ- ent methods will allow a designer to explore trade-off at a high-level in the design flow. This process is being automated in the IRIS architectural synthesis tool cur- rently being developed at Queen’s University allowing circuits to be rapidly designed.

Roger Woods received the degree of B.Sc. with Honours in Electri- cal and Electronic Engineering and degree of Ph.D. from the Queen’s

Lok-Kee Ting was born on September 28, 1973, in Malaysia. He re- ceived the degree of B.Eng. with honours in Electrical and Electronic Engineering from Queen’s University of Belfast, UK, in 1998, and the degree of Ph.D from the same university in 2001. His research interests are in the adaptive filter algorithm development, high-speed FPGA implementations and general VLSI architectures. He joined University of Belfast, UK in 1985 and 1990 respectively. From 1994, he has been a Senior Lecturer in the School of Electrical and Elec- tronic Engineering at the same university. His main research interests are in programmable systems using FPGAs, design tools for hetero- geneous platforms and low power VLSI. Dr Woods has published over 100 papers in the area of VLSI signal processing and he holds two patents. He was the chair of 2001 Field Programmable Logic con- ference and has served on the technical program committee of various IEEE conferences/workshops including Field-Programmable Cus- tom Computing Machines, Signal Processing Systems and Applica- tion Specific Array Processors. rwoanade@ee anh ac nk

Colin F.N. Cowan currently holds the Nortel Networks/Royal Academy of Engineering research professorship in Telecommuni- cations at the Queen’s University of Belfast. He was Professor of Signal Processing at Loughborough University from 1991 to 1996, and head of the Electronic & Electrical Engineering Dept. at Lough- borough from 1994 to 1996. During his time at Loughborough he was the head of the Communications & Signal Processing research group, within which he still holds a visiting chair. From 1989 to 1991 he was a reader in the Electrical Engineering Dept. at the Uni- versity of Edinburgh, and a Lecturer from 1980 to 1989. He has published over 200 papers and articles in the area of adaptive signal processing and has been actively involved in the organisation of a number of key international conferences, including chairing the Ist IEE International Conference on Artificial Neural Networks in 1989 and the 7th European Signal Processing Conference (EUSIPCO) in 1994. Intel in 2001, and currently works as VLSI design engineer involved in the design of the next generation network processor.

Table 2. Speedup for the proposed RDLMS architectures (T,, = Ty).

Table 3. Virtex-II implementation (post-layout) results for sampling rate and area. Finally, the retimed designs show better routing inter- connection delays than their non-pipelined counterpart as the pipelining registers act to shorten the intercon- nect delay. The limited area increase of 31% for the TF-RDLMS architectures indicates that pipelining, if only in some contexts, is essentially ‘free’ and very much dependent on the circuit architecture.

Table 5. Hardware sharing circuit (post-layout) results for sampling rate and area.

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FPGA Implementation of Genetic Algorithm for UAV Real-Time Path Planning

by Gilles Labonté

The main objective of an Unmanned-Aerial-Vehicle (UAV) is to provide an operator with services from its payload. Currently, to get these UAV services, one extra human operator is required to navigate the UAV. Many techniques have been... more

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Maximum power point tracking using a GA optimized fuzzy logic controller and its FPGA implementation

by abderrezak guessoum

2011, Solar Energy

Solar energy is a green energy which is not only perennial but also accessible to every strata of the world. An easy way to convert solar energy into electric energy is to use Solar Photovoltaic (SPV) system. Solar panel is a power source... more

The simulation results are shown in Fig.2. The comparison of the model parameters with manufacturer’s datasheet (SOLKAR module) is given in Table-I. Fig.4. Model Characteristics of SOLKAR solar module at different Temperatures (G=1000 W/m’)

The non linear optimization function used for GA is as stated in (9). The block diagram of the proposed MPPT scheme is shown in the Fig.6. In this scheme ANN is used to find out the maximum voltage. The ANN is trained by a set of input and output data which are optimized using GA.

Artificial neural networks are best suited for the approximation of non-linear systems.Non-linear systems can be exactly emulated by multilevel neural networks.They give best results than other algorithms.Neural networks contain three layers namely input layer,hidden layer,output layer.Feed-forward neural network is the simple type of neural networks.In this type the information moves in only forward direction,input nodes to hidden nodes and to output nodes.There are no cycles or loops in this network. The block diagram of the ANN for producing maximum voltage and power for given G and T is shown in Fig.5.The neural network used here has two input layers,hidden layers and two output layers and back propagation trainig method is used.

Fig.8. Feed Forward Neural Network for MPPT The structure of the proposed neural network is shown in Fig.8.The training result of ANN is shown in Fig.9. The voltage is compared with the SPV Array voltage and the error is given to the PI controller. PI controller is used with ANN block to reduce the steady state error. This PI controller is tuned using Ziegler-Nichols tuning method. The output of the PI controller is compared with high frequency triangula1 wave.And this pulse is given to the boost converter circuit to change the output of the system. The proposed MPPT system shown in Fig.6 is simulated using MATLAB-SIMULINK.

Fig.7 The trend of convergence of GA Fig.7 plots the convergence of total power computed by GA over the number of iterations for different insolation and temperature.

Fig.10 Simulation output for G=1000 W/m’, T=25°C Fig.11 Simulation output for G=200 W/m”, T=31.9°C

The simulated output waveforms for two different insolation levels and temperatures are shown in Fig.10 and Fig. 11.

The genetic algorithm parameters used in this work are given in Table II.

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Real-time canny edge detection parallel implementation for FPGAs

by Spiridon Nikolaidis

2010, 2010 17th IEEE International Conference on Electronics, Circuits and Systems

Edge detection is one of the most fundamental algorithms in digital image processing. The Canny edge detector is the most implemented edge detection algorithm because of its ability to detect edges even in images that are intensely... more

Our Canny implementation will be used by a lab on chip system on a Spartan 6 FPGA. Therefore we use the results produced by the Spartan 6 synthesis for our simulation. We simulate the design by using 3 different image file sources which are 8bit grayscale files of varying sizes. In Fig. 6 the input and the output files of the Canny implementations are demonstrated. Fig. 6.c and 6.d is an example frame of a video for a lab on chip experiment. The timing results are presented in Table II.

After smoothing the next step is the calculation of the gradient of the image. The gradient calculation leads to the detection of the possible edge strength and direction. This is executed by another convolution with a gradient operator. The most commonly used gradient operators are the Prewitt and the Sobel operators. Both operators perform a 2-D spatial gradient measurement on an image. The Sobel edge detector uses a pair of 3x3 convolution masks, one estimating the gradient in the x- direction (columns) and the other estimating the gradient in the y-direction (rows). The Sobel operators are presented in Fig. 2. Gradient magnitude and orientation is defined by the following equations:

Figure 3. 4-pixel parallel Gaussian smoothing calculation and addition/subtraction to increase speed. The results are stored in a cache used as an input for the next stage.

(a) lena input, (b) lena output, (c) HCLAchip input, (d) HCLAchip output, (e) disc-brake input, (f) disc-brake output

TABLE II. CANNY TIME RESULTS As can be seen for an image of 1.2Mpixel we have achieved a computation time of 3.09ms. Thus, for an image of 1 Mpixel a rate of 396 frames per second has been achieved, which is far beyond our set specifications for a real-time design. On the Virtex-5 the throughput reaches the number of 580 frames per second for 1Mpixel images. Even in the low-end Spartan-3E

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Hydra: A Block-Mapped Parallel Flash Memory Solid-State Disk Architecture

by Hongseok Kim

2010, IEEE Transactions on Computers

Flash memory solid-state disks (SSDs) are replacing hard disk drives (HDDs) in mobile computing systems because of their lower power consumption, faster random access, and greater shock resistance. We describe Hydra, a high-performance... more

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Synchronization in Software Radios-Carrier and Timing Recovery Using FPGAs

by fred harris

2000

Software defined radios ( S D R ) are highly configurable hardware platforms that provide the technology for realizing the rapidly expanding third (and future) generation digital wireless communication infrastructure. Many sophisticated... more

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A Time-Area-Power Efficient Multiplier and Square Architecture Based On Ancient Indian Vedic Mathematics

by Hamid R. Arabnia

2004

TABLE 2- 4 x 4 bit Square Using Duplex of Urdhva Tiryakbhyam D- Duplex TABLE 1- 4 x 4 bit Vedic multiplier Using Urdhva Tiryakbhyam

Table 3: Timing Simulations (Comparisons of the Multipliers)

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Digital Sliding-Mode Observer Implementation Using FPGA

by G. Gateau

2000, IEEE Transactions on Industrial Electronics

This paper details the digital implementation of a new observation strategy of the flying capacitor voltages dedicated to stacked multicell converters (SMC). This particular topology relies on the use of flying capacitors so as to equally... more

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FPGA implementation of K-means algorithm for bioinformatics application: An accelerated approach to clustering Microarray data

by Huseyin Seker

2011, 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

The Microarray is a technique used by biologists to perform many genome experiments simultaneously, which produces very large datasets. Analysis of these datasets is a challenge for scientists especially as the number of genome databases... more

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FPGA implementation of Izhikevich spiking neural networks for character recognition

by Melissa Smith

2009, … Computing and FPGAs

Figure 1. Spikes produced with Izhikevich model. Input images were presented to the first layer of neurons (which we refer to as level 1), with each image pixel corresponding to a separate input neuron. Thus the number of neurons in level 1 was equal to the number of pixels in the input image. The number of second layer neurons (which we refer to as level 2) was equal to the number of training images. This is because each level 2 neuron was encoded to fire only when it recognized one specific image. Lastly, each level 1 neuron was connected to every level 2 neuron. A small scale version of this network is shown in Fig. 3.

Each neuron has an input current / that is used to evaluate its membrane potential, V. If this membrane potential crosses a certain threshold (30 mV for our design) during a cycle, the neuron is considered to have fired. In case of a level 1 neuron, the input current, J, is zero if the neuron’s corresponding pixel in the input image is “off”. If the pixel is “on”, a constant current is supplied to the input neuron. A level 2 neuron’s overall input current is the sum of all the individual currents received from the level 1 neurons connected to it. This input current for a level 2 neuron is given by (3):

The elements of the weight matrix w are determined through a training process where a set of training images are Figure 3. Illustration of network connections between level | and level 2 neurons. f is a firing vector in which f(i) is 0 if the 7” level 1 neuron does not fire, and is | is the neuron does fire. w is a weight matrix in which w(i,j) is the input weight from the level 1 neuron i to the level 2 neuron /.

Figure 4. Overall Spiking Neural Network Design on Cray XD1.

Weight computations involve streaming the indices of the level 1 neurons that fired (stored in the local firing vector of Figure 5. State machine for spiking neural network controller.

LE I, STURCTURE OF NEURAL NETWORKS EXAMINED

TABLE IIL. HARDWARE-ACCELERATED TIMING BREAKDOWN

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Power analysis attacks against FPGA implementations of the DES

by Berna Ors Yalcin and

2004, Field Programmable Logic …

Cryptosystem designers frequently assume that secret parameters will be manipulated in tamper resistant environments. However, physical implementations can be extremely difficult to control and may result in the unintended leakage of... more

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An analytical performance model for the Spidergon NoC with virtual channels

by Wim Vanderbauwhede

2010, Journal of Systems Architecture

cost. The spidergon topology is a novel architecture which is proposed recently for NoC domain. The objective of the spidergon NoC has been addressing the need for a fixed and optimized topology to realize cost effective multi-processor... more

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Real-Time Optical Flow Calculations on FPGA and GPU Architectures: A Comparison Study

by Dah-jye Lee and

2008, 2008 16th International Symposium on Field-Programmable Custom Computing Machines

FPGA devices have often found use as higherperformance alternatives to programmable processors for implementing a variety of computations. Applications successfully implemented on FPGAs have typically contained high levels of parallelism... more

Figure 3. The Yosemite sequence and the measured optical flow field: 8th frame of Yosemite se quence (left) optical flow field (right)

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An FPGA implementation of a GF(p) ALU for encryption processors

by Emanuel Popovici

2004, Microprocessors and Microsystems

Secure electronic and internet transactions require public key cryptosystems to establish and distribute shared secret information for use in the bulk encryption of data. For security reasons, key sizes are in the region of hundred's of... more

Fig. 2. Modular subtraction. To perform modular subtraction, input B is bitwise inverted and added to input A with a carry-in of ‘1’. If the result is negative (i.e. the carry-out is low) then the modulus must be added to produce an output in the range [0, M — 1]. An architecture to perform modular subtraction is illustrated in Fig. 2. In this architecture, the value of ((A — B) + M) is computed while the relative magnitude of A and B is being determined. By this method, both possible results are computed in slightly more time than a single m-bit addition, and the correct result is selected depending on the carry out bit of the (A — B) stage. This eliminates the necessity to await a full m-bit magnitude comparison before deciding whether to add M or not.

used with the sum and bitwise inverted modulus as inputs, and the carry-in tied to ‘1’, thus performing two’s compliment subtraction. The carry-out of this adder is then an indication that (A + B) is greater than or equal to M. This signal controls the multiplexer which selects whether (A + B) or ((A + B) — M) is the correct result. 3.5. Modular multiplication

To map the number back to the integer domain, it must be Montgomery multiplied by ‘1’:

As stated in Section 3.8, the Montgomery domain inverse operation takes a constant 2m clock cycles in order to resist timing cryptanalysis attacks. In order to compute the actual inverse (A~' mod M) of an integer input A, the same number of clock cycles must be spent reducing the result modulo M, meaning a total of 4m clock cycles per integer inversion. However, one Montgomery modular multipli- cation takes m clock cycles, while simultaneously reducing the product. After performing the Montgomery domain inversion on an input C, the output equals C7 '27”"(mod M). Lines 08 and 09 of Algorithm 2 can be combined into a single modular subtraction performed using the architecture of Fig. 2, by setting input A to the modulus, and input B to the intermediate result, R. Lines 03 and 04 of Algorithm 3

A = MonPro(A, (27” mod M), M) = A2”” mod M

and hence their greatest common divisor (gcd) = 1. The Montgomery inverse of A is defined as:

Input selection for the 3 adders for each mode of operation Table 1

Results for the GF(p) ALU on Xilinx Virtex2 xc2v2000-6 FPGA Table 2

Clock cycles and execution time for ECC operations in GF(p) ALU Table 4

Target device: Xilinx Virtex2000e-6 FPGA on Celoxica RC1000 board. Implementation results for the application example of (48) mod M Table 3

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An FPGA-Based Network Intrusion Detection Architecture

by Abhishek Das

2008, IEEE Transactions on Information Forensics and Security

Network intrusion detection systems (NIDSs) monitor network traffic for suspicious activity and alert the system or network administrator. With the onset of gigabit networks, current generation networking components for NIDS will soon be... more

related work, and Section VII concludes the paper and presents the areas of future work. data and, therefore, reduces the computational cost of analyzing new data. PCA methodology has been successfully used in signal processing, namely the Karhunen Loeve Transformation [15], and image processing for compression and restoration. In the case of the KDD Cup 1999 data, where each connection record has 41 features, we will show that PCA can effectively account for up to 50% of the variation or relative significance of the data with only five principal components. Being able to capture such a large fraction of the variation by only using a small number of features is certainly a desirable property for the hardware implementation, (i.e., such an algorithm is likely to reduce the hardware overhead significantly).

Fig. 2. FPGA architecture with feature extraction and PCA. extracted from the packets fed into the system. The FEM, in the next phase, uses these headers to extract the temporal and con- nection-based characteristics of the network. We discuss FEM in detail in Section III. This information or, in other words, the network features are then processed by the anomaly detection phase, which here is done by using PCA (as shown in the figure). Formulation of PCA and its application in anomaly detection are presented in Section IV. Details regarding the framework imple- mentation are dealt with in Section IV-E. tivity in a period of time, referred to as a “bursty attack.” SYN floods are an example, where connection tables are flooded in a period of time, disabling the victim machine to service new connection requests. Connection-based attacks do not have a recognizable temporal aspect. They are sometimes referred to as “pulsing zombie attacks.” Port scans may release connec- tion requests in the span of seconds or days. Therefore, intru- sion detection methods focusing on large volumes of network activity are ineffective. Our architecture can capture both con- nection and time-based statistics.

Fig. 5. Feature sketches executed in parallel.

Fig. 7. Effect of FS row length(K) on accuracy.

Fig. 8. Effect of FS row length (K) on average deviation.

Fig. 9. Detection and false alarm rate versus q.

FPGA. The number of fields (p) is the number of 32-b fields used to calculate the throughput of the PSCP pipeline. The #mult field is the number of 18 x 18-b block multipliers used.

TABLE VI and coordination may inhibit the advantages of parallelization. Also, the number of stages required to perform the summation also varies by logs(q). For example, with q = 1, there is no need for an adder tree. For g = 2 to gq = 4, two pipeline stages are required.

XILINX ISE 5.21 PLACE-AND-ROUTE STATISTICS (XC2VP100) stages in the second summation (see Table V) constant. The second summation is an intense operation from a bandwidth per- spective. As the data travel through the pipeline, an initial 32-b value gets multiplied twice and becomes 128 b wide. We use this pipeline configuration to preserve the accuracy in fixed-point arithmetic. The overall throughput increases moving from Q3 to Q4 but then decreases afterwards in Q6 and Q8. The reason for this behavior is the large bandwidth of the second summa- tion.

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An FPGA Implementation of the LMS Adaptive Filter for Audio Processing

by Ahmed Elhossini

2006, 2006 IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig 2006)

This paper proposes three different architectures for implementing a least mean square (LMS) adaptive filtering algorithm, using a 16 bit fixed-point arithmetic representation. These architectures are implemented using the Xilinx... more

Figure 1. Simplified Block Diagram of LMS adaptive filter

Figure 3. Flowchart of the Software Imple- mentation

Table 2. Profiling Results of The LMS algo- rithm after using HW accelerator(Clock Cy- cles)

Figure 7. FSL LMS FIR-Filter Architecture

The FPGA implementation results of all the cores used to implement the three architectures are shown in Table 3. The FIR core consumes a consid compared to the other cores. Its N, and its operating frequency other units. Optimizing the ad could result in a significant im; erable amount of resources size linearly increases with is the lowest compared to der tree used in the filter provement of the resource requirements of the core. The FIR core greatly affects the overall FPGA implementation results shown in Table 4 for the three architectures. Table 4 and Figure 11 show Figure 9. Profiling results for the 3 architec- tures for 32 taps

Table 3. Implementation Requirement For Each Core the FPGA resource utilization of each architecture. Ihe maximum clock frequency for each architecture is shown in Figure 12. The SW implementation resource requirements are fixed since the algorithm is implemented on a single soft core, and changing N requires just modifying the C code and recompiling it. In the HW/SW implementation, the FIR core adds an extra resource to the SW system, and thus the area of the system is affected by N. In addition modifying N requires rebuilding the HW system. The clock frequency of the system is decreased due to adding the FIR core that performs the filter calculation. The HW implementation requires more resources with large values of N since the FIR core size increases with N. The clock frequency for the HW architecture is almost fixed and close to that of the SW architecture. It is also compared to the clock frequency for the FIR core as shown in Table 3. The HW architecture is designed to reuse the existing cores used with the HW/SW architecture.

Table 4. Implementation Requirement for dif- ferent architectures

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A high bit resolution FPGA implementation of a FNN with a new algorithm for the activation function

by Fernando Dias

2007, Neurocomputing

Several implementations of Feedforward Neural Networks have been reported in scientific papers. These implementations do not allow the direct use of off-line trained networks. Usually the problem is the lower precision (compared to the... more

Figure 1 shows a detail of the linear section approach versus the single point approach.

The development of the circuit was done in the Quartus II environment. Figure 2 - Picture of the Cyclone SmartPack kit.

Figure 3 - Logical structure of the basic processing block in the ANNP. - The basic structure is composed of the multiplier, adder and activation function (Figure 3) and must be reused several times in order to implement the ANN.

The main window of this application that runs in MATLAB can be seen in Figure 4. Figure 4 - Main window of the debugging application.

possible to perform control action. The control strategy used was a simple Direct Inverse Control (DIC) that is represented in Figure 5. Figure 6 shows a block diagram of the connection between MATLAB and the FPGA and Table 1 shows the characteristics of the inverse models tested in the FPGA.

To complete the analysis of the results and separate the error that is introduced by the use of the FPGA from the one introduced by the models, the same control is performed with both models in MATLAB. Figure 7 - FPGA results with ramp signal.

The results in the form of Mean Square Error (MSE) are summarized in Table 2. As can be seen the difference obtained between the control with the FPGA and the ones simulated in MATLAB, in terms of MSE, does not exceed 5x10°. Figure 8 - FPGA results with ramp and square wave signal.

Figure 9 - FPGA results with pseudo-random signal. This objective was successfully accomplished as was shown by the control tests done with models of a real system, where the maximum error obtained between the MATLAB and the hardware solution, using the MSE as a measure was of 5x10°.

Table 1- Resume of the characteristics of the inverse models tested in the FPGA. 5. CONCLUSION and FUTURE WORK

The goal that was searched was to obtain a hardware solution that allowed the direct use of the weights,

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Parallel FPGA-based all-pairs shortest-paths in a directed graph

by Uday Bondhugula

2006

With rapid advances in VLSI technology, Field Programmable Gate Arrays (FPGAs) are receiving the attention of the Parallel and High Performance Computing community. In this paper, we propose a highly parallel FPGA design for the... more

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High-Speed AES Encryptor With Efficient Merging Techniques

by Ezz El-Masry

2010, … Systems Letters, IEEE

This letter presents a new efficient architecture for high-speed advanced encryption standard (AES) encryptor. This technique is implemented using composite field arithmetic byte substitution, where higher efficiency is achieved by... more

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Implementation and Comparison of the 5/3 Lifting 2D Discrete Wavelet Transform Computation Schedules on FPGAs

by Konstantinos Masselos

2008, Journal of Signal Processing Systems

The suitability of the 2D Discrete Wavelet Transform (DWT) as a tool in image and video compression is nowadays indisputable. For the execution of the multilevel 2D DWT, several computation schedules based on different input traversal... more

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Code construction and FPGA implementation of a low-error-floor multi-rate low-density Parity-check code decoder

by lei yang

2006, IEEE Transactions on Circuits and Systems I-regular Papers

With the superior error correction capability, low-density parity-check (LDPC) codes have initiated wide scale interests in satellite communication, wireless communication, and storage fields. In the past, various structures of single... more

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Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit symmetric block ciphers

by piyush mishra

2001

Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based concurrent error detection (CED) architectures can be used to... more

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FPGA implementation of I<sup>2</sup>C & SPI protocols: A comparative study

by Mohamed Berrandjia

2009, 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)

I 2 C and SPI are the most commonly used serial protocols for both inter-chip and intra-chip low/medium bandwidth data-transfers. This paper contrasts and compares physical implementation aspects of the two protocols through a number of... more

Figure 1. I°C-Slave Transceiver Architecture.

Figure 2. SPJ-Slave Transceiver Architecture.

* : N is the number of devices connected to a single master on the bus. +: Feature inducing substantial area overhead. F COMPARISON OF I°C AND SPI PROTOCOLS The paper is organized as follows. In this section, we showed the requirement specifications of a recent market investigation for modem I?C/SPI IPs and their corresponding architectures. Section two contrasts and compares the implementation results. And finally some concluding remarks.

* : (1369-950)/950 = 0.44 TABLE Il. COMPARISON OF RTL-CODES

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Electromagnetic side channels of an FPGA implementation of AES

by Herve Chabanne

We show how to attack an FPGA implementation of AES where all bytes are processed in parallel using differential electromagnetic analysis. We first focus on exploiting local side channels to isolate the behaviour of our targeted byte.... more

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FPGA Implementation of 8, 16 and 32 Bit LFSR with Maximum Length Feedback Polynomial Using VHDL

by Amit Rajput

2012

LFSR based PN Sequence Generator technique is used for various cryptography applications and for designing encoder, decoder in different communication channel. It is more important to test and verify by implementing on any hardware for... more

The bits in the LFSR state which influence the input are called taps. A maximum-length LFSR produces an m- sequence (i.e. it cycles through all possible 2” -1 states within the shift register except the state where all bits are zero), unless it contains all zeros, in which case it will never change. The sequence of numbers generated by this method is random. The period of the sequence is (2” - 1), where n is the number of shift registers used in the design.

The circuit diagram for 16-bit LFSR with maximum length polynomial is shown in Fig. 3. The timing simulation is shown in Fig. 6.a from 20 ns to 1310720 ns and also in Fig. 6.b which is a zooming view of Fig. 6.a. It shows starting simulation and simulation at the end of cycle after which the sequence starts repeating again. Figure 3. Circuit Diagram of 16- Bit LFSR with maximum length Feedback Polynomial X'* + X'4+ X84 X!'4+1

Figure 2. Circuit Diagram of 8- Bit LFSR with maximum length Feedback Polynomial X* + X° + X°+X*+1 ~The’ circuit diagram for 6 bit -LFSR with maximum length polynomial is shown in Fig. 2. The timing simulation is shown in Fig. 5 from 40 ns to 5140 ns. After this clock time the random output is repeating again.

The circuit diagram for 32-bit LFSR with maximum length polynomial is shown in Fig. 4. The timing simulation is shown in Fig. 7.a starting from 20 ns to 85899345920 ns (85.9 sec) and we can observe here the simulation is running for a long time to complete the sequence. In the Fig. 7.b a small zooming portion is shown and it can be observed the randomness behaviour for 32 bit LFSR from 30225 ns to 30500 ns. For 32 bit LFSR using Xilinx ISE 10.1 simulator, it is taking about 3 hour duration for simulating upto | sec time duration with 20 ns clock period. As the run length is very large which is 429,49,67,295 random states, so it is taking actual 85.9 sec to complete the sequence but practically simulate with ISE 10.1 is taking about 10-12 days. Figure 4. Circuit Diagram of 32- Bit LFSR for maximum length Feedback Polynomial X* + X” + X?+ X'+1

Figure 6.b. Timing Simulation waveform of 16-Bit LFSR (Zoom image at the starting of simulation & at the end of the cycle after which it starts repeating) Figure 6.a. Timing Simulation waveform of 16-Bit LFSR (20 ns to 1310720 ns = 1310.7 us): Total 65535 periods

Figure 5. Timing Simulation waveform of 8-Bit LFSR (40 ns to 5140 ns = 5100 ns): Total 255 periods

‘igure 7.a. Timing Simulation waveform of LFSR-32 Bit (20 ns to 85899345920 ns = 85.9 sec): Total 429,49,67,295 periods

Figure 7.b. Timing Simulation waveform of LFSR-32 Bit (Zooming view of Fig.7.a)

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FPGA Implementation of the Pixel Purity Index Algorithm for Remotely Sensed Hyperspectral Image Analysis

by David Valencia

2010, Eurasip Journal on Advances in Signal Processing

Hyperspectral imaging is a new emerging technology in remote sensing which generates hundreds of images, at different wavelength channels, for the same area on the surface of the Earth. Over the last years, many algorithms have been... more

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FPGA Implementation of an Adaptive Filter Robust to Impulsive Noise: Two Approaches

by Juan F. Guerrero

2011, IEEE Transactions on Industrial Electronics

Adaptive filters are used in a wide range of applications such as echo cancellation, noise cancellation, system identification, and prediction. Its hardware implementation becomes essential in many cases where real-time execution is... more

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A single-chip FPGA implementation of real-time adaptive background model

by Kofi Appiah

2005, Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005.

This paper demonstrates the use of a single-chip FPGA for the extraction of highly accurate background models in real-time. The models are based on 24-bit RGB values and 8-bit grayscale intensity values. Three background models are... more

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Implementing a Simple Continuous Speech Recognition System on an FPGA

by Antonio Alencar

2002

Speech recognition is a computationally demanding task, particularly the stage which uses Viterbi decoding for converting pre-processed speech data into words or sub-word units. We present an FPGA implementations of the decoder based on... more

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