Context Switching

Real-Time systems are becoming pervasive. In a Real-Time System the correctness of the system behavior depends not only on the logical results of the computations, but also on the physical instant at which these results are produced. A missed deadline in hard real-time systems is catastrophic and in soft real-time systems it can lead to a significant loss .This work talks about static and dynamic scheduling algorithms for real time task. The problem of real-time scheduling spans a broad spectrum of algorithms from simple uniprocessor to highly sophisticated multiprocessor scheduling algorithms which are priority driven and divided into three classes fixed priority, dynamic priority and hybrid priority. Finally conclusion shows that Instantaneous utilization factor scheduling Algorithm gives better result in uniprocessor scheduling algorithms and Modified Instantaneous utilization factor scheduling Algorithm gives better context switching, response time and CPU utilization as compared to previous scheduling algorithms.

Scheduling is a fundamental operating system function. Almost all computer resources are scheduled before use. All major CPU scheduling algorithms concentrates more on to maximize CPU utilization, throughput, waiting time and turnaround time. In particularly, the performance of round robin algorithm depends heavily on the size of the time quantum. To improve the performance of CPU and to minimize the overhead on the CPU, time quantum should be large with respect to the context switch time. Otherwise, context switching will be more. In this research paper, we propose a method to minimize the context switching and to break the fixed time quantum size in round robin scheduling algorithm using optimization techniques. Both results and calculations show that, our proposed method is more efficient than the existing round robin scheduling algorithm.

The concept of processes scheduling has had a major role since the advent of operating scheduling policies, the CPU plays a significant role in the computer system by transferring control between different processes and must work efficiently, the operating system performs a basic task, which is scheduling the processor for its efficient and optimized use. Scheduling the processor is one of the most important operational implemented through the operating system. Different algorithms for processor scheduling exist including the scheduling algorithm of priority. The priority number makes the algorithm effective. In this research, a proposed algorithm for scheduling the processor between processes was adopted using the KNAPSACK algorithm in order to eliminate the waiting state and starvation situation that occurs for low priority processes.

Scheduling is a fundamental operating system function. Almost all computer resources are scheduled before use. All major CPU
scheduling algorithms concentrates more on to maximize CPU utilization, throughput, waiting time and turnaround time. In
particularly, the performance of round robin algorithm depends heavily on the size of the time quantum. To improve the performance of CPU and to minimize the overhead on the CPU, time quantum should be large with respect to the context switch time. Otherwise, context switching will be more. In this research paper, we propose a method to minimize the context switching and to break the fixed time quantum size in round robin scheduling algorithm using optimization techniques. Both results and calculations show that, our proposed method is more efficient than the existing round robin scheduling algorithm.

This paper concerns programming methodologies commonly called "graphical dataflow programming" that are used extensively for signal processing and experimentally for other applications. In this paper, "graphical" means simply that the program is explicitly specified by a directed graph where the nodes represent computations and the arcs represent streams of data. The graphs are typically hierarchical, in that a node in a graph may represent another directed graph.

To cope with the increasing demand for higher computational power and flexibility, dynamically reconfigurable blocks become an important part inside a system-on-chip. Several methods have been proposed to incorporate their reconfiguration aspects in to a design flow. They all lack either an interface to commercially available and industrially used tools or are restricted to a single vendor or technology environment. Therefore a methodology for modeling of dynamically re-configurable blocks at the system-level using SystemC 2.0 is presented. The high-level model is based on a multi-context representation of the different functionalities that will be mapped on the re-configurable block during different run-time periods. By specifying the estimated times of context-switching and active-running in the selected functionality modes, the methodology allows to do true design space exploration at the system-level, without the need to map the design first to an actual technology implementation.

In present era, one of the most important resources of computer machine is CPU. With the increasing number of application, there exist a large number of processes in the computer system at the same time. Many processes in system simultaneously raise a challenging circumstance of managing the CPU in such a manner that the CPU utilization and processes execution gets optimal performance. The world is still waiting for most efficient algorithm which remains a challenging issue. In this manuscript, we have proposed a new algorithm Progressively Varying Response Ratio Priority a preemptive CPU scheduling algorithm based on the Priority Algorithm and Shortest Remaining Time First. In this scheduling algorithm, the priority is been calculated and the processes with high priority get CPU first or next. For new process, the priority of it becomes equal to inverse of burst time and for the old processes the priority calculation takes place as a ratio of waiting time and remaining burst time. The objective is to get all the processes executed with minimum average waiting time and no starvation. Experiment and comparison show that the VRRP outperforms other CPU scheduling algorithms. It gives better evaluation results in the form of scheduling criteria. We have used the deterministic model to compare the different algorithms.

Multiple-view visualizations are useful for finding patterns in complex data sets, but little research has been done on how they are used. We performed a controlled experiment to study cognitive strategies and context switching by using combination of visualizations and different task types as independent variables, and collecting qualitative and quantitative data. To collect the data paper-based tests, logging of participants' interactions, eyetracking, think-aloud techniques, and video recordings were used. Unlike suggestions in literature, our results show that when considering dual-view visualizations the time cost for context switching may not be significant, and similar visualizations may actually cause more interference.

This paper discusses the preliminary performance study of hybrid multithreaded execution model that combines software-controlled multithreaded system with hardware support for efficient context switching and threads scheduling. The hardware support for multithreading is augmented with a software thread scheduling technique called setscheduling, and their benefit to the overall performance is discussed. Set scheduling schedules multiple threads onto the hardware scheduler to minimize the software scheduling and context switching costs. An analytical model of the proposed multithreaded model is discussed and simulation results of processor utilization based on the proposed model are presented. Through simulation, we find that the hybrid multithreaded execution model results in high processor utilization than traditional softwarecontrolled multithreading.

Partial and dynamic reconfiguration provides a relevant new dimension to design efficient parallel embedded systems. However, due to the encasing complexity of such systems, ensuring the consistency and parallelism management at runtime is still a key challenge. So architecture models and design methodology are required to allow for efficient component reuse and hardware reconfiguration management.This paper presents a distributed persistence management model and its implementation for reconfigurable multiprocessor systems on dynamically reconfigurable circuits. The proposed approach is inspired from the well-known component based models used in software applications development. Our model is based on membranes wrapping the systems components. The objective is to improve design productivity and ensure consistency by managing context switching and storage using modular distributed hardware controllers. These membranes are distributed and optimized with the aim to design self-adaptive systems by allowing dynamic changes in parallelism degree and contexts migration. Simulation and synthesis results are given to show performances and effectiveness of our methodology.

Changing how the operating system handles interrupt processing and scheduling can greatly reduce the difference between worst-case and average-case message latencies, thus increasing a program's perfor ma nce. nvestigations that analyze the time an operating system takes to schedule, interrupt, and "context-switch" to another process or job have helped developers produce highly optimized and tuned operating systems that can provide more than 99% sustained processor use for 20

In present era, one of the most important resources of computer machine is CPU. With the increasing number of application, there exist a large number of processes in the computer system at the same time. Many processes in system simultaneously raise a challenging circumstance of managing the CPU in such a manner that the CPU utilization and processes execution gets optimal performance. The world is still waiting for most efficient algorithm which remains a challenging issue. In this manuscript, we have proposed a new algorithm Progressively Varying Response Ratio Priority a preemptive CPU scheduling algorithm based on the Priority Algorithm and Shortest Remaining Time First. In this scheduling algorithm, the priority is been calculated and the processes with high priority get CPU first or next. For new process, the priority of it becomes equal to inverse of burst time and for the old processes the priority calculation takes place as a ratio of waiting time and remaining burst time. The objective is to get all the processes executed with minimum average waiting time and no starvation. Experiment and comparison show that the VRRP outperforms other CPU scheduling algorithms. It gives better evaluation results in the form of scheduling criteria. We have used the deterministic model to compare the different algorithms.

To cope with the increasing demand for higher computational power and flexibility, dynamically reconfigurable blocks become an important part inside a system-on-chip. Several methods have been proposed to incorporate their reconfiguration aspects in to a design flow. They all lack either an interface to commercially available and industrially used tools or are restricted to a single vendor or technology environment. Therefore a methodology for modeling of dynamically re-configurable blocks at the system-level using SystemC 2.0 is presented. The high-level model is based on a multi-context representation of the different functionalities that will be mapped on the re-configurable block during different run-time periods. By specifying the estimated times of context-switching and active-running in the selected functionality modes, the methodology allows to do true design space exploration at the system-level, without the need to map the design first to an actual technology implementation.