Built in self test

FPGA chips have wide applications in nowadays digital systems. Because of fault prone nature of FPGA chips, testing of them is one of the major challenges for designers. Among various test methods, the Built-in Self-Test (BIST) based ones have shown good performance. In this paper, we presented a BIST-based approach to test LUTs as most vulnerable part of FPGA chip. The BIST-based approach is off-line and has been accomplished within two FPGA configurations. Each configurable logic block (CLB) can be tested independently and there is no handshaking among various CLBs' BIST cores. The proposed BIST architecture has been simulated in HSPICE based on 45-nm CMOS technology. Simulation results shown 100% coverage for single stuck at faults along with 19% area overhead due to additional BIST hardware and 25% increase in leakage power.

In this paper we study the use of pseudorandom test techniques for linear and nonlinear devices, in particular Micro Electro Mechanical Systems (MEMS). These test techniques lead to practical Built-In-Self-Test techniques (BIST). We will first present the pseudorandom test technique for Linear Time Invariant (LTI) systems. Next, we will illustrate and evaluate the application of these techniques for weakly nonlinear, purely nonlinear and strongly nonlinear devices.

In this paper we study the use of pseudorandom test techniques for linear and nonlinear devices, in particular Micro Electro Mechanical Systems (MEMS). These test techniques lead to practical Built-In-Self-Test techniques (BIST). We will first present the pseudorandom test technique for Linear Time Invariant (LTI) systems. Next, we will illustrate and evaluate the application of these techniques for weakly nonlinear, purely nonlinear and strongly nonlinear devices.

The goal of this contribution is to describe how a universal Turing machine was embedded into a hardware system in order to verify the computational universality of a novel architecture. This implementation was realized with a multicellular automaton inspired by the embryonic development of living organisms. In such an architecture, every artificial "cell" contains a complete copy of the description of the machine, a redundancy that allows the introduction of the properties of self-repair and self-replication. These properties were coupled with a modified version of the W-machine to realize a robust, self-replicating universal computer in actual hardware.

An efficient and modular architecture is used to implement Arithmetic Fourier Transform algorithm as a Built-in-Self Test structure to identify electromigration faults in FPGAs. Xilinx Virtex 5 FPGA, implemented in 65 nm fabrication process, is used to implement BIST and simulate the electromigration failure mechanisms. Fault signatures are developed for different interconnect FPGA resources and simulation results are presented. I.

System-on-chip (SOC) design methodology is becoming the trend in the IC industry. Integrating reusable cores from multiple sources is essential in SOC design, and different design-for-testability methodologies are usually required for testing different cores. Another issue is test integration. The purpose of this paper is to present a hierarchical test scheme for SOC with heterogeneous core test and test access methods. A hierarchical test manager (HTM) is proposed to generate the control signals for these cores, taking into account the IEEE P1500 Standard proposal. A standard memory BIST interface is also presented, linking the HTM and the memory BIST circuit. It can control the BIST circuit with the serial or parallel test access mechanism. The hierarchical test control scheme has low area and pin overhead, and high flexibility. An industrial case using this scheme has been designed, showing an area overhead of only about 0.63%.

System-on-chip (SOC) design methodology is becoming the trend in the IC industry. Integrating reusable cores from multiple sources is essential in SOC design, and different design-for-testability methodologies are usually required for testing different cores. Another issue is test integration. The purpose of this paper is to present a hierarchical test scheme for SOC with heterogeneous core test and test access methods. A hierarchical test manager (HTM) is proposed to generate the control signals for these cores, taking into account the IEEE P1500 Standard proposal. A standard memory BIST interface is also presented, linking the HTM and the memory BIST circuit. It can control the BIST circuit with the serial or parallel test access mechanism. The hierarchical test control scheme has low area and pin overhead, and high flexibility. An industrial case using this scheme has been designed, showing an area overhead of only about 0.63%.

Memory cores are usually the densest portion with the smallest feature size in system-on-chip (SOC) designs. The reliability of memory cores thus has heavy impact on the reliability of SOCs. Transparent test is one of useful technique for improving the reliability of memories during life time. This paper presents a systematic algorithm used for transforming a bit-oriented march test into a transparent word-oriented march test. The transformed transparent march test has shorter test complexity compared with that proposed in the previous works . For example, if a memory with 32-bit words is tested with March C , time complexity of the transparent word-oriented test transformed by the proposed scheme is only about 56% or 19% time complexity of the transparent word-oriented test converted by the scheme reported in or , respectively.

Intended Audience: Designers, researchers and test engineers interested in learning about the state-of-the-art in BIST methods and practices for complex systems-chips. With the emerging trend of designing core-based complex system-chips, Built-in Self-test (BIST) is becoming the solution of choice that provides testability reuse, IP protection, and facilitates silicon debug. In addition, it is a key enabler for mixing and matching self-testable cores from different sources onto a single chip. This tutorial covers both the basic methods and current practices for integrating BIST into cores, chips and systems. First it introduces the basic building blocks to act as BIST sources and sinks for test pattern generation and output data compaction respectively, and then it discusses their incorporation into the design flow of random logic cores and embedded memories for supporting BIST, diagnosis and even repair functions. The overall test integration at the chip level is also addressed in ...

Many Built-In Self Test pattern generators use Linear Feedback Shift Registers (LFSR) to generate test sequences. In this paper, we address the generation of deterministic pairs of patterns for delay faults testing with LFSRs. A new synthesis procedure for a n-size LFSR is given and guarantees that a deterministic set of n precomputed test pairs is embedded in the maximal length pseudo-random test sequence of the LFSR. Sufficient and necessary conditions for the synthesis of this pseudodeterministic LFSR are provided and show that at-speed delay faults testing becomes a reality without any additional cost for the LFSR. Moreover, since the theoretical properties of LFSRs are preserved, our method could be beneficially used in conjunction with any other technique proposed so far.

BIST is a viable approach to test today's digital systems. Constraints, such as power, noise, area overhead, and others, limit the possibilities of parallel BIST execution in complex VLSI devices. This paper presents a BIST scheduling process that takes into consideration such constraints, and introduces a new BIST control methodology, that implements the BIST schedule with a highly modular architecture. In fuct, due to the uniformity of interface, the BIST control elements are independent of the BIST scheme used in the embedded blocks of a device. This BIST control architecture can provide block level diagnostic information.

This paper addresses the problem of Multi-Chip Module (MCM) testing, and specifically testing assembled MCM performance. The presented solution is based-on self-test. It augments the conventional single-chip BIST approach, which is needed to produce known-good-dies, to a new multi-chip BIST solution. The multi-chip BIST puts the entire module in a self-test mode. This self-test mode not only provides detection of static and dynamic faults, but also identifies failed elements, i.e. bad dies or substrate. The multi-chip selftest scheme is based on a pseudo-random test approach and uses a multi-signature evaluation technique. The hardware design of multi-chip and single-chip self-test blocks are combined under a common architecture called the Dual BIST Architecture. The paper describes a set of design configurations to create Dual BIST Architecture. The presented BIST solution provides a reliable static and dynamic test at the module level as well as the bare die level.

Reconfigurable logic devices that are based on an FPGA substrate are gaining widespread acceptance. As such devices are used in many different configurations, manufacturers need to ensure that each potential configuration will not fail due to device defects. This flexibility leads to severely increased test time. We show how to use reconfigurability to speed up test and diagnosis times of individual FPGA blocks. We present a scheme to incorporate our test architecture, reducing diagnostic and test times of individual FPGA blocks. The test architecture includes added Feedback Shift Registers (FSRs) that change the circuit configuration during test. Algorithms are presented to produce test and diagnosis test sets with a minimized number of test configurations, along with the creation of an FSR that produces the test and diagnosis sets by dynamic reconfiguration of the device.

In this paper, we propose a built-in self-test (BIST) for the resistor array in an embedded analog configurable circuit (EACC) that is present in the Texas Instruments® MSP430 microcontrollers family. The EACC is formed also by an Operational Amplifier (OA) and interconnection resources. We focus in the resistor array test due to this section establishes the feedback path for the embedded OAs and set the gain value for the EACC closed-loop configurations. The test establishes, through very simple measurements, which combinations of the resistor ladder are available for the user by using only the resources embedded in the microcontroller. The experimental results show that the BIST proposed presents a very good repeatability in the measurements with very low dispersion, for one chip, for a sample of chips and under different temperature conditions. The error in the measurements, evaluated using a higher precision voltmeter, is also low. These results show that the BIST proposed is us...

High quality Built-In Self Test (BIST) needs to efficiently tackle the coverage of random-pattern-resistant (r.p.r) defects. Several techniques have been proposed to cover r.p.r faults at logic level, namely, weighted pseudo-random and mixed-mode. In mixed-mode test pattern generation (TPG) techniques, deterministic tests are added to pseudorandom vectors to detect r.p.r. faults. Recently, a RTL mixed-mode TPG technique has been proposed to cover r.p.r defects, the mask-based BIST technique. The purpose of this paper is to present mask-based BIST TPG improvements, namely in two areas: RTL estimation of the test length to be used for each mask, in order to reach high Defects Coverage (DC), and the identification of an optimum mask for each set of nested RTL conditions. Results are used to predict the number of customized vectors for each mask of one ITC'99 benchmark module.

With the rapid advancements in very large scale integration (VLSI) and
integrated circuit (IC) technology, the complexity of devices has escalated
significantly. Designing a VLSI chip is essential for scaling up the
capabilities of chips to meet the growing demands of modern applications,
like artificial intelligence (AI), IoT, and high-performance computing. Chip
testing and verification also emerges as crucial tasks to ensure optimal
device functionality. Testing verifies the integrity of a circuit’s gates and
connections, ensuring accurate operation. Throughout the chip’s design and
development life cycle, design, testing and verification composes a
substantial portion of the effort. AI and machine learning (ML) are used in
many different research domains to improve predicted accuracy, automate
difficult jobs, provide data-driven insights, and optimise workflows. This
study aims to showcase the vital role of AI/ML in reducing complexity in
VLSI chip design life cycle by automating test pattern generation and fault
detection, enhancing efficiency and accuracy, and significantly reducing the
time and resources needed for design verification and optimization.

The use of cross-correlation between power supply current and output voltage dynamic responses is presented as a methodology for improved mixed current /voltage testing of analogue and mixed-signal circuits. Results obtained from simulations are presented which show that better fault coverage and a simplification of test circuitry can be obtained, when compared with the results obtained from the direct observation of the individual signals. These advantages are important factors to develop viable new design for testability and buil-in self test techniques.

The use of cross-correlation between power supply current and output voltage dynamic responses is presented as a methodology for improved mixed current /voltage testing of analogue and mixed-signal circuits. Results obtained from simulations are presented which show that better fault coverage and a simplification of test circuitry can be obtained, when compared with the results obtained from the direct observation of the individual signals. These advantages are important factors to develop viable new design for testability and buil-in self test techniques.

One can find today system-on-chip devices comprising also radio-frequency blocks. These highly integrated circuits raise extraordinary challenges for testing, jeopardizing the low cost requirements associated often to these products. A built-in self test scheme for RF power amplifiers based on a polynomial fitting approach is proposed here, which takes advantage of the existing local oscillator, up-conversion mixer, and pre-driver, allowing for low area overhead and performance degradation. Simulation and experimental results for gain and linearity (1 dB compression and third order interception points) obtained with a GaAs distributed amplifier are presented which confirm the validity of the method. The BIST scheme proposed for implementing this method on-chip is then described, together with preliminary simulation results.

A pseudorandom pattern generator produces sequences similar to true random sequences. A variable length pseudo-random pattern generator (PRPG), which can be used as a pattern generator for various applications like built-in self-test (BIST) or cryptography, is proposed in this paper. Our work is based on a linear feedback shift register circuit platform. The proposed design can generate patterns corresponding to different characteristic polynomials of any given polynomial degree. These characteristic polynomials are integrated into the linear feedback shift register circuit by providing an option to select the feedback paths of any of these polynomials. This paper implements and evaluates the proposed design for primitive and non-primitive characteristic polynomials of degrees 3 to 15. The circuit generates output patterns of different periods based on user inputs. Compared to other pseudorandom pattern generator circuits, the proposed circuit can generate a large set of patterns and consumes less power. Adequate results from the experiments demonstrate the functionalities and performance of the proposed pattern generator from degrees 3 to 15. The proposed circuit generates pseudorandom patterns that can be used not only for built-in self-test but also for cryptography and wireless communication applications.

A novel built-in self test architecture for locally controlled cube-type N N multistage interconnection networks (MINs) is presented. First, a state-based pseudoexhaustive test procedure for this class of MINs is outlined. Then, a labelling algorithm on a binary n-cube is described which generates the necessary inputs for the tests. From the dependence graph of this algorithm a tree architecture is derived which results in a hardware overhead of O1= log N.

Recent safety standards set stringent requirements for the target fault coverage in embedded microprocessors, with the objective to guarantee robustness and functional safety of the critical electronic systems. This motivates the need for improving the quality of test generation for microprocessors. A new high-level implementationindependent test generation method for RISC processors is proposed. The set of instructions of the processor is partitioned into groups. For each group, a dedicated test template is created, to be used for generating two test programs, for testing the control and the data paths respectively. For testing the control part, a novel high-level control fault model is proposed. Using this model, a set of deterministic test data operands are generated for each instruction of the given group. The advantage of the high-level fault model is that it covers larger than SAF fault class including multiple fault coverage in the control part. For generating the data path test, pseudoexhaustive data operands are used. We investigated the feasibility of the approach and demonstrated high efficiency of the generated test programs for testing the execute module of the miniMIPS RISC processor.

Testing is very essential in ULSI (Ultra-Large-Scale Integration) designs to identify structural defects in the chip and to fix hard defects before shipping the defective manufactured chip to customers to avoid failures at site. Toggling activity in the design is the main reason for defects being local or latent between lower cells and metal layers and is popped up at different PVT conditions. Identification of these defects require testing process to ensure the chip being manufactured at desired specifications with reduced cost and time for testing. Also, toggling activity shows impact on pattern inflation, power, and testability aspects. In today's ULSI world, maintaining lower power in limelight of energy crisis has been a captious issue while keeping in pace with ever increasing complexity of transistor integration onto a single silicon substrate. As the chip density increases, power dissipation during testing mode doubles than the normal mode affecting the chip's durability, performance, cost, and reliability. It became critical for test engineers to minimize the test power leveraging the techniques of Design for Testability (DFT) to incorporate low power management of a SoC (System on Chip). Traditional DFT approaches uses structural scan-based testing to obtain testability metrics. In this paper, a novel LFSR architecture is proposed for power reduction in test mode by replacing the conventional scan approach. This architecture is designed and tested using cadence tools on ISCAS89 benchmarking circuits. Experimental results are compared for different parameters like coverage, pattern count, WSA (Weighted Switching Activity) and runtime to prove that LFSR (Linear shift feedback Register) driven design shows better results than the traditional scan structured procedure. Adopting the novel LFSR architecture, toggling activity is reduced by factor of ~1.34X with 4K pattern reduction running almost 1hr faster than traditional scan-based design. Test Power is reduced by ~45% and is found to be showcasing better results as complexity of design is increased. Hence, it is found to be ideal approach for industrial designs racing to obtain low power with reduced pattern count, lower cost and with shorter run time. This novel approach is more helpful for 2.5D and 3D designs.

PART I: THE THEORETICAL FOUNDATION CHAPTER 1: INTRODUCTION In this first chapter of the thesis, a short description of the research area will be outlined. Then the purpose of the research, the stated research questions, the objectives, and the scope and limitations will be presented. Thereafter the structure of the thesis will be described. CHAPTER 2: THEORETICAL FRAME OF REFERENCE In this chapter some theories with complementary perspectives upon maintenance and continuous improvement of complex and critical technical systems will be presented. Initially the concepts of failures, faults, and systems will be described. Thereafter, theories about Health Management, Quality Management, and Requirements Management will be outlined. Examples of some central definitions will also be presented. CHAPTER 3: RESEARCH DESIGN In this chapter some research options and performed choices for the design of the planned research will be discussed. Areas such as research purpose, perspective, and strategy will be presented and described. Aspects of data collection and analysis will also be briefly described. In addition to this, some aspects of reliability and validity will be discussed. Finally, a roadmap that summarises the performed design choices will be presented.

In context of the oscillation-based-test (OBT) technique, a simple and low-cost method of testing oscillators by comparison of finite segment of waveform with the ideal sine-wave is presented. The method is based on the subtraction of two sigma-delta modulated signals with the aid of a 1-bit subtractor that employs oversampling based noise-shaping. An up/down counter extracts the average of the bit stream that is used as a fault signature. The simulation results on the example of the Van der Pol oscillator show that the proposed fault signature is sensitive to the frequency and amplitude deviations and is able to detect non-linear oscillation as well.

This paper describes a new method of pseudoexhaustive test pattern generation suitable above all for circuits using random access scan (RAS). Two linear feedback shift registers (LFSR) are used to generate scan addresses and test patterns to be scanned into these addresses. It is shown that the suggested testing method gives better results than random testing. Index-Terms-Built-in self-test equipment, linear code, linear feedback shift register, pseudoexhaustive testing, random testing, scan design, simplex code, test generation.

Direct digital synthesis (DDS) technology is used to generate and modify high-quality waveforms in a broad range of applications in such diverse fields as medicine, industry, instrumentation, communications, and defense. This article provides an overview of the technology, describes its benefits and limitations, and takes a look at some application examples— and new products that make the technology more readily available.

This paper describes a simulation to predict the susceptibility of an advanced avionics control system to electrical transients resulting in logic errors, latched errors, error propagation, and digital upset. The system is based on a custom-designed microprocessor, and it incorporates fault-tolerant techniques. The system being tested and the method of performing the transient-injection experiment are described. Results for 2100 transient injections are analyzed and classified according to charge level, type of error, and location of injection. Logic errors Electrical transient Analog-digital simulation

This work presents the capacitive micromechanical accelerometer with a completely differential high-order switched capacitor sigma-delta modulator interface. Such modulation interface circuit generates one-bit output data using a third sigma-delta modulator low-noise front-end, doing away with the requirement for a second enhanced converter of resolution to encode the feedback route analog signal. A capacitive micromechanical sensor unit with just a greater quality factor has been specifically employed to give greater resolution. The closed-loop and electrical correction control are used to dampen the high-Q values to get the system's stability with high-order. This microelectromechanical system (MEMS) capacitive accelerometer was calibrated using a lookup table and Akima interpolation to find manufacturing flaws by recalculating voltage levels for the test electrodes. To determine the proper electrode voltages for fault compensation, COMSOL software simulates a number of defects upon that spring as well as the fingers of the sensor system. When it comes time for the feedback phase of a proof mass displacement correction, these values are subsequently placed in the lookup table.

With the advance of VLSI technology, the capacity and density of memories is rapidly growing. The yield improvement and testing issues have become the most critical challenges for memory manufacturing. Conventionally, redundancies are applied so that the faulty cells can be repairable. Redundancy analysis using external memory testers is becoming inefficient as the chip density continues to grow, especially for the system chip with large embedded memories. This paper presents three redundancy analysis algorithms which can be implemented on-chip. Among them, two are based on the local-bitmap idea: the local repair-most approach is efficient for a general spare architecture, and the local optimization approach has the best repair rate. The essential spare pivoting technique is proposed to reduce the control complexity. Furthermore, a simulator has been developed for evaluating the repair efficiency of different algorithms. It is also used for determining certain important parameters in redundancy design. The redundancy analysis circuit can easily be integrated with the built-in self-test circuit.

The present paper describes the CRTC and EuNICE-Test project actions and outcomes. The original idea was to build a long-lasting European Network for test engineering education using both test resource mutualisation and remote experiments. This objective is fully fulfilled and we have now, in Europe, five centers of competence able to deliver high-level and high-specialized training courses in the field of test engineering using a high-performing industrial ATE. All the centers propose training courses on digital testing, three of them propose mixed-signal trainings and three of them propose memory trainings. Taking into account the demand in test engineering, the network is planned to continue in a stand alone mode.

The main aspects of the design and test (D&T) of a reconfigurable architecture for the Data Acquisition Electronics (DAE) system of the Clear-PEM detector are presented in this paper. The application focuses medical imaging using a compact PEM (Positron Emission Mammography) detector with 12288 channels, targeting high sensitivity and spatial resolution. The DAE system processes data frames that come from a front-end (FE) electronics, identifies the relevant data and transfers it to a PC for image processing. The design is supported in a novel D&T methodology, in which hierarchy, modularity and parallelism are extensively exploited to improve design and testability features. Parameterization has also been used to improve design flexibility. Nominal frequency is 100 MHz. The DAE must respond to a data acquisition rate of 1 million relevant events (coincidences) per second, under a total single photon background rate in the detector of 10 MHz. Trigger and data acquisition logic is implemented in eight 4-million, one 2-million and one 1-million gate FPGAs (Xilinx Virtex II). Functional Built-In Self Test (BIST) and Debug features are incorporated in the design to allow on-board FPGA testing and self-testing during product lifetime.

Test power requirements for complex components are becoming stringent. The purpose of this paper is to reuse a recently proposed RT (Register Transfer) Level test preparation methodology to drive innovative Low-Energy (LE)/Low-Power (LP) BIST solutions for digital SoC (System on a Chip) embedded cores. RTL test generation is carried out through the definition of a reduced set of partially specified input vectors (masks), leading to a high correlation between multiple detection of RTL faults and single detection of likely physical defects. The methodology is referred as masked-based BIST, or m-BIST. BIST quality is evaluated considering three attributes: test effectiveness (TE), test length (TL) and test power (TP). LE BIST sessions are defined as short test sequences leading to high values of RT-level IFMB metrics and low-level Defects Coverage (DC). The energy and power of the BIST sessions, with and without mask forcing, is computed. It is shown that, by forcing vectors with the RTL masks, short BIST sessions, with low energy and with a comparable (or smaller) average power consumption, as compared to pseudo-random test, are derived. The usefulness of the methodology is ascertained using the VeriDOS simulation environment and modules of the CMUDSP and TORCH ITC'99 benchmark circuits.

A survey on techniques to perform VLSI Testing efficiently using BIST explores various methodologies to enhance
Very Large-Scale Integration (VLSI) testing through Built-In-Self-Test (BIST) mechanism. The research delves into
the significance of BIST controllers, such as the utilization of Low-Feedback Shift Registers (LFSR) for efficient
testing. It also addresses the critical challenge of reducing test power in low-power VLSI circuits, emphasizing the
need for innovative techniques to mitigate excessive power consumption during testing processes. Furthermore, the
paper highlights the evolution of BIST applications in VLSI and System-on-Chip (SoC) testing, showcasing the
growing importance of BIST for fault detection in modern electronic devices. Additionally, the study focuses on the
design of Logic BIST structures, emphasizing the role of components like Test Pattern Generators, Response
Analyzers, and Comparators in enhancing chip testing efficiency.

Purpose -This paper aims to address the various issues of board-level (off-chip) interconnects testing. A new algorithm based on the boundary scan architecture is developed to test off-chip interconnect faults. The proposed algorithm can easily diagnose which two interconnects are shorted. Design/methodology/approach -The problems in board-level interconnects testing are not simple. A new algorithm is developed to rectify some of the problems in existing algorithms. The proposed algorithm to test board-level interconnect faults is implemented using Verilog on Modelsim software. The output response of each shorting between different wires of different nodes is different, which is the basis of fault detection by the proposed algorithm. The test vectors are generated by the test pattern generator and these test vectors are different for different nodes. This work implements built in self test using boundary scan technique. Findings -The dominant-1 (wired-OR, denoted as WOR), dominant-0 (wired-AND, denoted as WAND) and stuck-at faults are tested using the proposed algorithm. The proposed algorithm is also compared with the several algorithms in the literature, i.e. modified counting, walking one's algorithm and others. This paper's results are found to be better than the existing algorithms. Research limitations/implications -The limitation of the proposed algorithm is that, at any time, the faults on any seven nodes can be tested to avoid aliasing. So, the groups are formed out of total nodes, in a multiple of seven to carry out the testing of faults. Practical implications -The proposed algorithm is free from the problems of syndromes and utilizes a smaller number of test vectors. Originality/value -Various existing algorithms namely modified counting, walking one's algorithm and others are discussed. A new algorithm is developed which can easily detect board-level dominant-1 (WOR), dominant-0 (WAND) and stuck-at faults. The proposed algorithm is completely free from aliasing and confounding syndromes.

In this paper, we propose a built-in self-test (BIST) for the resistor array in an embedded analog configurable circuit (EACC) that is present in the Texas Instruments® MSP430 microcontrollers family. The EACC is formed also by an Operational Amplifier (OA) and interconnection resources. We focus in the resistor array test due to this section establishes the feedback path for the embedded OAs and set the gain value for the EACC closed-loop configurations. The test establishes, through very simple measurements, which combinations of the resistor ladder are available for the user by using only the resources embedded in the microcontroller. The experimental results show that the BIST proposed presents a very good repeatability in the measurements with very low dispersion, for one chip, for a sample of chips and under different temperature conditions. The error in the measurements, evaluated using a higher precision voltmeter, is also low. These results show that the BIST proposed is us...

This paper proposes the application of the analog configurability test (ACT) approach for an embedded analog configurable circuit, composed by operational amplifiers and interconnection resources that are embedded in the MSP430xG461x microcontrollers family, with the aim of verifying its mode programmability. This test strategy is particularly useful for applications involving in-field circuit reconfiguration, and require reliability and safe operation characteristics. The approach minimizes the cost in hardware overhead by employing only the hardware and software resources of the microcontroller. An embedded test routine sequentially programs selected module configurations, sets the test stimulus, acquires data from the internal ADC, and performs required calculations to determine the gain of the block. The test approach is experimentally evaluated using an embedded-system based real application board. Our experimental results show very good repeatability, with very low errors. The...

The main aspects of the design and test (D&T) of a reconfigurable architecture for the Data Acquisition Electronics (DAE) system of the Clear-PEM detector are presented in this paper. The application focuses medical imaging using a compact PEM (Positron Emission Mammography) detector with 12288 channels, targeting high sensitivity and spatial resolution. The DAE system processes data frames that come from a front-end (FE) electronics, identifies the relevant data and transfers it to a PC for image processing. The design is supported in a novel D&T methodology, in which hierarchy, modularity and parallelism are extensively exploited to improve design and testability features. Parameterization has also been used to improve design flexibility. Nominal frequency is 100 MHz. The DAE must respond to a data acquisition rate of 1 million relevant events (coincidences) per second, under a total single photon background rate in the detector of 10 MHz. Trigger and data acquisition logic is implemented in eight 4-million, one 2-million and one 1-million gate FPGAs (Xilinx Virtex II). Functional Built-In Self Test (BIST) and Debug features are incorporated in the design to allow on-board FPGA testing and self-testing during product lifetime.

Today’s deep submicron technologies allow the integration of multiple memories on a single chip. Embedded memories are one of the most universal cores, which occupy around 90% area in system-on-chip (SoC) architecture due to the demand for high data storage. So, the embedded memory test process has become an essential part of the SoC development phase. Some of the March algorithms including recently developed March SS algorithms though provide architectural flexibility to run different algorithms on the similar hardware architecture. This flexibility is a trade-off with logic overhead, number of March operations and computational delay. The MBSIR methodology presented in this paper is based on the totally selfchecking logic using Berger code. This architecture supports the fault diagnosis as well as on-fly self-repair mechanism. The experimental results show that the complexity of the replacement of the faulty core and its impact on performance degradation may be traded-off by a mar...

A testable EXOR-Sum-of-Products (ESOP) circuit realization and a simple, universal test set which detects all single stuck-at faults in the internal lines and the primary inputs/outputs of the realization are given. Since ESOP is the most general form of AND-EXOR representations, our realization and test set are more versatile than those described by other researchers for the restricted GRM, FPRM, and PPRM forms of AND-EXOR circuits. Our circuit realization requires only two extra inputs for controllability and one extra output for observability. The cardinality of our test set for an input circuit is (+6). For Built-in Self Test (BIST) applications, we show that our test set can be generated internally as easily as a pseudo-random pattern, and that it provides 100% single stuck-at fault coverage. In addition, our test set requires a much shorter test cycle than a comparable pseudo-exhaustive or pseudo-random test set.

In this paper the built in self test for analog to digital converter of programmable system on chip is implemented. The new approach for finding out static errors in ADC is based on time. This approach uses ramp signal and determines time difference between two successive samples, which in turn leads to finding out the static error like DNL, INL of the ADC. The proposed work uses PSoC devices which enable us to design a complete mixed signal system with few off chip components To test static parameter of ADC on chip components are used. Ramp signal is generated by using on chip IDAC of PSoC. The BIST circuit implemented here calculate DNL, INL based on timing i.e. a new approach to calculate DNL, INL is implemented and verified.

A Verilog HDL-based fault simulator for testing embedded cores-based synchronous sequential circuits is proposed in the paper to detect single stuck-line faults The simulator emulates a typical BIST (built-in self-testing) environment with test pattern generator that sends its outputs to a CUT (circuit under test) and the output streams from the CUT are fed into a response data analyzer. The fault simulator is suitable for testing sequential circuits described in Verilog HDL. The subject paper describes in detail the architecture and applications of the fault simulator along with the models of sequential elements used. Results on some simulation experiments on ISCAS 89 full-scan sequential benchmark circuits are also provided.