Unification of partitioning, placement and floorplanning

Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC, 2003

In this paper we study the large-scale mixed-size placement problem where there is a significant size variation between big and small placeable objects (the ratio can be as large as 10,000). We develop a multi-level optimization algorithm, MPG-MS, for this problem which can efficiently handle both large-scale designs and large size variations. Compared with the recently published work [1] on large-scale mixed macro and standard cell placement benchmarks for wirelength minimization, our method can achieve 13% wirelength reduction on average with comparable runtime.

2006

Abstract Large macro blocks, predesigned datapaths, embedded memories, and analog blocks are increasingly used in application-specific integrated circuit (ASIC) designs. However, robust algorithms for large-scale placement of such designs have only recently been considered in the literature. Large macros can be handled by traditional floorplanning, but are harder to account for in min-cut and analytical placement.

Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific, 2003

In traditional floorplanners, area minimization is an important issue. Due to the recent advances in VLSI technology, the number of transistors in a design and their switching speeds are increasing rapidly. This results in the increasing importance of interconnect delay and routability of a circuit. We should consider interconnect planning and buffer planning as soon as possible. In this paper, we propose a method to reduce interconnect cost of a floorplan by searching alternative packings. We found that if a floorplan F contains some rectangular supermodules, we can rearrange the blocks in the supermodule to obtain a new floorplan with the same area as F but possibly with a smaller interconnect cost. Experimental results show that we can always reduce the interconnect cost of a floorplan without any penalty in area and runtime by using this method.

Proceedings of the 2002 international symposium on Physical design, 2002

While a number of recent works address large-scale standard-cell placement, they typically assume that all macros are fixed. Floorplanning techniques are very good at handling macros, but do not scale to hundreds of thousands of placeable objects. Therefore we combine floorplanning techniques with placement techniques in a design flow that solves the more general placement problem. Our work shows how to place macros consistently with large numbers of small standard cells. Our techniques can also be used to guide circuit designers who prefer to place macros by hand. The proposed flow relies on an arbitrary black-box standardcell placer to obtain an initial placement and then removes possible overlaps using a fixed-outline floorplanner. This results in valid placements for macros, which are considered fixed. Remaining standard cells are then placed by another call to the standardcell placer. Empirical evaluation on ibm benchmarks shows, in most cases, wirelength improvements of 10%-50% compared to Cadence QPlace, as well as runtime improvements.

Journal of Parallel and Distributed Computing, 1999

Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a computeintensive process, and as a result several research efforts have been undertaken to parallelize this algorithm. Parallel placement is most needed for very large circuits. Since these circuits do not fi t in memory, the traditional approach has been to partition and place individual modules. This causes a hit in placement quality in terms of area and wirelength. Our algorithm is circuit partitioned and can handle arbitrary large circuits on cluster-of-workstations type parallel machines such as the Intel Paragon and IBM SP-2. Most previous work in parallel placement has minimized just area and wirelength, but with current deep submicron designs, minimizing wirelength delay is most important. As a result the algorithm discussed in this paper also supports timing driven placement for partitioned circuits. The algorithm, called mpiPLACE, has been tested on several large industry benchmarks on a variety of parallel architectures.

2008

The technique of using balanced min-cut partitioning in placement was presented by Breuer in 1977 [7]. Such min-cut placers use scalable and extensible divide-and-conquer algorithmic framework and tend to produce routable placements [9]. Recent work offers extensions to block placement and large-scale mixed-size placement [15, 18, 31], and robust incremental placement [33].

Proceedings of the …, 2004

Many current designs contain a large number of standard cells intermixed with larger macro blocks. The range of size in these "mixed block" designs complicates the placement process considerably; traditional methods produce results that are far from satisfactory.

IEEE Journal of Solid-State Circuits, 1995

This paper presents a new approach toward performance-driven placement of analog integrated circuits. The freedom in placing the devices is used to control the layout-induced performance degradation within the margins imposed by the designer's specifications. This guarantees that the resulting layout will meet all specifications by construction.

1993

This paper describes a new schematlc-driven floorplanning algorithm. This algorithm improves on initial constructive placement iteratively not only by selecting the best orientation for the module cells , but also optlmising the floorplan topology through local transformations applied to the polar graph representation of the floorplan. The transformations are easy to implement, efficient to perform and produce compact layout.

Proceedings of the …, 2002

A new approach to the interconnect-driven floorplanning problem that integrates bus planning with floorplanning is presented. The integrated floorplanner is intended for bus-based designs. Each bus consists of a large number of wires. The floorplanner ensures routability by generating the exact location and shape of interconnects (above and between the circuit blocks) and optimizes the timing. Experiments with MCNC benchmarks clearly show the superiority of integrated floorplanning over the classical floorplan-analyze-and-then-refloorplan approach. Our floorplans are routable, meet all timing constraints, and are on average 12-13% smaller in area as compared to the traditional floorplanning algorithms.