A Novel Processor for Artificial Intelligence Acceleration

2008

This article proposes using symbolic learning methods based on multiple-valued (MV) logic and implemented in reconfigurable hardware. In the part one, we discussed why symbolic learning is useful in some applications, such as robotics. We presented an architecture for a massively parallel reconfigurable processor that enables speeding up logic operations performed in learning hardware. Rather than learning using evolutionary and neural network methods in hardware, our approach uses combinatorial synthesis methods developed in the framework of the logic synthesis approach in digital-circuitdesign automation. In contrast to previous

R. Phani Vidyadhar & J. Selva Kumar, 2013

Coarse-Grained Reconfigurable Architecture (CGRAs) requires many Processing Elements (PEs) and a configuration cache memory unit for reconfiguration of its PE array. This structure is meant for high performance and flexibility, it consumes significant power. The applications of Field Programmable Gate Arrays (FPGAs) are multi fold in real-time systems. They have several advantages over Application Specific Integrated Circuits (ASICs), but CGRAs applications have been restricted to integer arithmetic, since existing CGRAs supports only integer arithmetic or logical applications. In this work proposed here main objective is to design existing 4 x 4 Processing Elements (PEs) array for integer arithmetic. The main idea of this paper is to explore the advantages of FPGA in real world by mapping applications that supports integer arithmetic and the mapping can be done by using the Fast Heuristic algorithm to get the required results. The focus is to do synthesis of both existing 4 x 4 PE array design and modified 4 x 4 PE array design for speed, power and delay using Xilinx and Xpower analysis tool. This design uses HDL, Modelsim simulator and Xilinx9.1i Synthesizer targeted on Vertex platform. Heuristic approach using Quantum- inspired Evolutionary Algorithm (QEA) used here supports for integer arithmetic applications. The proposed Modified Processing Elements proves to be 20 - 25% reduction in delay and power dissipation, when compared to the existing PEs of 4 x 4 elements. The proposed PEs might lead a significant reduction in power and delay when used in multimedia application, with maximum throughput.

FPGAs for Custom Computing Machines, …, 1997

This thesis describes a processor architecture called OneChip, which combines a fixed logic processor core and reconfigurable logic resources. Using the variable components of this architecture, the performance of speed-critical applications can be improved by customizing

2007 International Conference on Field-Programmable Technology, 2007

This paper presents a method to implement a reconfigurable logic array on an FPGA. To design circuits with 2valued k-input LUTs, 2 k-valued logic is introduced. Standard benchmark functions as well as symmetric functions are efficiently implemented by a logic array with 2 k-valued variables. Number of products and number of bits to represent functions by the expressions with 2 k-valued variables for k = 1, 2, 3, 4, and 5 are compared. Both sumof-products expressions and EXOR sum-of-products expressions of 2 k-valued logic significantly reduces needed FPGA resources, when 2 ≤ k ≤ 5. Experimental results for benchmark functions and symmetric functions are shown. Implementations of arrays with 16-valued variables on Xilinx and Altera FPGAs are also shown.

2017

In this paper, a hardware implementation of artificial neural networks and implementation of logic gates using artificial neural networks on Field Programmable Gate Arrays (FPGA) is presented. A digital system architecture for feed forward multilayer neural network is realized. The parallel structure of a neural network makes it potentially fast for the computation of certain tasks that makes a neural network well suited for implementation in VLSI technology. Then logic gates are implemented using Feed Forward Neural Network. FPGA has been used to reduce the unit neuron hardware by designing the activation function inside the neuron without the need of lookup tables. The whole design is realized using Verilog HDL and is implemented on FPGA.

Euromicro Symposium on Digital System Design, 2003. Proceedings., 2003

This paper suggests a novel architecture for a reconfigurable accelerator for computations over discrete vectors. The number of executed operations is limited but they can arbitrarily be chosen from a practically unlimited set of feasible operations. The software model and hardware implementations of the accelerator are discussed in detail.

International Journal of Reconfigurable Computing, 2010

To accelerate the execution of an application, repetitive logic and arithmetic computation tasks may be mapped to reconfigurable hardware, since dedicated hardware can deliver much higher speeds than those of a general-purpose processor. However, this is only feasible if the run-time reconfiguration of new tasks is fast enough, so as not to delay application execution. Currently, this is opposed by architectural constraints intrinsic to current Field-Programmable Logic Array (FPGA) architectures. Despite all new features exhibited by current FPGAs, architecturally they are still largely based on general-purpose architectures that are inadequate for the demands of reconfigurable computing. Large configuration file sizes and poor hardware and software support for partial and dynamic reconfiguration limits the acceleration that reconfigurable computing may bring to applications. The objective of this work is the identification of the architectural limitations exhibited by current FPGAs...

Lecture Notes in Computer Science, 1993

With the arrival of large Field Programmable Gate Arrays (FPGAs) it is possible to build an entire computer using only FPGA and memory. In this paper we share some experience from building a highly parallel computer using this concept. Even if today's FPGAs are of considerable size, each processor must be relatively simple if a highly parallel computer is to be constructed from them. Based on our experience of other parallel computers and thorough studies of the intended applications, we think it is possible to build very powerful and efficient computers using bit-serial processing elements with SIMD (Single Instruction stream, Multiple Data streams) control. A major benefit of using FPGAs is the fact that different architectural variations can easily be tested and evaluated on real applications. In the primary application area, which is artificial neural networks, the gains of extensions like bit-serial multipliers or counters can quickly be found. A concrete implementation of a processor array, using Xilinx FPGAs, is described in this paper. To get efficient usage and high performance with the FPGA circuits signal flow plays an important role. As the current implementation of the Xilinx EDA software does not support that design issue, the signal flow design has to be made by hand. The processing elements are simple and regular which makes it easy to implement them with the XACT Editor. This gives high performance, up to 40-50 MHz.

International Journal of Reconfigurable Computing, 2008