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1989, Applied Optics
Cascadable optically nonlinear arrays of logic devices interconnected with space invariant optical components are proposed for the core memory of a digital computer. Access time to any portion of the memory is O(log 2 N) gate delays for logic devices with fan-in and fan-out of two, where Nis the size of the memory in bits. The cost of the design in switching components is near minimal for a random access memory (RAM) between one and two components per stored bit of information depending on the size of the memory. The design is extensible to very large RAMs, although parallel access memory is preferred to a RAM configuration for large memories due to the parallel access capability of the optical design.
International Journal of Optics and Applications, 2011
This paper demonstrates an all-optical 1-bit Random Access Memory (RAM) with massive use of nonlinear material. All-optical switching mechanism is exploiting here to realize the all-optical 1-bit RAM. The all-optical switch by a composite slab of linear medium (LM) and non-linear medium (NLM) is the building block of our proposed 1-bit RAM circuit. An all-optical clocked D flip flop is the main storing element of the RAM. These circuits are simple and all-optical in nature. It can also gear up to the highest capability of optical performance in high-speed all-optical data storing, computing and communicating system.
IEEE Journal of Selected Topics in Quantum Electronics, 2000
All-optical digital circuits based on loop memories are demonstrated. These circuits are a variable optical buffer, an optical random access memory, an optical shift register, and an optical linear feedback shift register. Buffers are employed in network nodes to solve the contentions without loosing information. Shift registers are used for error detection and correction techniques. Linear feedback shift registers are employed for generation of pseudo-random bit sequences, data scrambling, and encryption/decryption of information in secure communication systems. Since the role of optical processing is gradually increasing within the communication systems, the possibility to store information directly in the optical domain can lead to a systems simplification and to a performance improvement. In order to make the schemes suitable for practical applications, optical integration is necessary. The use of semiconductor optical amplifier as gain element into the memory loop allows all the proposed schemes to be integrated.
Applied Optics, 1988
Regular free-space interconnects such as the perfect shuffle and banyan provided by beam splitters, lenses, and mirrors connect optical logic gates arranged in 2-D arrays. An algorithmic design technique transforms arbitrary logic equations into a near-optimal depth circuit. Analysis shows that an arbitrary interconnect makes little or no improvement in circuit depth and can even reduce throughput. Gate count is normally higher with a regular interconnect, and we show cost bounds. We conclude that regularly interconnected circuits will have a higher gate count compared with arbitrarily interconnected circuits using the design techniques presented here and that regular free-space interconnects are comparable with arbitrary interconnects in terms of circuit depth and are preferred to arbitrary interconnects for maximizing throughput. 1. Introduction All-optical digital computers have the potential for high speed, cheap communications, and massive parallelism. Logic gates based on nonlinear dielectric constants were investigated theoretically in the early 1960s by von Neumann. 1 In the last few years optical bistable devices, 2 ' 3 nonlinear Fabry-Perots, 4 ' 5 and hybrid electrooptic devices 6 have been studied experimentally. These results encourage development of architectures suitable for optics. Historically, two architectural approaches have dominated the field. One approach uses integrated optics to interconnect optical logic devices. A system designed with this approach is architecturally similar to a conventional computer, with logic gates connected in arbitrary configurations. This similarity means that an optical computer designed with this approach is worth building only if it can be made more cheaply or more powerful. An alternative approach makes use of 2-D arrays of devices interconnected in free space. This approach uses space-variant interconnects (provided by holograms) or space-invariant regular interconnects (provided by beam splitters). We prefer the space-invariant regular interconnect approach for simplicity, extensibility, and high throughput. To take advan
Journal of the Optical Society of Korea, 2008
Applied Optics, 2009
A semiconductor optical amplifier-based all-optical read-only memory (ROM) is successfully demonstrated through simulations using a one-level simplification method optimized for optical logic circuits. Design details are presented, and advantages are discussed in comparison with an all-optical ROMemploying decoder. We demonstrate that eight characters can be stored at each address in the American Standard Code for Information Interchange.
Applied Sciences, 2017
Electronic Content Addressable Memories (CAM) implement Address Look-Up (AL) table functionalities of network routers; however, they typically operate in the MHz regime, turning AL into a critical network bottleneck. In this communication, we demonstrate the first steps towards developing optical CAM alternatives to enable a re-engineering of AL memories. Firstly, we report on the photonic integration of Semiconductor Optical Amplifier-Mach Zehnder Interferometer (SOA-MZI)-based optical Flip-Flop and Random Access Memories on a monolithic InP platform, capable of storing the binary prefix-address data-bits and the outgoing port information for next hop routing, respectively. Subsequently the first optical Binary CAM cell (B-CAM) is experimentally demonstrated, comprising an InP Flip-Flop and a SOA-MZI Exclusive OR (XOR) gate for fast search operations through an XOR-based bit comparison, yielding an error-free 10 Gb/s operation. This is later extended via physical layer simulations in an optical Ternary-CAM (T-CAM) cell and a 4-bit Matchline (ML) configuration, supporting a third state of the "logical X" value towards wildcard bits of network subnet masks. The proposed functional CAM and Random Access Memories (RAM) sub-circuits may facilitate light-based Address Look-Up tables supporting search operations at 10 Gb/s and beyond, paving the way towards minimizing the disparity with the frantic optical transmission linerates, and fast re-configurability through multiple simultaneous Wavelength Division Multiplexed (WDM) memory access requests.
2000
The Optically Programmable Gate Array (OPGA), an optical version of a conventional FPGA, benefits from a direct parallel interface between an optical memory and a logic circuit. The OPGA utilizes a holographic memory accessed by an array of VCSELs to program its logic. An active pixel sensor array incorporated into the OPGA chip makes it possible to optically address the logic in a very short time allowing for rapid dynamic reconfiguration. Combining spatial and shift multiplexing to store the configuration pages in the memory, the OPGA module can be made compact. The reconfiguration capability of the OPGA can be applied to solve more efficiently problems in pattern recognition and database search.
Pramana
A logical NAND and NOR gate was simulated using bistability behavior in nonlinear medium of Fabry-Perot cavity based on the inverse trend of output intensity vs. input intensity. The gate was optimised relative to different cavity parameters, sharp edges between the ON and OFF modes and threshold switching intensity. The real and imaginary parts of the refractive index of the nonlinear medium were utilised to compute numerical results. Finally, gate speed was calculated to be 9.2 Gb/s.
Applied Optics, 1995
We propose a multilayer associative memory with a winner-take-all operation on the inner product between an input and stored exemplars. The winner-take-all operation is performed by a unit-step operation with an adaptive-threshold strategy. We show that the multilayer-associative-memory unit-step operation with an adaptive-threshold strategy has a high noise immunity and a large storage capacity, and it is also capable of extending to a gray-level associative memory with a phaserepresentation technique. A hybrid optical implementation with a proof-of-concept experiment is also provided.
Optics in Computing 2000, 2000
The Optically Programmable Gate Array (OPGA), an optical version of a conventional FPGA, benefits from a direct parallel interface between an optical memory and a logic circuit. The OPGA utilizes a holographic memory accessed by an array of VCSELs to program its logic. An active pixel sensor array incorporated into the OPGA chip makes it possible to optically address the logic in a very short time allowing for rapid dynamic reconfiguration. Combining spatial and shift multiplexing to store the configuration pages in the memory, the OPGA module can be made compact. The reconfiguration capability of the OPGA can be applied to solve more efficiently problems in pattern recognition and database search.
Applied Optics, 1986
The results of investigations into the feasibility of incorporating optically bistable elements into an optical processor are presented. Two forms of bistable device, etalons of InSb and interference filters containing ZnSe, have been used in the first experimental demonstrations of digital all-optical circuits. It is shown that cw optical bias beams may be used to hold logic gates sufficiently close to their switch point that the available signal gain allows one to realize indefinitely extensible optical logic. The results of such experiments are presented and the implications they have on the field of optical computing are discussed. It is concluded that parallel arrays can give significantly high rates of digital operations.
IEEE/OSA Journal of Lightwave Technology, 2009
This paper describes the fiber optic loop buffer-based switch in which contention is resolved in the time and wavelength domain. In the loop buffer, tunable wavelength converters (TWCs) are placed in place of semiconductor optical amplifiers (SOAs) as in conventional loop buffer-based architectures. The placement of TWCs inside the buffer facilitate simultaneous read/write operation and dynamic re-allocation of wavelengths and improves the switch performance significantly. It is a well known fact that the re-circulating type buffer structure suffers from circulation limit (maximum revolutions that data can take in the buffer) due to the loss and noise accumulation in the switch. This paper presents a mathematical model to obtain a maximum number of allowed circulations of the data in loop buffer-based switch architecture. This model is derived for various configurations (transparent, noisy, and regenerative) of TWC. The detrimental effect of crosstalk and four wave mixing are shown, and the affect of dispersion on the maximum allowed bit rate is discussed. The minimum length of the loop is also evaluated. Finally, the bounded region is shown (bit rate versus number of wavelengths graph) where memory can work efficiently.
ICENCO'2010 - 2010 International Computer Engineering Conference: Expanding Information Society Frontiers, 2011
We experimentally demonstrate the accuracy of an all-optical S-R latch and an optical S-R flip-flop based on hybrid integrated Mach-Zehnder Interferometers, with Semiconductor Optical Amplifier in each arm (MZI-SOA). The performance of both bistable devices will be studied and compared in terms of extinction ratio and switching times.
The concurrent-read concurrent-write (CRCW) model of shared memory for parallel computation is considered unimplementable in practice, due to limitations of electronic technology. But optical technology opens new possibilities that may overcome these limitations. An optical CRCW memory can be designed, in principle, based on the following ideas. First, optical free-space interconnections eliminate the need for shared switches that su er from contention. Second, practically unlimited fan-in on detectors allows for concurrent writing without serialization. And third, retrore ective optical elements that reverse the propagation of beams of light implement concurrent reads without address decoding and sequential service. It should be noted, however, that the required technology is still immature, and much work is needed before a practical design is reached.
IEEE Journal of Selected Topics in Quantum Electronics, 2000
We demonstrate analytical frequency-domain transfer function expressions for an optical random access memory (RAM) cell that employs two SOA-based ON/OFF switches and two coupled SOA-MZI gates forming an optical flip-flop. Our theoretical model relies on first-order perturbation theory approximations applied for the first time to coupled optical switching structures, resulting to an optical RAM cell frequency response that allows for a qualitative and quantitative analysis of optical RAM memory speed and performance characteristics and their dependence on certain RAM cell device parameters. We show that the transfer function of an optical RAM cell and its incorporated flip-flop device exhibits periodic resonance frequencies resembling the behavior of optical ring resonator configurations. Its free spectral range is mainly dictated by the length of the waveguide that enables the coupling of the two SOA-MZI gates, yielding this coupling length as the dominant memory speed determining factor. The obtained results are in close agreement with experimental observations, demonstrating that optimized RAM cell designs with waveguide coupling lengths lower than 5 mm can enable RAM operation at memory speeds well beyond 40 GHz.
An all-optical flip-flop memory with separate set and reset inputs is presented. The flipflop is formed from two coupled polarization switches that are operated by utilizing the nonlinear polarization rotation in semiconductor optical amplifiers. The concept of the system is explained and experimental results are presented, demonstrating that a contrast ratio of over 20 dB between output states and a switching power of less than −3 dBm can be obtained. The all-optical flip-flop can be utilized in all-optical packet switches.
IEEE Photonics Technology Letters, 2000
A multistate optical memory based on serially interconnected lasers is presented. We show that only one of the lasers can lase at a time, thus, the state of the optical memory is determined by the wavelength of the dominant laser. The light from the dominant laser suppresses its neighboring lasers through gain saturation, but still receives amplification by the active element of the suppressed lasers, compensating for coupling losses. This light passes through each of the successive lasers, simultaneously suppressing and being amplified. By this mechanism, all other lasers are suppressed. A five-state optical memory based on this concept is experimentally demonstrated. The contrast ratio between different states is over 30 dB. Dynamic flip-flop operation based on two different all-optical switching methods is also demonstrated.
An all-optical memory with three states is presented. The optical memory is realized from three-coupled identical nonlinear polarization switches. The state of the optical memory is determined by the wavelength of the memory's output light. In each state, only one wavelength is dominant. The concept is explained and experimental results are presented that demonstrate that a contrast ratio of over 20 dB and a switching power of around 8 dBm can be obtained. This concept can be extended for an all-optical memory with a large number of states, which is crucial to realize 1×N all-optical packet switches.
Optics Communications, 1992
The various possibilities of optically interconnecting 16 × 16-data arrays by shuffle patterns are presented and analysed. The pattern analysis is based on evaluating the skew of each particular path of the shuffle interconnections. Geometric quantities of interest (deflection angle, path length of spatial and frequency pattern) are derived. The switch preserving transformation of 2D shuffle interstage patterns into their equivalent 1D shuffles and vice versa, the way a 1D shuffle overlaps into a 2D shuffle in the 3D physical space, is presented. The costs of these different interconnection schemes are evaluated and the results are compared. (The applied cost measure is the total length of the interconnections.) For example, the interconnection of 256 data has the least costs if the arrays are interconnected by a 4D shuffle.
Optoelectronic Interconnects VI, 1999
In this paper we introduce a micro-optical architecture that uses meso-scopic diffractive optical elements ( DOEs) as three dimensional interconnects in a memory system for high level instruction level parallelism (ILP) processors. By using meso-scopic DOEs we can reduce the scale of integration to the VLSI scale, i.e., the micron scale, achieve submicron alignment tolerance, improve reliability due to monolithic integration, facilitate integration into the current manufacturing infrastructure, and offer the ability for higher bandwidth and high interconnect densities. To this the end we are developing the component technologies needed to realize this system. In this paper we present our work in the development of a theoretical and experimental framework for the design and characterization of meso-scopic DOEs, preliminary experimental results of meso-scopic beam splitters, and a large scale demonstration of the ILP memory system.
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