A Parallel Evolutionary Algorithm for Circuit Partitioning

Computational Optimization and Applications, 2002

As general-purpose parallel computers are increasingly being used to speed up different VLSI applications, the development of parallel algorithms for circuit testing, logic minimization and simulation, HDL-based synthesis, etc. is currently a field of increasing research activity. This paper describes a circuit partitioning algorithm which mixes Simulated Annealing (SA) and Tabu Search (TS) heuristics. The goal of such an algorithm is to obtain a balanced distribution of the target circuit among the processors of the multicomputer allowing a parallel CAD application for Test Pattern Generation to provide good efficiency. The results obtained indicate that the proposed algorithm outperforms both a pure Simulated Annealing and a Tabu Search. Moreover, the usefulness of the algorithm in providing a balanced workload distribution is demonstrated by the efficiency results obtained by a topological partitioning parallel test-pattern generator in which the proposed algorithm has been included. An extented algorithm that works with general graphs to compare our approach with other state of the art algorithms has been also included.

ijcee.org

In this paper multiway circuit partitioning of circuits using Genetic Algorithms has been attempted. Due to the random search, inherent parallelism, and robustness of genetic algorithms, the solution of a circuit partitioning problem is global optimum. Results obtained show the versatility of the proposed method in solving NP hard problems like circuit partitioning. Results obtained show an improvement over the results of UCLA Branch and Bound partitioner [27]. Information of the circuit has been given in accordance with circuit netlist files used in ISPD'98 circuit benchmark suite.

Circuit partitioning is the first and the most important step in the designing of VLSI circuits. Owing to the rapidly increasing size of the designs, partitioning tools are becoming more important for the future. The partitioning algorithms are of two types, namely, constructive algorithms and iterative algorithms. In constructive algorithms, partition sets are formed with the help of algorithms; whereas, in case of iterative algorithms, new improved partition sets are formed at each iteration stepwith the modified netlist. A variety of heuristic algorithms have been developed to solve the problem of mincut which is NP-complete. With the main objective of minimizing the cutsize, numerous algorithms have been proposed for circuit partition which includes genetic and evolutionary algorithms, probability-based algorithms, clustering algorithms, and nature-based heuristics. The main intention of this paper is to provide a concise review of the VLSI CAD algorithms adopted for designing VLSI circuits. From the numerous partitioning methods available in the literature, a subjective selection has been made.

IJCA Proceedings on National …, 2012

Circuit partitioning problem is a well known NP hard problem. The potential of Genetic Algorithm has been used to solve many computationally intensive problems (NP hard problems) because existing conventional methods are unable to perform the required breakthrough in terms of complexity, time and cost. The presented work deals with the problem of partitioning of a circuit using Genetic Algorithm. The program inputs the adjacency matrix, generates graph of the circuit and partitions the circuit based on crossover operator. The program produces a set of vertices that are highly connected to each other but highly disconnected from the other partitions.

Future Generation Computer Systems, 1998

In this paper simulated annealing and genetic algorithms are applied to the graph partitioning problem. These techniques mimic processes in statistical mechanics and biology, respectively, and are the most popular meta-heuristics or general-purpose optimization strategies. A hybrid algorithm for circuit partitioning, which uses tabu search to improve the simulated annealing meta-heuristics, is also proposed and compared with pure tabu search and simulated annealing algorithms, and also with a genetic algorithm. The solutions obtained are compared and evaluated by including the hybrid partitioning algorithm in a parallel test generator which is used to determine the test patterns for the circuits of the frequently used ISCAS benchmark set.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1998

A genetic algorithm for partitioning a hypergraph into two disjoint graphs of minimum ratio cut is presented. As the Fiduccia-Mattheyses graph partitioning heuristic turns out to be not effective when used in the context of a hybrid genetic algorithm, we propose a modification of the Fiduccia-Mattheyses heuristic for more effective and faster space search by introducing a number of novel features. We also provide a preprocessing heuristic for genetic encoding designed solely for hypergraphs which helps genetic algorithms exploit clustering information of input graphs. Supporting combinatorial arguments for the new preprocessing heuristic are also provided. Experimental results on industrial benchmarks circuits showed visible improvement over recently published algorithms with a lower growth rate of running time.

International Journal of …, 2005

In recent years there has been a great interest in accelerating time consuming algorithms that solve large combinatorial optimization problems [1]. The advent of high density field programmable gate arrays in combination with efficient synthesis tools have enabled the production of custom machines for such difficult problems. Genetic Algorithms (GAs) [13] are robust techniques based on natural selection that can be used to solve a wide range of problems, including circuit partitioning. Although, a GA can provide very good solutions for such problems the amount of computations and iterations required for this method is enormous. As a result, software implementations of GA can become extremely slow for large circuit partitioning problems. In this paper, an architecture for implementing GAs on a Field Programmable Gate Array (FPGA) is presented. The architecture employs a combination of pipelining and parallelization to achieve substantial speedups. The GA accelerator proposed in this paper achieves more than 100× improvement in processing speed over its counterpart software implementation.

Numerical Methods and Applications, 2019

In this paper parallel and hybrid metaheuristics for graph partitioning are compared taking into account their efficiency in terms of a cost function and computation time. Seventeen methods developed on the basis of evolutionary algorithm, simulated annealing and tabu search are implemented and tested against graph instances computed on the basis of queen graphs from DIMACS repository and a class of random R-MAT graphs. These graphs are supposed to model a class of digital circuits being subject of decomposition into a given number of modules. In partitioning process several additional constraints have to be satisfied in order to enable composition of original circuits from subcircuits by means of VLSI/FPGA modules.

Functional decomposition is a process of splitting a complex circuit into smaller sub-circuits. This paper deals with the problem of determining the set of best free and bound variables (variable partitioning problem) for disjoint (disjoint serial) decomposition, such that the decomposed circuits are smaller in size and its truth table representation have maximal don't cares. A novel pruned breadth first search (PBFS/IPBFS) approach is proposed to determine the set of good variable partitions with minimal time and computational complexity. The heuristics proposed minimize the size of the sub-functions. The proposed approach has been successfully implemented and test with MCNC and Espresso benchmarks.

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004

When designing a circuit, it may be too large to fit on a single layer of a chip, on a single chip, or on a single board. Regardless of the design level, the same objectives remain. Normally, it is desirable to minimize the number of layers, chips, or boards, along with minimizing the delay. Additional constraints, such as the number of interconnections and power consumption, must often be considered. We have developed two k-way bounded partitioning algorithms; one is evolutionary-based, while the other is a hierarchical graph center-based approach. The algorithms are implemented and compared with known partitioning algorithms. Since VLSI circuits can be naturally modeled by graphs, experiments were conducted by partitioning graphs from various graph families against both simulated and real-world partitioning criteria. A direct result of this research is a high-level abstract graph-partitioning model. This model allows one to specify mathematical evaluation metrics and control parameters, permitting inter-domain comparison of algorithms and allowing one to identify the particular scenarios they are best applicable to.