High-throughput LDPC decoders

International journal of engineering and technology, 2018

This article, deals with efficient trellis inbuilt decoding architecture for non-binary Linear Density Parity Check (LDPC) codes. In this decoder, a bidirectional recursion is embedded to enhance the layered scheduling and decoding latency, which in turn is used to minimize the number of iterations compared to existing techniques. Consequently, it is necessary to increase the throughput for improving the efficiency of the system. In addition, a compression technique is implemented for reducing the requirements of memory and the area. Trellis based decoder was used to reinforce the check node processing. The proposed decoder for LDPC codes yields high throughput when compared to other similar decoders presented in preceding works. The designed architecture was implemented using Cadence Virtuoso software. This decoder provides a throughput of about 39.21 Mb/s at clock frequency of 190MHz.

2006

A high throughput pipelined LDPC decoder that supports multiple code rates and codeword sizes is proposed. In or- der to increase memory throughput, irregular block struc- tured parity-check matrices are designed with the constrai nt of equally distributed odd and even nonzero block-columns in each horizontal layer for the pre-determined set of code rates. The designed decoder achieves a data

Performance Comparison of Turbo coder and low-density parity check codes, 2021

This paper investigates the two powerful forward error correction techniques, Turbo codes and LDPC codes. The different code parameters such as code rate, decoding iterations, and block length are considered under AWGN channel. The strengths and performance hindrance facts of both the coding techniques been summarized.

Proceedings of the 2002 international symposium on Low power electronics and design - ISLPED '02, 2002

Iterative decoding of low-density parity check codes (LDPC) using the message-passing algorithm have proved to be extraordinarily effective compared to conventional maximumlikelihood decoding. However, the lack of any structural regularity in these essentially random codes is a major challenge for building a practical low-power LDPC decoder. In this paper, we jointly design the code and the decoder to induce the structural regularity needed for a reduced-complexity parallel decoder architecture. This interconnect-driven code design approach eliminates the need for a complex interconnection network while still retaining the algorithmic performance promised by random codes. Moreover, we propose a new approach for computing reliability metrics based on the BCJR algorithm that reduces the message switching activity in the decoder compared to existing approaches. Simulations show that the proposed approach results in power savings of up to 85.64% over conventional implementations. Categories and Subject Descriptors B.7.1 [Types and Design Styles]: VLSI; E.4 [Coding and Information Theory]: Error control codes However, in order to achieve desired power and throughputs for current applications (e.g., > lMbps in 3G wireless systems, > lGbps in magnetic recording systems), fully parallel and pipelined iterative decoder architectures are needed. Compared to turbo codes, LDPC codes enjoy a significant advantage in terms of computational complexity and are known to have a large amount of inherent parallelism [3]. However, the randomness of LDPC codes results in stringent memory requirements that amount to an order of magnitude increase in complexity compared to those for turbo codes. A direct approach to implementing a parallel decoder architecture would be to allocate, for each node or cluster of nodes in the graph defining the LDPC code, a function unit for computing the reliability messages, and employ an interconnection network to route messages between function nodes (see Fig.1). A major problem with this approach is that the interconnection networks require complex wiring to perform global routing of messages and hence must be deeply pipelined (e.g., bidirectional multilayered networks in [4] and 4096-input multiplexers per function unit in [5]). Moreover, the randomness in the pattern of communicating messages leads to routing and congestion problems on the networks which require extensive buffering to resolve.

In this paper, a reduced-complexity, scalable implementation of LDPC decoder is presented. The decoder architecture in this paper is an improved version of . The new architecture makes the implementation of multiple code rates, multiple block sizes and multiple standards LDPC decoder very straightforward. As an example, we implemented a parameterized decoder that supports the LDPC code in IEEE 802.16e standard, which requires code rates of 1/2, 2/3 and 3/4, with block sizes varying from 576 to 2304. The decoder is synthesized with Texas Instruments' 90 nm ASIC process technology, with a target operation frequency of 100 MHz, 15 decoding iterations, the maximum data rate is up to 256 Mbps.

IEEE Journal of Solid-State Circuits, 2002

A 1024-b, rate-1/2, soft decision low-density paritycheck (LDPC) code decoder has been implemented that matches the coding gain of equivalent turbo codes. The decoder features a parallel architecture that supports a maximum throughput of 1 Gb/s while performing 64 decoder iterations. The parallel architecture enables rapid convergence in the decoding algorithm to be translated into low decoder switching activity resulting in a power dissipation of only 690 mW from a 1.5-V supply.

The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology, 2005

A new parameterized-core-based design methodology targeted forprograinniable decoders for low-density parity-check (LDPC) codes is proposed. The inethodology solves the two major drawbacks of excessive memory overhead and complex on-chip interconnect typical of existing decoder implementations which limit the scalability, degrade the error-correction capability, and restrict the domain of application of LDPC codes. Diverse memory and interconnect optimizations are pcrfotined at the code-design, decoding algorithm, decoder architecture, and physical layout levels, with the following features: 1) Architecture-aware (AA)-LDPC code design with embedded structural features that significantly reduce interconnect complexity, 2) faster and memory-etficient turbo-decoding algorithm for LDPC codes, 3) programmable architecture having distributed memory, parallel message processing units, and dynamiclscalable transport networks for routing messages, and 4) a parameterized macro-cell layout library implernenting the main components of the architecture with scaling parameters that enable low-level transistor sizing and power-rail scaling forpowerdelay-area optimization. A 14mm2 programmable decoder core for a rate-f, Icngtti 2048 AA-LDPC code generated using the proposed methodology is presented, which delivers B throuphwt of I. 6 G b~s at 125MHz and consumes 760mW of power.

IEEE Transactions on Circuits and Systems I: Regular Papers, 2010

A low-complexity message-passing algorithm, called Split-Row Threshold, is used to implement low-density parity-check (LDPC) decoders with reduced layout routing congestion. Five LDPC decoders that are compatible with the 10GBASE-T standard are implemented using MinSum Normalized and MinSum Split-Row Threshold algorithms. All decoders are built using a standard cell design flow and include all steps through the generation of GDS II layout. An = 16 decoder achieves improvements in area, throughput, and energy efficiency of 4.1 times, 3.3 times, and 4.8 times, respectively, compared to a MinSum Normalized implementation. Postlayout results show that a fully parallel = 16 decoder in 65-nm CMOS operates at 195 MHz at 1.3 V with an average throughput of 92.8 Gbits/s with early termination enabled. Low-power operation at 0.7 V gives a worst case throughput of 6.5 Gbits/s-just above the 10GBASE-T requirement-and an estimated average power of 62 mW, resulting in 9.5 pJ/bit. At 0.7 V with early termination enabled, the throughput is 16.6 Gbits/s, and the energy is 3.7 pJ/bit, which is 5.8 lower than the previously reported lowest energy per bit. The decoder area is 4.84 mm 2 with a final postlayout area utilization of 97%. Index Terms-Full parallel, high throughput, low-density parity check (LDPC), low power, message passing, min sum, nanometer, 10GBASE-T, 65-nm CMOS, 802.3an. I. INTRODUCTION S TARTING in the 1990s, much work was done to enhance error-correction codes to where communication over noisy channels was possible near the Shannon limit. Defined by sparse random graphs and using probability-based message-passing algorithms, low-density parity-check (LDPC) codes [1] became popular for their error-correction and near-channel-capacity performances. At first, neglected since its discovery [2], advances in VLSI have given LDPC a recent revival [3]-[6]. LDPC has relatively low error floors, as well as better error performance with large code lengths, and as a result, they have been adopted as the forward error-correction method for many recent standards, such as digital video broadcasting via satellite (DVB-S2) [7], the WiMAX standard for microwave communications (802.16e) [8], the G.hn/G.9960 standard for wired home networking [9], and the 10GBASE-T standard for 10-Gbit Ethernet (802.3an) [10]. While there has been much Manuscript

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

This paper introduces a new approach to costeffective, high-throughput hardware designs for Low Density Parity Check (LDPC) decoders. The proposed approach, called Non-Surjective Finite Alphabet Iterative Decoders (NS-FAIDs), exploits the robustness of message-passing LDPC decoders to inaccuracies in the calculation of exchanged messages, and it is shown to provide a unified framework for several designs previously proposed in the literature. NS-FAIDs are optimized by density evolution for regular and irregular LDPC codes, and are shown to provide different trade-offs between hardware complexity and decoding performance. Two hardware architectures targeting high-throughput applications are also proposed, integrating both Min-Sum (MS) and NS-FAID decoding kernels. ASIC post synthesis implementation results on 65nm CMOS technology show that NS-FAIDs yield significant improvements in the throughput to area ratio, by up to 58.75% with respect to the MS decoder, with even better or only slightly degraded error correction performance.

IEEE Journal of Solid-State Circuits, 2006

A 14.3-mm 2 code-programmable and code-rate tunable decoder chip for 2048-bit low-density parity-check (LDPC) codes is presented. The chip implements the turbo-decoding message-passing (TDMP) algorithm for architecture-aware (AA-)LDPC codes which has a faster convergence rate and hence a throughput advantage over the standard decoding algorithm. It employs a reduced complexity message computation mechanism free of lookup tables, and features a programmable network for message interleaving based on the code structure. The chip decodes any mix of 2048-bit rate-1/2 (3,6)-regular AA-LDPC codes in standard mode by programming the network, and attains a throughput of 640 Mb/s at 125 MHz for 10 TDMP-decoding iterations. In augmented mode, the code rate can be tuned up to 14/16 in steps of 1/16 by augmenting the code. The chip is fabricated in 0.18-m six-metal-layer CMOS technology, operates at a peak clock frequency of 125 MHz at 1.8 V (nominal), and dissipates an average power of 787 mW. Index Terms-Architecture-aware low-density parity-check (AA-LDPC) codes, iterative decoders, LDPC codes, turbodecoding message-passing (TDMP) algorithm, VLSI decoder architectures.