Jitter and phase noise in ring oscillators

2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015

The jitter and the phase noise of ring oscillators utilizing subthreshold source-coupled logic (STSCL) style are analyzed in this paper. Closed-form equations are derived to predict the jitter and phase noise caused by white and flicker noise. Measurement results of a test chip fabricated in a standard CMOS 90 nm technology are presented to validate these expressions. The performed analysis shows that jitter in STSCLbased ring oscillator is independent of technology parameters, as opposed to its CMOS counterparts that depend on supply voltage and parameters of technology. Based on measured results, noise on current control line can dominate the total jitter of the oscillator. Design guidelines are proposed to limit the jitter effect of ring oscillators using STSCL logic. The proposed STSCLbased ring oscillator achieves an average RMS jitter as low as 0.24 % of the oscillation period at a 1.08 MHz/μA energy efficiency, which demonstrates its suitability for ultra-low-power applications.

This thesis describes a methodology for analyzing and predicting jitter (phase noise) in ring oscillators. Due to their high operating frequency and ease of integration, use of rings in jitter sensitive applications is becoming more common. One example is in data communication, where a ring is used as the voltage controlled oscillator (VCO) in a phaselocked loop (PLL). Despite the wide use of ring oscillators, their jitter performance has been poorly understood. The first step in developing this methodology is a technique for relating various measures of jitter in PLLs. The technique establishes correspondence among time and frequency domain measures of jitter with the PLL loop open or closed. Results are given when this time/frequency technique is applied to jitter measurements from an existing PLL.

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143)

An analysis of the phase noise in differential and singleended ring oscillators using a time-variant model is presented. An expression for the RMS value of the impulse sensitivity function (ISF) is derived. A closed-form equation for phase noise of ring oscillators is calculated and a lower limit on the phase noise of ring oscillators is shown. Phase noise measurements of oscillators running up to 5.5GHz are shown to be in good agreement with the theory.

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017

Voltage noise is the main source of dynamic variability in integrated circuits and a major concern for the design of Power Delivery Networks (PDNs). Ring Oscillators Clocks (ROCs) have been proposed as an alternative to mitigate the negative effects of voltage noise as technology scales down and power density increases. However, their effectiveness highly depends on the design parameters of the PDN, power consumption patterns of the system and spatial locality of the ROCs within the clock domains. This paper analyzes the impact of the PDN parameters and ROC location on the robustness to voltage noise. The capability of reacting instantaneously to unpredictable voltage droops makes ROCs an attractive solution, which allows to reduce the amount of decoupling capacitance without downgrading performance. Tolerance to voltage noise and related benefits can be increased by using multiple ROCs and reducing the size of the clock domains. The analysis shows that up to 83% of the margins for voltage noise and up to 27% of the leakage power can be reduced by using local ROCs.

This project deals with the design and performance analysis of a ring oscillator using CMOS 180 nm technology process in Cadence virtuoso environment. The design of optimal Analog and Mixed Signal (AMS) very large scale integrated circuits (VLSI) is a challenging task for the integrated circuit(IC)designer. A Ring Oscillator is an active device which is made up of odd number of NOT gates and whose output oscillates between two voltage levels representing high and low. There are a number of challenges ahead while designing the CMOS Ring Oscillator which are delay, noise and glitches. CMOS is the technology of choice for many applications, CMOS oscillators with low power, phase noise and timing jitter are highly desired. In this project, we have designed a CMOS ring oscillator with nine stages. The researchers were unable to reduce the phase noise in ring oscillators substantially with nine stages. We have successfully reduced the phase noise to -6.4kdBc/Hz at 2GHz centre frequency of oscillation.

IEEE Access

We describe in this paper an improved ring voltage-controlled oscillator (VCO) showing a reduced phase noise while allowing an extended frequency tuning range. The phase noise improvement is obtained through the minimized contribution of tuning line noise while maintaining a rail-to-rail swing. The proposed VCO features a linear tuning characteristic yielding a constant gain over a wide range of operating frequencies. An analytical model is extracted resulting in closed-form expressions for the VCO phase noise. Employing the analytical expressions, the contributed noise and phase noise limitations are fully addressed, and all the effective factors are investigated. The VCO prototype was fabricated in a 0.35 µm CMOS process. It consumes 0.903 mW from a 3.3 V supply when running at its maximum oscillation frequency of 9.37 MHz. The measured VCO phase noise is-147.57 dBc/Hz at 1 MHz offset from the 9.37 MHz oscillation frequency, and the circuit occupies a silicon area of 0.005 mm 2. A state-variable Matlab model of a time-based sensor interface has been developed including the impact of phase noise nonideality. The system-level simulations demonstrate that the PLL-based sensor interface exploiting the proposed VCO characteristics can achieve a 88.43 dB signal-to-noise ratio over a 1-kHz bandwidth. 14 15 INDEX TERMS Sensor interface, ring oscillators, voltage-controlled oscillator, phase noise, linear characteristics. I. INTRODUCTION 16 The voltage-controlled oscillator (VCO) is a critical circuit in 17 modern analog and mixed-signal integrated system designs 18 such as phase-locked loops (PLLs), clock/data recovery, 19 frequency modulation/demodulation, on-chip clock distri-20 bution, and synchronizing circuits [1], [2], [3], [4]. Over 21 the past decades, the semiconductor industry has been 22 directed towards smaller technologies that are especially 23 effective for digital circuits while raising some difficulties 24 in designing analog systems [5], [6]. Supply voltage reduc-25 tion, weak intrinsic transistor properties (e.g., lower gain and 26 devices' mismatch), large power and chip area result in poor 27 48 ring structures, LC resonant configuration, or relaxation 49 circuits [15], [16], [17]. LC-VCOs exhibit better phase 50 noise performance owing to the high Q resonator. However, 51 besides the limited tuning range of these structures, adding 52 high-performance bulky passive devices (such as inductors) 53 to a CMOS process leads to chip complexity, and area and 54 cost inefficiency [15]. On the contrary, ring VCOs are a 55 popular alternatives in scaled CMOS technologies since they 56 offer a wide tuning range, less die area, straightforward 57 integrated design, multi-phase output capability, and good 58 power performance [18]. Consequently, a ring-type VCO is 59 a promising approach for voltage-to-time conversion, fre-60 quency translation, and generating required periodic signals 61 for timing in digital circuits that are widely used in industrial 62 platforms. 63 However, nonlinear performance and poor phase noise are 64 the key issues in ring VCOs. For instance, the nonlinear 65 nature of voltage-to-time conversion provokes a linearity 66 issue in a time-domain comparator, and the VCO phase noise 67 has a great impact on its resolution [8], [21]. Besides, the 68 performance of VCO-based ADCs is severely distortion lim-69 ited by VCO gain variation (tuning nonlinearity) that causes 70 an inter-stage gain error [22]. Moreover, in an open-loop 71 VCO-based sensor interface shown in Fig. 1(a), the VCO's 72 nonlinearity leads to the appearance of harmonic spurs in 73 the output spectrum and limits the overall system signal-74 to-noise ratio (SNR) [19], [23]. To tackle this issue, the 75 closed-loop interface architecture depicted in Fig. 1(b) is 76 usually employed [20]. Although the VCO in a loop ensures 77 higher linearity, the operating frequency range is narrowed, 78 each cell, the long metal lines, in physical implementation, 439 that act as antennas for the transient noise of the oscillator 440 can be avoided. In addition, the mismatch between delay cells 441 was reduced by allowing a proper physical layout design and 442 adopting layout matching techniques. This further improves 443 the jitter and phase noise performance of the implemented 444 VCO. Meanwhile, by forming a guard ring layer around the 445 VCO design, the output signals have been protected from 446 coupling to the underlying substrate noises. The power supply 447 noise is also reduced due to the use of on-chip linear bypass 448 capacitors within the free chip area.

2016

In this work, a new ring voltage controlled oscillator with a two cross coupled load PMOS transistors is proposed. The proposed method preserves the maximum frequency of the VCO unaffected which leads to improvement in phase noise and the power consumption of VCO oscillators. The proposed ring oscillator implemented in 0.18μm CMOS shows the worse phase noise of -108 dBc/Hz at 10MHz offset, tuning range of 140.7%, while dissipating a maximum power consumption of 9 mW from 1.8 V supply. Keywords— Ring oscillators, VCO, tuning range, phase noise, cross coupled PMOS transistors.

This paper presents a study of phase noise in two inductorless CMOS oscillators. First-order analysis of a linear oscillatory system leads to a noise shaping function and a new definition of Q. A linear model of CMOS ring oscillators is used to calculate their phase noise, and three phase noise phenomena, namely, additive noise, high-frequency multiplicative noise, and low-frequency multiplicative noise, are identified and formulated. Based on the same concepts, a CMOS relaxation oscillator is also analyzed. Issues and techniques related to simulation of noise in the time domain are described, and two prototypes fabricated in a 0.5-m CMOS technology are used to investigate the accuracy of the theoretical predictions. Compared with the measured results, the calculated phase noise values of a 2-GHz ring oscillator and a 900-MHz relaxation oscillator at 5 MHz offset have an error of approximately 4 dB.

2020 European Conference on Circuit Theory and Design (ECCTD)

The immunity of jitter with respect to supply voltage is one of the desirable characteristics of digitally controlled oscillators (DCO) for clocking applications. This paper presents a design of such an oscillator with a high frequency resolution and small area in 28 nm technology. In order to reduce the dependence of the oscillator frequency on its voltage supply, differential amplifiers are used as inverters (delay cells) and a bias circuit with a stable voltage output is employed to bias the oscillator. From post-layout simulations, this DCO achieves a dynamic range from 1.13 to 1.54 GHz with the use of differential delay cells, the variation of the output frequency is less than 4.5% over all the frequency range, for VDD variation of 10%. The frequency control has 9.2 bits, giving an average frequency step of 722 kHz. This DCO achieves a phase noise of-74 dBc/Hz@1MHz or an jitter equivalence of 2.3 ps. The maximal power consumption of this DCO at maximum frequency is 840 µW, which is a low figure comparing to the state-of-the-art implementation with typical power of sub-milliwatts for the similar frequency range. Index Terms-All-Digital Phase Locked Loop (ADPLL), Digitally controlled oscillator (DCO), differential inverter ring