Online algorithms for packet scheduling and buffer management

2010 48th Annual Allerton Conference on Communication, Control, and Computing (Allerton), 2010

Internet traffic has increased at a very fast pace in recent years. The traffic demand requires that future packet switching systems should be able to switch packets in a very short time, i.e., just a few nanoseconds. Algorithms with lower computation complexity are more desirable for this high-speed switching design. Among the existing algorithms that can achieve 100% throughut for input-queued switches for any admissible Bernoulli traffic, ALGO3 [1] and EMHW [2] have the lowest computation complexity, which is O(logN), where N is the number of ports in the switch. In this paper, we propose a randomized scheduling algorithm, which can also stabilize the system for any admissible traffic that satisfies the strong law of large number. The algorithm has a complexity of O(1). Since the complexity does not increase with the size of a switch, the algorithm is highly scalable and a good choice for future high-speed switch designs. We also show that the algorithm can be implemented in a distributed way by using a low-rate control channel. Simulation results show that the algorithm can provide a good delay performance as compared to algorithms with higher computation complexity.

Computers, Materials & Continua, 2022

The high-performance computing paradigm needs high-speed switching fabrics to meet the heavy traffic generated by their applications. These switching fabrics are efficiently driven by the deployed scheduling algorithms. In this paper, we proposed two scheduling algorithms for input queued switches whose operations are based on ranking procedures. At first, we proposed a Simple 2-Bit (S2B) scheme which uses binary ranking procedure and queue size for scheduling the packets. Here, the Virtual Output Queue (VOQ) set with maximum number of empty queues receives higher rank than other VOQ's. Through simulation, we showed S2B has better throughput performance than Highest Ranking First (HRF) arbitration under uniform, and non-uniform traffic patterns. To further improve the throughput-delay performance, an Enhanced 2-Bit (E2B) approach is proposed. This approach adopts an integer representation for rank, which is the number of empty queues in a VOQ set. The simulation result shows E2B outperforms S2B and HRF scheduling algorithms with maximum throughput-delay performance. Furthermore, the algorithms are simulated under hotspot traffic and E2B proves to be more efficient.

Computer Communications, 2005

This paper addresses scheduling and memory management in input queued switches having finite buffer with the objective of improving the performance in terms of throughput and average delay. Most of the prior works on scheduling related to input queued switches assume infinite buffer space. In practice, buffer space being a finite resource, special memory management scheme becomes essential. Maximum weighted matching (MWM) algorithm, which is known to be the optimal in terms of throughput for infinite buffer case turns out to be sub optimal in the presence of memory limitations. We introduce a buffer management scheme called iSMM (Integrated Scheduling and Memory Management) that can be employed jointly with any deterministic iterative scheduling algorithm. We applied iSMM over iSLIP, a popular scheduling algorithm, and study its effect under various input traffic conditions. Simulation results indicate iSMM to perform better than iSLIP and MWM both in terms of throughput and delay especially under non-uniform traffic.

Theoretical Computer Science, 2008

Many applications need to solve the deadline guaranteed packet scheduling problem. However, it is a very difficult problem if three or more deadlines are present in a set of packets to be scheduled. The traditional approach to dealing with this problem is to use EDF (Earliest Deadline First) or similar methods. Recently, a non-EDF based algorithm was proposed that constantly produces a higher throughput than EDF-based algorithms by repeatedly finding an optimal scheduling for two classes. However, this new method requires the two classes be non-overloaded, which greatly restricts its applications. Since the overloaded situation is not avoidable from one iteration to the next in dealing with multiple classes, it is compelling to answer the open question: Can we find an optimal schedule for two overloaded classes efficiently? This paper first proves that this problem is NP-complete. Then, this paper proposes an optimal preprocessing algorithm that guarantees to drop a minimum number of packets from the two classes such that the remaining set is non-overloaded. This result directly improves on the new method.

Communications, 2004 IEEE …, 2004

Recently, extensive analytic research into packet scheduling in crossbar switches has yielded interesting throughput maximizing algorithms. Surprisingly, however, quality of service (QoS) performance associated with these algorithms has only been approximated through simulation. We present here certain randomized algorithms with analytic QoS. These are simple to implement and possess closed form expressions for various performance measures. By fine tuning particular parameters of these algorithms, one can vary the QoS associated with individual ports as desired. This allows cost and utility optimization, a feature which was not feasible under previously studied packet scheduling algorithms.

2004

We address the problem of congestion resolution in optical packet switching (OPS). We consider a fairly generic all-optical packet switch architecture with a feedback optical buffer constituted of fiber delay lines (FDL). Two alternatives of switching granularity are addressed for a switch operating in a slotted transfer mode: switching at the slot level (ie, fixed length packets of a single slot) or at the burst level (variable length packets that are integer multiples of the slot length).

IEEE/ACM Transactions on Networking, 2008

In modern packet switches, technology limitations may introduce switch configuration delays that are non-negligible compared with the time required to transmit a single packet. In this paper, we propose a methodology for scheduling of packets, in the context of these technology limitations. If the total tolerable delay through a packet switch is at least on the order of the switch configuration delay, we show that a near 100% utilization of the communication links is possible, while providing strict quality of service guarantees. The main idea is to increase the quantum with which data is scheduled and switched to beyond that of a single packet. This also decreases the rate at which scheduling need to be made, and hence decreases the implementation complexity. The quality of service guarantees we consider are in terms of a service curve. Specifically, we present a framework for the provision of service curves while coping with non-negligible switch configuration delays.

High-performance Packet Switching Architectures, 2007

We discuss the control of a packet switch where delays due to mode switching become important. Whereas most packet switch scheduling analysis assumes that switches can operate with negligible delays, we consider what to do when this does not hold.

IJCSNS, 2006

This paper investigates the problem of enabling Quality of Service (QoS) of multimedia traffic at the input port of high-performance input-queued packet switches using a simulation-based evaluation. We focus on the possibility of assuring QoS of multimedia traffic in such switches by implementing traffic prioritization at the input port where each input-queue has been modified to provide a separate buffer for each of the service classes. The multimedia traffic can be categorized into three classes based on its real-time properties and loss tolerance, and assigned a separate queue for each class. We select appropriate models for each of three types of traffic: video, voice, and data. Then, we propose an efficient dynamic scheduling strategy by implementing multimedia traffic prioritization at the input port of input-queued packet switches. Simulation-based comparisons show that while the static priority scheme is beneficial for highest priority class at the expense of the others, the dynamic prioritization serves fairly well all the classes in terms of delay and loss requirements.

IEEE Journal on Selected Areas in Communications, 2000

In this paper, we model the internal structure of a packet switching node in a real-time system and characterize the tradeoff between throughput, delay, and packet loss as a function of the buffer size, switching speed, etc. We assume a simple shared single path switch fabric, though the analysis can be generalized to a wider class of switch fabrics. We show that with a small number of buffers the node will provide a guaranteed delay bound for high-priority traffic, a low-average delay for low-priority traffic, no loss of packets at the input and low probability of packet loss at output. From 1984 to 1985 he was on the faculty with the Department of Electrical Engineering at the Technion. From 1985 he is with IBM T.

2005

AKIN, OZDEMIR. Active Queue Management and Scheduling Methods for Packet-Switched Networks (under the supervision of Dr. J. Keith Townsend) To support the myriad of envisioned communication products of the future, there is a need to develop a network infrastructure that can provide larger bandwidth, with better control of quality of service (QoS). However, with increasing demand for applications running over packet networks, congestion at the intermediate nodes (e.g., routers and switches) can be a serious problem. Consequences include long delays, large delay variation and high packet loss rates. Different solutions requiring varying levels of modification to the currently used algorithms have been proposed both for responsive (e.g., TCP) and unresponsive (e.g., UDP) protocols. However, most of the solutions are either too complicated to implement in real life or not general enough to be applicable to an arbitrary network topology. In this thesis, we investigate two mechanisms — ac...

arXiv (Cornell University), 2014

Given the rapid increase in traffic, greater demands have been put on high-speed switching systems. Such systems have to simultaneously meet several constraints, e.g., high throughput, low delay and low complexity. This makes it challenging to design an efficient scheduling algorithm, and has consequently drawn considerable research interest. However, previous results either cannot provide a 100% throughput guarantee without a speedup, or require a complex centralized scheduler. In this paper, we design a distributed 100% throughput algorithm for crosspoint buffered switches, called DISQUO, with very limited message passing. We prove that DISQUO can achieve 100% throughput for any admissible Bernoulli traffic, with a low time complexity of O(1) per port. To the best of our knowledge, it is the first distributed algorithm that can provide a 100% throughput for a crosspoint buffered switch.

IEEE/ACM Transactions on Networking, 2009

In this paper, we use fluid model techniques to establish new results for the throughput of input-buffered switches. Dai and Prabhakar have shown that any maximal size matching algorithm with speedup of 2 achieves 100% throughput. We introduce the maximum node containing matching (MNCM), which is a new class of matching algorithms that achieve 100% throughput with no speedup. The only assumption on the arrival processes is they satisfy the strong law of large numbers (SLLN). The MNCM policies only need to include ports whose weight (backlog) are above a threshold in the matching rather than finding a matching with maximum total weight. This simplified requirement enables us to introduce a new matching algorithm, maximum first matching (MFM), with O(N 2 5) complexity. We show that MFM is a low-complexity algorithm with good delay performance. We also provide a deterministic upper bound for the buffering requirement of a switch with an MNCM scheduler, when the ports incoming traffic are admissible and () regulated.

IEEE Transactions on Communications, 2003

iSLIP and parallel hierarchical matching (PHM) are distributed maximal size matching schedulers for input-buffered switches. Previous research has analyzed the hardware cost of those schedulers and their performance after a small number of iterations. In this letter, we formulate an upper bound for the number of iterations required by PHM to converge. Then, we compare the number of iterations required by iSLIP and PHM to achieve a maximal throughput under uniform Bernoulli traffic, by means of simulation. Finally, we obtain the corresponding delay performances, which are similar. The results suggest that PHM has both the advantages of previous hierarchical matching algorithms (low hardware complexity) and iSLIP (low number of iterations).

2000

In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission.