VMW: a visualization-based microarchitecture workbench

Modern microprocessors achieve high p erformance through the use of speculative execution and mechanisms to exploit instruc- tion level parallelism. Performance evaluation of such architec- tures is generally made using d etailed, cycle-by-cycle simula- tion. Since detailed simulation is s low, the design o f r ecent simulators has been focused on developing fast simulation en- gines. However, these optimized simulators are difficult t o modify or extend. In addition, intensive benchmarking is re- quired to v alidate simulation performance results. This task consumes a significant amount of time even if very fast simula- tors are used. This paper presents a novel simulation environment to study high p erformance microarchitectures. This environment con- sists of an extensible simulator for superscalar architectures and a group o f utilities to p erform benchmarking in p arallel. The new simulator developed has features that are not found in other simulators reported in the literatur...

Journal of Visual Languages & Computing, 1992

Novis, an experimental visual environment which supports the interactive development and animated simulation of special purpose parallel architectures, is presented. In sharp contrast with other systems which concentrate on the representation of parallelism within programs, Novis lets users design networks at an abstract level by placing processing elements into a connected grid of arbitrary (user selected) shape. The environment's underlying philosophy of maximal information hiding makes it unnecessary for the user to be intimately familiar with the details of low{level issues such as process schedule maintenance and event dispatching. Layout violations and exceptions detected during execution simulation (e.g., deadlock) are automatically reported to the user.

IEEE Symposium on Information Visualization, 1999

The advent of superscalar processors with out-of-or der execution makes it increasingly difficult to determine how we ll an applica- tion is utilizing the processor and how to adapt th e application to improve its performance. In this paper, we describ e a visualiza- tion system for the analysis of application behavio r on superscalar processors. Our system provides an

Proceedings of the 1990 IEEE Workshop on Visual Languages, 1990

Novis, a visual environment which supports the interactive development and animated simulation of special purpose parallel architectures, is presented. In sharp contrast with other systems which concentrate on the representation of parallelism within programs, Novis lets users design networks at an abstract level by placing processing elements into a connected grid of arbitrary (user selected) shape. The environment's underlying philosophy of maximal information hiding makes intimate familiarity on the part of the user with the details of low{level issues such as process schedule maintenance and event dispatching unnecessary. Layout violations and exceptions detected during execution simulation (e.g., deadlock) are automatically reported to the user. An overview of Novis's features is followed by examples that show o the environment's capabilities in a variety of useful applications.

2005

M-Sim is a multi-threaded microarchitectural simulation environment with a detailed cycle-accurate model for the key pipeline structures. M-Sim extends the SimpleScalar 3.0d toolset with accurate models of the pipeline structures, including explicit register renaming, and support for the concurrent execution of multiple threads according to the Simultaneous Multithreading (SMT) model. For power estimations, M-Sim includes the Wattch framework as applied to SimpleScalar. This technical report provides an overview of M-Sim, including a detailed description of the simulated processor as well as instructions for the installation and use of the M-Sim environment. The description is focused only on the changes made with respect to the Simplescalar.

High-performance computer processors have become much more complex in recent years, especially in the research community. We describe a Web-based interactive simulation and graphics tool under development at URI for the new Levo research processor. The tool mimics Levo operation and structure, aiding in broad understanding by researchers, students and engineers.

IEEE Micro, 1999

Designers face many choices when planning a new high-performance, general purpose microprocessor. Options include superscalar organization (the ability to dispatch and execute more than one instruction at a time), out-of-order issue of instructions, speculative execution, branch prediction, and cache hierarchy. However, the interaction of multiple microarchitecture features is often counterintuitive, raising questions concerning potential performance benefits and other effects on various workloads. Complex design trade-offs require accurate and timely performance modeling, which in turn requires flexible, efficient environments for exploring microarchitecture processor performance. Workload-driven simulation models are essential for microprocessor design space exploration. A processor model must ideally: capture in sufficient detail those features that are already well defined; make evolving assumptions and approximations in interpreting the desired execution semantics for those features that are not yet well defined; and be validated against the existing specification. These requirements suggest the need for an evolving but reasonably precise specification, so that validating against such a specification provides confidence in the results. Processor model validation normally relies on behavioral timing specifications based on test cases that exercise the microarchitecture. This approach, commonly used in simulation-based functional validation methods, is also useful for performance validation. In this article, we describe a workload driven simulation environment for PowerPC processor microarchitecture performance exploration. We summarize the environment's properties and give examples of its usage

ECMS 2011 Proceedings edited by: T. Burczynski, J. Kolodziej, A. Byrski, M. Carvalho, 2011

The computing systems, and particularly microarchitectures, are in a continuous expansion reaching an unmanageable complexity by the human mind. In order to understand and control this expansion, researchers need to design and implement larger and more complex systems' simulators. In the current paradigm the simulators play the key role in going further, by translating all complex processing mechanisms in relevant and easy to understand information. This paper aims to make a suggestive description of the concepts and principles implemented into a Simultaneous Multithreading Architecture. We introduce the SMTAHSim framework, an educational tool that simulates in an interactive manner the important aspects of this particular microarchitecture. The graphical simulation and the results reporting techniques provide a lot of easy to understand information that outline an expressive image of Simultaneous Multithreading (SMT) processing mechanisms. Our developed software tool facilitates the understanding of theoretical questions, thus allowing students to feel more confident when studying SMTrelated issues.

Embedded Computer Systems: …, 2009

System-level computer architecture simulations create large volumes of simulation data to explore alternative architectural solutions. Interpreting and drawing conclusions from this amount of simulation results can be extremely cumbersome. In other domains that also struggle with interpreting large volumes of data, such as scientific computing, data visualization is an invaluable tool. Such visualization is often domain specific and has not become widely studied and utilized for evaluating the results of computer architecture simulations.

Workshop On Computer Architecture Education, 2006

Two of the most important design issues for modern processors are power and performance. It is important for students in computer organization classes to understand the tradeoff between these two issues. This paper presents PSATSim, a graphical simulator that allows student to con- figure the design of a speculative out-of-order execution su- perscalar processor and see the effect of the