An algorithm for polygon conversion to boxes for VLSI layouts

ACM Transactions on Design Automation of Electronic Systems, 1996

We present two practical algorithms for partitioning circuit components represented by rectilinear polygons so that they can be stored using the L-shaped corner stitching data structure; that is, our algorithms decompose a simple polygon into a set of nonoverlapping L-shapes and rectangles by using horizontal cuts only. The more general of our algorithms computes an optimal configuration for a wide variety of optimization functions, whereas the other computes a minimum configuration of rectangles and L-shapes. Both algorithms run in O(n ϩ h log h) time, where n is the number of vertices in the polygon and h is the number of H-pairs. Because for VLSI data h is small, in practice these algorithms are linear in n. Experimental results on actual VLSI data compare our algorithms and demonstrate the gains in performance for corner stitching (as measured by different objective functions) obtained by using them instead of more traditional rectangular partitioning algorithms.

Computer-Aided Design, 1986

An efficient geometrical design rule checker is proposed, based on operations on quadtrees, which represent VLSI mask layouts. The time complexity of the design rule checker is O(N.), where N is the number of polygons in the mask. A pseudoPascal description is provided of all the important algorithms for geometrical design rule verification. computer-aided design, geometrical design rule checker, quadtrees 0010--4485/86/070380--09 ~03.00

Integration, the VLSI Journal, 1989

In this paper, we present two new tree structures, bisection trees and half-quad trees that can be used as data structures for storing VLSI layouts. The bisection tree is based on the structure of a 2-d tree and the half-quad tree is constructed based on the bisection tree and the quad tree. These two trees perform as good as a 4-d tree in terms of speed but require less memory. Specifically, our experimental results show that, for region queries, the bisection tree has approximately the same nodes visited as the 4-d tree. In addition, the bisection tree requires less memory space and simpler procedures. For the half-quad tree, it is shown that it approximately 50% memory of that used by the 4-d tree which is approximately the same as the memory used by the quad tree. In addition, the half-quad tree achieves a much better speed than the quad tree.

Computer-Aided Design, 1990

This paper presents the algorithms, implementation, and performance of a hierarchical mask compactor based on a fast region-query and space-efficient data structure called the multiple storage quadtree. Unlike symbolic compaction, the proposed mask compaction is based on rectangles rather than symbols. A new method of generating the constraint graph by using a sweeping-line algorithm in two-dimensional space is proposed in detail. 5ome important features of the mask compactor, such as error tolerance, mixed constraint, grid freeness, and hierarchical design and amalgamation, are described. Experimental results show that the proposed system successfully accomplishes layout compaction with almost linear time complexity in terms of the rectangles in the source layout.

IEEE Transactions on Automatic Control, 1983

In this paper, we present a new methodology for custom VLSI layout which aims at a low turnaround time and a high quality of design. VLSI circuits are highly complex, and to speed up the design process we exploit the hierarchical structure of a design, splitting the problem domain into several levels. The process of layout at each level is divided into steps such as placement of rectangular blocks, determining block dimensions, determining interconnection paths, etc. In order to obtain high quality designs, we have systematically analyzed the relationship among the parameters being computed at various steps and have accordingly organized the flow of data and control through these steps. There are two novel features in our scheme. First, we do not follow the usual pure top-down or pure bottom-up approach, so as to take into account the infl.uence of design decisions at the higher levels on design decisions made at the lower levels, as well as vice versa. For example, we determine the geomehy of a block taking into consideration the context in which it is placed, as well as the geometries of the lower level blocks it encloses. Second, we perform a look-ahead operation when the values of some. parameters are needed before they are actually deterministically computable by the process. For example, at the ,time of placement, the area required for routing is estimated statistically (before doing the actual routing) so that a more routable placement can be obtained, thereby avoiding some unnecessary iterations.

1987

In this paper, a new incremental algorithm for layout compaction is proposed. In addition to its linear time performance in terms of the number of rectangles in the layout, we also describe how incremental compaction can form a good feature in the design of a layout editor. The design of such an editor is also described. In the design of the editor, we describe how arrays can be used to implement quadtrees that represent VLSI layouts. Such a representation provides speed of data access and low storage requirements.

2000

This paper presents a survey and a taxonomy of layout compaction algorithms, which are an essential part of modern symbolic layout tools employed in VLSI circuit design. Layout compaction techniques are also used in the low-end stages of silicon compilation tools and module generators. The paper addresses the main algorithms used in compaction, focusing on their implementation characteristics, performance, advantages and drawbacks. Compaction is a highly important operation to optimize the use of silicon area, achieve higher speed through wire length minimization, support technology retargeting and also allow the use of legacy layouts. Optimized cells that were developed for a fabrication process with a set of design rules have to be retargeted for a new and more compact process with a different set of design rules

Arabian Journal of Geosciences, 2018

Based on an analysis of drawbacks in the existing graphical display of complex area objects in embedded system, the paper introduces a new method termed as consecutive boundary organization (CBO) which is able to convert a large number of separate polygons belonging to the same area object into a single consecutive stroke fitting for quick display. The working principle of the CBO method is demonstrated in three cases that can typically occur to the real-world concept Blake^: (1) a lake with an island in it, (2) a lake with multiple islands, and (3) the nested lake-island-lake. In spite of complicated inclusion relationships, the CBO method can always construct an integral stroke with neither information loss nor redundancy. Experiments with a real dataset of lakes and islands from North America have proved the feasibility and efficiency of the CBO method. Due to its generic nature, the CBO method can be applied to any other complex area objects with multiple polygons and inclusion levels.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1994

Folding or topological compaction of array-based VLSI layouts is an important optimization step that is carried out after logic synthesis. In this paper, a new approach to two-dimensional multiple folding of array-based VLSI layouts is presented. From the specification of the problem a pair of intersection gruphs is created. We show that any pair of interval graphs that contain the intersection graphs as spanning subgraphs corresponds to a set of feasible foldings. Next, a complete and exact characterization of the folding problem is presented. In particular, it is shown that the set of all feasible foldings associated with a given pair of interval graphs corresponds to the set of independent colorings of a pair of compatibility graphs. The compatibility graphs are derived from a pair of interval graphs that contain the intersection graphs as spanning subgraphs. Thus, minimizing the area of a layout is tantamount to finding a pair of compatibility graphs such that the product of their chromatic numbers is minimum. As important as minimizing the area of a layout is, the ability to rapidly generate compact layouts over a wide range of aspect ratios is often equally, if not more, important. The interval graphbased formulation of the folding problem permits a controlled and systematic generation of compact layouts with varying aspect ratios. Efficient and provably correct algorithms to generate compact layouts that have a given number of rows or a given number of columns within their minimum and maximum possible values are given. The basic theory and methods are extended to include U 0 and other types of constraints. Finally, the results of experiments that were carried out on a large number of benchmark problems are given. These results are compared with those obtained by previously reported methods. I. INTRODUCTION TRUCTURED LOGIC refers to logic forms that exhibit S a high degree of regularity in their layout and interconnections. The use of such regular structures makes it possible to automatically generate the layout from an abstract specification. The most widely used regular structure is the Programmable Logic Array (PLA). In addition, a variety of other regular structures have been proposed over the past two decades. Examples include Doubly Folded Transistor Matrix [19], Metal-Metal Matrix (M 3) [12], Flexible Transistor Matrix (FTM) [8], and Gate Matrix [21]. All these forms have a two-dimensional structure consisting of an array of row and column elements. An element can be as simple as a single transistor or as complex as a small network of transistors. When used in their most basic form, the advantage Manuscript

Proceedings Sixteenth Conference on Advanced Research in VLSI, 1995

We present a recursive method for generating layout for VLSI chips which combines the flexibility of gate array and standard cell layout with the control and density of custom layout. The method allows seamless integration of hand-drawn and synthesized layout, so that hand layout need only be used where the increase in density is justified. Layout is generated automatically with predictable results; small changes in the source result in small changes of the overall layout. The system is versatile enough to build dense VLSI microprocessor chips automatically.