Arithmetic Logic Unit Design using Vedic Mathematics

2012

This paper is devoted for designing high speed arithmetic logic unit. All of us know that ALU is a module which can perform arithmetic and logic operations. The reason behind choosing this topic as a research work is that, ALU is the key element of digital processors like as microprocessors, microcontrollers, central processing unit etc. Every digital domain based technology depends upon the operations performed by ALU either partially or whole. That's why it highly required designing high speed ALU, which can enhance the efficiency of those modules which lies upon the operations performed by ALU. The speed of ALU greatly depends upon the speed of multiplier. There are so many multiplication algorithms exist now-a-days at algorithmic and structural level. Our work proved that Vedic multiplication technique is the best algorithm in terms of speed. Further we have seen that the conventional Vedic multiplication hard wares have some limitations. So to overcome those limitations a n...

All of us know that ALU is a module which can perform arithmetic and logic operations. The reason behind choosing this topic as a research work is that, ALU is the key element of digital processors like as microprocessors, microcontrollers, central processing unit etc. Every digital domain based technology depends upon the operations performed by ALU either partially or whole. That’s why it highly required designing high speed ALU, which can enhance the efficiency of those modules which lies upon the operations performed by ALU. The speed of arithmetic is of extreme importance and depends greatly on the speed of multiplier. Therefore the technologies are always looking for new algorithm and hardware so as to implement this operation in much optimized way in the terms of area and speed. Vedic Mathematics deals with various branches of mathematics like arithmetic, algebra, geometry etc in computation algorithm of the coprocessor which will reduce the complexity of execution time, area and power consumption etc. Multiplier based on Vedic Mathematics is one of the fast and low power multiplier. In this paper arithmetic logic unit is design with the pipelining technique based on vedic mathematics to improve the execution speed and consuming power.

2014

Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculation based on 16 formula (sutras). The word Vedic is desired from word Veda which store house of all knowledge. As the ever increasing demand in enhancing the ability of coprocessor to handle the complex and challenging processor as resulted in integration of number of processor cores into single chip, but still the load on the processor is not less in generic system. This load is reduced by connecting the main processor with co processor, which are designed to work on the specific types of function like numeric computation, signal processing, image processing and arithmetic operation. The speed of arithmetic is of extreme importance and depends greatly on the speed of multiplier. Therefore the technologies are always looking for new algorithm and hardware so as to implement this operation in much optimized way in the terms of area and speed. Vedic Mathematics deals with various branches of...

2015

The ever increasing demand in enhancing the speed of processors to handle the challenging problems has resulted in the need of an efficient ALU. The speed of ALU greatly depends on multiplier and Vedic mathematics helps in the design of an efficient multiplier using Anurupyena and Urdhva Tiryakbhyam. Using Ekadhikena Purvena and Dwandwayoga a squarer circuit is generated. After designing the proposed Vedic multiplier and Squarer Circuit, it is integrated into an eight bit module of arithmetic logic unit along with the conventional adder, subtractor, and basic logic gates. The performance of the Different Multipliers and Squarer circuit is analyzed using Xilinx ISE 9.1i.From the results it is found that Dwandwayoga Squarer is better than Ekadhikena in terms of time delay but on the other hand Ekadhikena Purvena consumes less power than Dwandwayoga. Among multipliers Anurupyena is better in terms of power consumption than Urdhva Tiryakbhyam but it is having much delay. After synthesiz...

The Concentration of this paper is the designing and implementation of an Arithmetic Logic Unit (ALU) using certain area optimizing techniques such as Vedic Multiplier Algorithm for Multiplication Process & Gate-Diffusion-input (GDI) logic for basic elements. The main sub-blocks of ALU are Adder, Multiplier, Multiplexer and Logical Block. This paper evaluates and compares the performance and optimized area of ALU with CMOS technique and GDI technique in 180nm CMOS process technology. Simulations are performed by using Cadence 180nm technology and compared with CMOS logic realization. The simulation gives that design of ALU through GDI is more efficient with low power consumption, decreases area and faster compared with CMOS logic.

Digital signal processing (DSP) is the technology that is omnipresent in almost every engineering discipline. A typical processor devotes a considerable amount of processing time in performing arithmetic operations, particularly multiplication operations. Multiplication is one of the basic arithmetic operations and it requires substantially more hardware resources and processing time than addition and subtraction. In fact, 8.72% of all the instruction in typical processing units is multiplication. The core computing process is always a multiplication routine; therefore, DSP engineers are constantly looking for new algorithms and hardware to implement them. Vedic mathematics is the name given to the ancient system of mathematics, which was rediscovered, from the Vedas between 1911 and 1918 by Sri Bharati Krishna Tirthaji. The whole of Vedic mathematics is based on 16 sutras (word formulae) and manifests a unified structure of mathematics. This paper presents the design of a low power high speed algorithms for arithmetic logic units using this ancient mathematics techniques and also their hardware implementation. Even convolution algorithms using this technique are discussed along with their FGPA implementation. Employing these techniques in the computation algorithms of the coprocessor has reduced the complexity, execution time, area, power. Further research prospects may include the design and development of a Vedic DSP chip using VLSI technology

IOSR Journal of VLSI and Signal Processing, 2016

Arithmetic and Logic Unit (ALU) is the most crucial and core component of central processing unit as well as of number of embedded systems and microprocessors. ALU consists of many computational units like adders, multipliers, logical units etc. Vedic Mathematics concepts are proposed here for designing the computational units of an 8-bit ALU. Here, a high-speed 8×8 bit multiplier is proposed which is based on the Vedic multiplier mechanism. A divider based on vedic mathematics is also proposed here. The proposed Vedic mathematics based ALU is designed using high level hardware description language-Verilog, followed by synthesization using EDA tool, Xilinx ISE 14.1. Finally, the synthesized circuit has been implemented on Xilinx Spartan-6 Field Programmable Gate Array (FPGA) device.

International Journal of Scientific Research in Science and Technology, 2022

16-bit RISC processor with Vedic multiplier architecture is used in this project. In addition to multiplier which is implemented using vedic mathematics we are also proposing an adder which is hybrid adder for building higher bit adders in an area efficient which is implemented in addition as well as for compression in vedic mathematic to obtain the output. The multiplier unit is developed utilizing Vedic Sutras, which is the primary accomplishment of this study. The primary premise of Vedic mathematics is to minimize the computational complexity by reducing the usual calculation of conventional mathematics to a very simple calculation. The suggested RISC processor is extremely primitive, and it can only execute 14 instructions. The accomplishment of this study is that in the case of MAC and ALU, power savings and minimized latency are realized as compared to traditional ALU and MAC. Following that, the Vedic MAC and ALU are combined with other processing blocks to create a 16-bit Vedic processor. As a result, the major features of the developed RISC processor are an increase in operating speed, a decrease in power consumption, and a reduction in area consumption.

The load on general processor is increasing. For Fast Operations it is an extreme importance in Arithmetic Unit. The performance of Arithmetic Unit depends greatly on it multipliers. So, researchers are continuous searching for new approaches and hardware to implement arithmetic operation in huge efficient way in the terms of speed and area. Vedic Mathematics is the old system of mathematics which has a different technique of calculations based on total 16 Sutras. Proposed work has discussion of the quality of Urdhva Triyakbhyam Vedic approach for multiplication which uses different way than actual process of multiplication itself. It allows parallel generation of elements of products also eliminates undesired multiplication steps with zeros and mapped to higher level of bit using Karatsuba technique with processors, the compatibility to various data types. It is been observed that lot of delay is required by the conventional adders which are needed to have the partial products so in the work it is further optimized the Vedic multiplier type Urdhva Triyakbhyam by replacing the traditional adder with Carry save Adder to have more Delay Optimization. The proposed work shows improvement of speed as compare with the traditional designs. After the proposal discussion of the Vedic multiplier in the paper, It is been used for the implementation of Arithmetic unit using proposed efficient Vedic Multiplier it is not only useful for the improve efficiency the arithmetic module of ALU but also it is useful in the area of digital signal processing. The RTL entry of proposed Arithmetic unit done in VHDL it is synthesized and simulated with Xilinx ISE EDA tool. At the last the proposed Arithmetic Unit is validated on a FPGA device Vertex-IV.

2014

A high speed controller or processor depends vastly on the multiplier as it is one of the main hardware blocks in most digital signal processing unit as well as in general processors. This paper presents a high speed Vedic multiplier architecture which is quite different from the Conventional Vedic multiplier. The most significant aspect of the proposed method is that, the developed multiplier architecture uses Carry look ahead adder as a key block for fast addition. Using Carry look ahead adder the performance of multiplier is vastly improved. This also gives chances to break whole design into smaller blocks and use it whenever required. So by using structural modeling we can easily make large design by using small design and thus complexity gets reduced for inputs of larger no of bits. We had written code for proposed new Vedic multiplier using VHDL (Very High Speed Integrated Circuits Hardware Description Language), synthesized and simulated using XilinxISE8.1i and downloaded to ...