Architectural implications of a digital optical processor

Semiconductor Technologies, 2010

Semiconductor Technologies 438 designated output port. The other packet is delayed or discharged. Therefore a complex photonic digital circuit, able to compare two boolean numbers, is mandatory (Andriolli et al., 2007). All-optical subsystems able to discriminate if an N-bit (with N1) pattern representing a boolean number is greater or lower than another one are not reported yet. Calculating the addition of boolean numbers is another important functionality to perform packet header processing. If some packets are routed to the wrong link or are mislabelled, they can be routed in circles without reaching the destination. These loops are a cause of network congestion and must be avoided. A Time-To-Live (TTL) field in the packet prevents the formation of loops. This field represents the maximum number of hops of a packet and it is decremented after each node. When the field value is zero, the packet is discharged (McGeehan et al., 2003). The implementation of this functionality requires an all-optical processing circuit able to perform the decrementing of the boolean number in the TTL field. This operation can be performed by means of an all optical full-adder applying the so called method of complements (Hayes 1998). Moreover the all-optical full-adder can find application in resolving the Viterbi algorithm in the Maximum-Likelihood Sequence Estimation (MLSE) (Forney 1973; Proakis 1996). This method requires performing fast additions. An all-optical implementation of this algorithm can improve its efficiency. Other two important functions are analog-to-digital conversion (ADC) and digital-to-analog conversion (DAC). ADC is a key functionality which, converting continuous-time signals to digital binary signals, enables them to be transmitted through the modern digital communication networks. Applications regard e.g. radar signals, high-definition video, realtime signal monitoring, ultra-fast dispersion compensation. Although it didn't receive the same attention as all-optical analog-to-digital conversion, DAC and/or multilevel codification in the optical domain has also been extensively investigated in order to implement some ultra-fast signal processing functions. These functions include, for instance, pattern recognition for header extraction (Saida et al., 2001), amplitude multiplexing for increasing spectral efficiency (Abbade et al., 2005) or label/payload encoding techniques (Abbade et al., 2006), and waveform generation for radar and display applications (Yacoubian & Das, 2003). The photonic digital processing is effective and attractive if it can be realised with integrated solutions. SOAs have shown to be attractive because of their compactness, stability, low switching energy and low latency. SOAs are reliable, relatively low cost devices which can be integrated within complex optical circuits with hybrid techniques (Maxwell, 2008; Lal et al., 2007; Kehayas et al., 2006 b). In this perspective, the possibility of using a single basic building gate for implementing all the complex logic functions is practical. In this chapter new schemes for the implementation of SOA-based reconfigurable logic gates, a photonic combinatorial network, a comparator, a full-adder, a digital-to-analog converter and an analog-to-digital converter will be presented. 2. Reconfigurable logic gates with a single SOA Scheme of all-optical logic gates are reported in literature, using nonlinear effects in optical fibers (

Proceedings of SPIE - The International Society for Optical Engineering, 1990

The activities of the Rutgers CAM group 'for 1989 are recorded herein. These consist of the development of several experimental software systems on an AHT m (Distributed Array Processor) for evaluation and research purposes. The resulti determinations of the strengths and weakness of the DAP are discussed. Twoa machine architectures were developed in an attempt to consolidate the strengths ar4 overcome the weaknesses. The effort led to the analysis of certain paralitil algorithms from a new point of view, and thius to a new class. of paralle. algroithms, the semiserial algorithms. /> .

Applied Optics, 1988

Regular free-space interconnects such as the perfect shuffle and banyan provided by beam splitters, lenses, and mirrors connect optical logic gates arranged in 2-D arrays. An algorithmic design technique transforms arbitrary logic equations into a near-optimal depth circuit. Analysis shows that an arbitrary interconnect makes little or no improvement in circuit depth and can even reduce throughput. Gate count is normally higher with a regular interconnect, and we show cost bounds. We conclude that regularly interconnected circuits will have a higher gate count compared with arbitrarily interconnected circuits using the design techniques presented here and that regular free-space interconnects are comparable with arbitrary interconnects in terms of circuit depth and are preferred to arbitrary interconnects for maximizing throughput. 1. Introduction All-optical digital computers have the potential for high speed, cheap communications, and massive parallelism. Logic gates based on nonlinear dielectric constants were investigated theoretically in the early 1960s by von Neumann. 1 In the last few years optical bistable devices, 2 ' 3 nonlinear Fabry-Perots, 4 ' 5 and hybrid electrooptic devices 6 have been studied experimentally. These results encourage development of architectures suitable for optics. Historically, two architectural approaches have dominated the field. One approach uses integrated optics to interconnect optical logic devices. A system designed with this approach is architecturally similar to a conventional computer, with logic gates connected in arbitrary configurations. This similarity means that an optical computer designed with this approach is worth building only if it can be made more cheaply or more powerful. An alternative approach makes use of 2-D arrays of devices interconnected in free space. This approach uses space-variant interconnects (provided by holograms) or space-invariant regular interconnects (provided by beam splitters). We prefer the space-invariant regular interconnect approach for simplicity, extensibility, and high throughput. To take advan

2006

We present a logical design of an all-optical processor that performs modular arithmetic. The overall design is based a set of interconnected modules that use all-optical gates to perform simple logical functions. The all-optical logic gates are based on the semiconductor optical amplifier nonlinear loop. Simulation results are presented and some practical design issues are discussed.

2011

This paper is dedicated to full-optical logical NOT, AND and NAND gates. In the first section are described logical functions based on Mach-Zehnder interferometric structure. The second part deals with full-optical logical gate AND, that utilizes TOAD structure. The last one is focused on the exploitation of logical gate AND for optical head separation from payload data. Simulations and final design were realized in simulation environment Virtual Photonic close up to 150 Gb.s bit rate.

Applied Optics, 1992

Heat removal, rather than finite interconnect density, is the major mechanism that limits how densely we can pack three-dimensional computing systems of increasing numbers of elements. Thus highly interconnected approaches can be employed without a further increase in system size. The use of optical interconnections for implementing the longer connections of such systems is advantageous. In fact, if the optical communication energy is sufficiently low and large-bit repetition rates are employed, conductors are useful for only the shortest connections and can be dispensed with altogether with little disadvantage. This justifies consideration of an optical digital computer. This paper is an initial attempt to understand whether and when an all-optical digital computer may prove useful. Several researchers have addressed this issue in the past, often with negative conclusions. We believe that an increasing understanding regarding the importance of communication in computing and the realization that the architectural-logical construction of a computing system can no longer be divorced from its physical construction justifies a reevaluation of previous arguments and a search for hitherto unexplored perspectives.

Applied Optics, 1998

A concept for a parallel digital signal processor based on optical interconnections and optoelectronic very large scale integrated circuits is presented. It is shown that the right combination of optical communication, architecture and algorithms allows a throughput that outperforms pure electronic solutions. The usefulness of low-level algorithms from the add-and-shift class is emphasized. These algorithms lead to ne-grain, massively parallel on-chip processor architectures with high demands for optical o -chip interconnections. A comparative performance analysis shows the superiority of a bit serial architecture. This architecture is mapped onto an optoelectronic 3-D circuit and the necessary optical interconnection scheme is speci ed.

Applied Optics, 1995

The slow execution speed of current rule-based systems 1RBS's2 has restricted their application areas. To improve the speed of RBS's, researchers have proposed various electronic multiprocessor systems as well as optical systems. However, the electronic systems still suffer in performance from the large amount of required time-consuming pattern-matching and comparison operations at the core of RBS's. And optical systems do not fully exploit the available parallelism in RBS's. We propose an optical contentaddressable parallel processor for expert systems. The processor executes the three basic RBS operations, match, select, and act, in a highly parallel fashion. Additionally, it extracts and exploits all possible parallelism in a RBS. Distinctive features of the proposed system include the following: 112 two-dimensional representation of data 1knowledge2 and control information to exploit the parallelism of optics in the three RBS units; 122 capability of processing general-domain knowledge expressed in terms of variables, numbers, symbols, and comparison operators such as greater than and less than; 132 the parallel optical match unit, which performs the two-dimensional optical pattern matching and comparison operations; 142 a novel conflict-resolution algorithm to resolve conflicts in a single step within the optical select unit. The three units and the general-knowledge representation scheme are designed to make the optical content-addressable parallel processor for expert systems suitable for any high-speed general-purpose RBS.

2015

Optical computing elements offer benefits over traditional CMOS-based electronic logic gates such as increased performance and reduced power. Using polarization to encode the information to be processed allows for the possibility of nonbinary switching theory to be applied that further offers the benefit of reducing the number of required elements in an optical computing circuit. A methodology for synthesizing non-binary optical computing circuits is described and experimental results are provided that justify the approach.