Shared Memory Multiprocessor-A Brief Study

2009

Cooperative researches between Brazilian and French universities are not recent. In the last years, these cooperations have allowed research groups to exchange knowledge and experiences in many different fields. High Performance Computing is one of these research areas in which research groups from both countries are collaborating in order to achieve meaningful results. In this scenario, cooperations between France and Brazil researchers are becoming more and more frequent. This work presents the results of some of these cooperations concerning the impact of hierarchical Shared Memory Multiprocessors on High Performance Applications.

… of the 22nd annual international conference …, 2008

This paper describes initial results for an architecture called the Shared-Thread Multiprocessor (STMP). The STMP combines features of a multithreaded processor and a chip multiprocessor; specifically, it enables distinct cores on a chip multiprocessor to share thread state. This shared thread state allows the system to schedule threads from a shared pool onto individual cores, allowing for rapid movement of threads between cores.

Proceedings. Fifth International Conference on High Performance Computing (Cat. No. 98EX238), 1998

In this paper, we consider the design alternatives available for building the next generation DSM machine (e.g., the choice of memory architecture, network technology, and amount and location of per-node remote data cache). To i n vestigate this design space, we h a ve simulated six applications on a wide variety of possible DSM architectures that employ signi cantly di erent caching techniques. We also examine the impact of using a specialpurpose system interconnect designed speci cally to support low latency DSM operation versus using a powerful o the shelf system interconnect. We h a ve found that two architectures have the best combination of good average performance and reasonable worst case performance: CC-NUMA employing a moderate-sized DRAM remote access cache (RAC) and a hybrid CC-NUMA/S-COMA architecture called AS-COMA or adaptable S-COMA. Both pure CC-NUMA and pure S-COMA have serious performance problems for some applications, while CC-NUMA employing an SRAM RAC does not perform as well as the two a r c hitectures that employ larger DRAM caches. The paper concludes with several recommendations to designers of next-generation DSM machines, complete with a discussion of the issues that led to each recommendation so that designers can decide which ones are relevant to them given changes in technology and corporate priorities.

2007

The model improves the performance of the shared memory multiprocessor systems by separating shared data from private data. Private data migrate to the local cache of each processor and the shared data to a shared cache.

Wiley-Interscience eBooks, 2005

Shared memory systems form a major category of multiprocessors. In this category, all processors share a global memory. Communication between tasks running on different processors is performed through writing to and reading from the global memory. All interprocessor coordination and synchronization is also accomplished via the global memory. A shared memory computer system consists of a set of independent processors, a set of memory modules, and an interconnection network as shown in Figure 4.1. Two main problems need to be addressed when designing a shared memory system: performance degradation due to contention, and coherence problems. Performance degradation might happen when multiple processors are trying to access the shared memory simultaneously. A typical design might use caches to solve the contention problem. However, having multiple copies of data, spread throughout the caches, might lead to a coherence problem. The copies in the caches are coherent if they are all equal to the same value. However, if one of the processors writes over the value of one of the copies, then the copy becomes inconsistent because it no longer equals the value of the other copies. In this chapter we study a variety of shared memory systems and their solutions of the cache coherence problem.

1991

Multiprocessors with shared memory are considered more general and easier to program than message-passing machines. The scalability is, however, in favor of the latter. There are a number of proposals showing how the poor scalability of shared memory multiprocessors can be improved by the introduction of private caches attached to the processors. These caches are kept consistent with each other by cache-coherence protocols.

Concurrency Practice and Experience, 1993

In the standard kernel organization on a bus-based multiprocessor, all processors share the code and data of the operating system; explicit synchronization is used to control access to kernel data structures. Distributed-memory multicomputers use an alternative approach, in which each instance of the kernel performs local operations directly and uses remote invocation to perform remote operations. Either approach to interkernel communication can be used in a large-scale shared-memory multiprocessor. In the paper we discuss the issues and architectural features that must be considered when choosing between remote memory access and remote invocation. We focus in particular on experience with the Psyche multiprocessor operating system on the BBN Butterfly Plus. We find that the Butterfly architecture is biased towards the use of remote Invocation for kernel operations that perform a significant number of memory references, and that current architectural trends are likely to increase this bias in future machines. This conclusion suggests that straightforward parallelization of existing kernels (e.g. by using semaphores to protect shared data) is unlikely in the future to yield acceptable performance. We note, however, that remote memory access is useful for small, frequently-executed operations, and is likely to remain so. *Eliseu Chaves is with the Universidade Federal do Rio de Janeim, Brazil. He spent six months on leave at the University of Rochester in 1990. Prakash Das is now with Transarc Corp. in Pittsburgh, PA. Brian Marsh is now with the Matsushita Information Technology Lab in Princeton, NJ. 1 t is customary to refer to bus-based machines as UMA (uniform memory access) multiprocessors, but the terminology can be misleading. Main memory (if present) is equally far from all processors, but caches are not, and caches are the dominant determinant of memory performance.

Trinity College Dublin, 1998

So much has already been written about everything that you can't nd out anything about it. | James Thurber, L a n terns and Lances (1961) Loosely-coupled distributed systems have e v olved using message passing as the main paradigm for sharing information. Other paradigms used in loosely-coupled distributed systems, such as rpc, are usually implemented on top of an underlying message-passing system. On the other hand, in tightly-coupled architectures, such a s m ulti-processor machines, the paradigm is usually based on shared memory with its attractively simple programming model. The shared-memory paradigm has recently been extended for use in more loosely-coupled architectures and is known as distributed shared memory (dsm 153, 1 7 8 , 5 8 ]) in this context. This chapter discusses some of the issues involved in the design and implementation of such a dsm in loosely-coupled distributed systems and brie y discusses related work in other elds.

Characteristics of multiprocessors  A multiprocessor system is an interconnection of two or more CPUs with memory and input-output equipment.  The term "processor" in multiprocessor can mean either a central processing unit (CPU) or an input-output processor (IOP).  Multiprocessors are classified as multiple instruction stream, multiple data stream (MIMD) systems  The similarity and distinction between multiprocessor and multicomputer are o Similarity  Both support concurrent operations o Distinction  The network consists of several autonomous computers that may or may not communicate with each other.  A multiprocessor system is controlled by one operating system that provides interaction between processors and all the components of the system cooperate in the solution of a problem.  Multiprocessing improves the reliability of the system.  The benefit derived from a multiprocessor organization is an improved system performance.

Computer, 2000

S hared memory multiprocessors make it practical to convert sequential programs to parallel ones in a variety of applications. Most such machines incorporate caches in each node, to allow data replication, and use a cache coherence protocol to ensure that a processor accesses the latest copy of the replicated data.

Proceedings of 1993 5th IEEE Symposium on Parallel and Distributed Processing, 1993

This paper presents the results of an experimental evaluation of the performance of a dynamic distributed federated database (DDFD). Databases of varying sizes up to 1025 nodes, have been evaluated in a test environment consisting of a 22 IBM Blade Servers plus 3 Logical Partitions of an IBM System P Server. The results confirm that by 'growing' databases, using biologically inspired principles of preferential attachment, that the resulting query 'execute time' is a function of the number of nodes (N) and the network latency (T L ) between nodes and scales as O(T L logN). Distributing data across all the nodes of the database and performing queries from any single node also confirms that, where network bandwidth is not a constraint, the data 'fetch time' is linear with number of records returned.

2013

Modern embedded systems embrace many-core shared-memory designs. Due to constrained power and area budgets, most of them feature software-managed scratchpad memories instead of data caches to increase the data locality. It is therefore programmers’ responsibility to explicitly manage the memory transfers, and this make programming these platform cumbersome. Moreover, complex modern applications must be adequately parallelized before they can the parallel potential of the platform into actual performance. To support this, programming languages were proposed, which work at a high level of abstraction, and rely on a runtime whose cost hinders performance, especially in embedded systems, where resources and power budget are constrained. This dissertation explores the applicability of the shared-memory paradigm on modern many-core systems, focusing on the ease-of-programming. It focuses on OpenMP, the de-facto standard for shared memory programming. In a first part, the cost of algorithm...

Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '07, 2007

This paper presents a framework to design a shared memory multiprocessor on a programmable platform. We propose a complete flow, composed by a programming model and a template architecture. Our framework permits to write a parallel application by using a shared memory model. It deals with the consistency of shared data, with no need of hardware coherence protocol, but uses a software model to properly synchronize the local copies with the shared memory image. This idea can be applied both to a scratchpadbased architecture or a cache-based one. The architecture is synthesizable with standard IPs, such as the softcores and interconnect elements, which may be found in any commercial FPGA toolset.

Supercomputing Conference, 1995

The goal of this work is to explore architectural mechanisms for supporting explicit communication in cachecoherent shared memory multiprocessors. The motivation stems from the observation that applications display wide diversity in terms of sharing characteristics and hence impose different communication requirements on the system. Explicit communication mechanisms would allow tailoring the coherence management under software control to match these differing needs and strive to provide a close approximation to a zero overhead machine from the application perspective. Toward achieving these goals, we first analyze the characteristics of sharing observed in certain specific applications. We then use these characteristics to synthesize explicit communication primitives. The proposed primitives allow selectively updating a set of processors, or requesting a stream of data ahead of its intended use. These primitives are essentially generalizations of prefetch and poststore, with the ability to specify the sharer set for poststore either statically or dynamically. The proposed primitives are to be used in conjunction with an underlying invalidation based protocol. Used in this manner, the resulting memory system can dynamically adapt itself to performing either invalidations or updates to match the communication needs. Through application driven performance study we show the utility of these mechanisms in being able to reduce and tolerate communication latencies.

ACM Transactions on Computer Systems, 1993