Evolutionary Codesign

Design Automation for Embedded Systems, 2011

Embedded systems are widely used in many sophisticated applications. To speed the time-to-market cycle, the hardware and software co-design has become one of the main methodologies in modern embedded systems. The most important challenge in the embedded system design is partitioning; i.e. deciding which modules of the system should be implemented in hardware and which ones in software. Finding an optimal partition is hard because of the large number and different characteristics of the modules that have to be considered.

Lecture Notes in Computer Science, 1996

In this paper, we present an approach to hardware software codesign of real-time embedded systems. Two of the di culties associated with codesign are handling tradeo s among multiple attributes and exploring a large design space. We use a combination of techniques from the evolutionary computation and utility theory elds to address these problem areas. A real-time microcontroller-based design example is presented to illustrate our approach.

1998

The HW/SW partitioning problem addressed in this paper is one of the key steps in the co-design flow of heterogeneous embedded systems. Generally the aim is to provide solutions that respect timing constraints and minimize an objective function such as the total area and/ or the power consumption. Minimizing the hardware area conflicts with reducing execution time. Therefore, we introduce an heuristic for synthesizing heterogeneous systems that uses a global metric to guide the mapping of tasks according to the reusability of components and the time margin induced by timing constraints.

… , 1993, with the European Event in …, 1994

... IEEE Symp. on Field-Programmable Custom Computing Ma-chines, pp. ... [14] M. Kaul, R. Vemuri, S. Govindarajan, and I. Ouaiss, “An auto-mated temporal partitioning and loop fission approach for fpga based reconfigurable synthesis of dsp applications,” in Proc. ...

2001

A novel ÅÙÐØ ¹Ä Ú Ð È ÖØ Ø ÓÒ Ò (MLP) technique taking into account Ö Ð¹ÛÓÖÐ ÓÒ×ØÖ ÒØ× for hardwaresoftware partitioning in ×ØÖ ÙØ Ñ ÅÙÐØ ÔÖÓ ××ÓÖ ËÝ×Ø Ñ× (DEMS) is proposed. This MLP algorithm uses a gradient metric based on hardware-software cost and performance as the core metric for selection of optimal partitions and consists of three nested Ð Ú Ð×. The innermost level is a simple binary search that allows quick evaluations of a large number of possible partitions. The middle level iterates over different possible allocations of processors (that execute software) to subsystems. The outermost level iterates over the number of processors and the hardware cost range. Heuristics are applied to each level to avoid the expensive exhaustive search. The application of MLP as a recently purposed ×ØÖ ÙØ Ñ ËÝ×Ø Ñ Ó × Ò (DESC) methodology shows its feasibility. Comparisons between real-world examples partitioned using MLP and using other existing techniques demonstrate contrasting strengths of MLP. Sharing, clustering, and hierarchical system model are some important features of MLP, which contribute towards producing more optimal partition results.

EURASIP Journal on Advances in Signal Processing, 2003

We provide a methodology used for the temporal partitioning of the data-path part of an algorithm for a reconfigurable embedded system. Temporal partitioning of applications for reconfigurable computing systems is a very active research field and some methods and tools have already been proposed. But all these methodologies target the domain of existing reconfigurable accelerators or reconfigurable processors. In this case, the number of cells in the reconfigurable array is an implementation constraint and the goal of an optimised partitioning is to minimise the processing time and/or the memory bandwidth requirement. Here, we present a strategy for partitioning and optimising designs. The originality of our method is that we use the dynamic reconfiguration in order to minimise the number of cells needed to implement the data path of an application under a time constraint. This approach can be useful for the design of an embedded system. Our approach is illustrated by a reconfigurable implementation of a real-time image processing data path.

ACM Transactions on Design Automation of Electronic Systems, 2003

This paper presents an in-depth study of several system partitioning procedures. It is based on the appropriate formulation of a general system model, being therefore independent of either the particular co-design problem or the specific partitioning procedure. The techniques under study are a knowledge-based system and three classical circuit partitioning algorithms (Simulated Annealing, Kernighan&Lin and Hierarchical Clustering). The former has been entirely proposed by the authors in previous works while the later have been properly extended to deal with system level issues. We will show how the way the problem is solved biases the results obtained, regarding both quality and convergence rate. Consequently it is extremely important to choose the most suitable technique for the particular co-design problem that is being confronted.

ACM Transactions on Design Automation of Electronic Systems, 2003

This paper presents an in-depth study of several system partitioning procedures. It is based on the appropriate formulation of a general system model, being therefore independent of either the particular co-design problem or the specific partitioning procedure. The techniques under study are a knowledge-based system and three classical circuit partitioning algorithms (Simulated Annealing, Kernighan&Lin and Hierarchical Clustering). The former has been entirely proposed by the authors in previous works while the later have been properly extended to deal with system level issues. We will show how the way the problem is solved biases the results obtained, regarding both quality and convergence rate. Consequently it is extremely important to choose the most suitable technique for the particular co-design problem that is being confronted.

2002

The problem of hardware-software partitioning for systems that are being designed as multifunction systems is addressed. Simulated annealing is known to generate very good solutions for most optimization problems, however the running time of this algorithm can be very high. We apply a modified simulated annealing approach to the partitioning problem resulting in a smaller search space, yet yielding good partitions. We show experimental results that yield better solutions in comparison to the existing multifunction partitioning approaches within acceptable running time.