Optimal aspect ratios of building blocks in VLSI

Iee Proceedings-computers and Digital Techniques - IEE PROC-COMPUT DIG TECH, 1997

The authors consider the optimum partitioning problem defined as follows: given a rectilinear layout C consisting of n rectangles, it is desirable to partition (decompose) the remaining free space into rectangular free blocks using horizontal and/or vertical partition edges such that the number of free blocks is minimised. The authors give a new formula for counting the number of free blocks in any partition of a given layout. Based on the new formula, they show that the optimum partitioning problem reduces to the problem of finding a maximum independent vertex set (MIS) in a bipartite graph. They then give an optimum partitioning algorithm (OPA) for computing an optimum partition. This optimum partitioning algorithm can be used to improve the space and time complexities of many applications where space partitioning is encountered. One example is the corner stitching data structure used for design rule checker (DRC) in the layout system Magic. In the experiments, the space complexity of the corner stitching data structure can be improved by an average of 13% by using the proposed optimum partitioning. Other applications are also presented.

2017 Computer Science and Information Technologies (CSIT), 2017

A slicing floorplan is a geometrical structure obtained by a series of successive dissections of a given rectangle by horizontal or vertical lines. The logical structure of a slicing floorplan can be represented by a binary tree whose leaves denote rectangles of the resulting floorplan and internal nodes specify horizontal and vertical cut lines. The slicing structure is widely used in digital circuit physical design to determine rectangles (or, rooms), where blocks (i.e., separated parts of the digital circuit) should be allocated. The quality of a floorplan is estimated based on the area of its enclosing rectangle and the closeness of logically connected blocks to each other. We suggest a method of transformation of a floorplan to solve several optimization problems such as concentration of predefined blocks around a target point, migration of predefined blocks towards each other, etc. All these transformations are done by keeping the bounding rectangle of the floorplan.

Lecture Notes in Computer Science, 2000

We present a genetic algorithm (GA) which used a normalized postfix encoding scheme to solve the VLSI floorplanning problem. We claim to have overcome the representational problems previously associated with encoding postfix expressions into GAs, and have developed a novel encoding scheme which preserves the integrity of solutions under the genetic operators. Optimal floorplans are obtained for module sets taken from some MCNC benchmarks. The slicing tree construction procedure, used by our GA to generate the floorplans, has a run time scaling which compares very favourably with other recent approaches.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1998

Existing algorithms for floorplan topology generation by rectangular dualization usually do not consider sizing issues. In this paper, given a rectangularly dualizable adjacency graph and a set of aspect ratios of the modules, a topology which is likely to yield an optimally sized floorplan, is produced first in a top-down fashion by an AI-based search technique with novel heuristic estimates based on size parameters. It is shown that for any rectangular graph, there exists a feasible topology using only either straight or Z-cutlines recursively within a bounding rectangle. The significance of this result is four-fold: 1) considerable acceleration of the heuristic search, 2) topology generation with minimal number of nonslice cores, 3) guaranteed safe routing order without addition of pseudo modules, and 4) design of an efficient bottom-up heuristic for optimal sizing. Experimental results show that this integrated method elegantly solves floorplan optimization problem for general including inherently nonslicible adjacency graphs.

Floorplanning is a key problem in VLSI physical design. The floorplanning problem can be formulated as that a given set of 3D rectangular blocks while minimizing suitable cost functions. Here, we are concentrating on the minimization of the total volume of 3D die. In this paper, first we propose a new topological structure using weighted directed graph of a floorplaning problem in 3D VLSI physical design. But here the main question is this structure is effective or not. For this, we give the idea of a new algorithm to minimize the volume of 3D die in floorplanning problem using this new representation technique. It is interesting to see that our proposed structure is also capable to calculate the total volume and position of the dead spaces if dead spaces exist. Next, we give the experimental result of our new algorithm and then conclude the paper.

Floorplanning is an important problem in very large scale integrated-circuit (VLSI) design automation as it determines the performance, size, yield, and reliability of VLSI chips. From the computational point of view, VLSI floorplanning is an NP-hard problem. Modern very large scale integration technology is based on fixed-outline floorplan constraints, generally with an objective of minimizing area and wirelength between the modules. This survey paper gives an up-to-date account on various metaheuristic algorithms used to solve VLSI floorplanning problem.

ACM Transactions on Design Automation of Electronic Systems, 1996

We present two practical algorithms for partitioning circuit components represented by rectilinear polygons so that they can be stored using the L-shaped corner stitching data structure; that is, our algorithms decompose a simple polygon into a set of nonoverlapping L-shapes and rectangles by using horizontal cuts only. The more general of our algorithms computes an optimal configuration for a wide variety of optimization functions, whereas the other computes a minimum configuration of rectangles and L-shapes. Both algorithms run in O(n ϩ h log h) time, where n is the number of vertices in the polygon and h is the number of H-pairs. Because for VLSI data h is small, in practice these algorithms are linear in n. Experimental results on actual VLSI data compare our algorithms and demonstrate the gains in performance for corner stitching (as measured by different objective functions) obtained by using them instead of more traditional rectangular partitioning algorithms.

IEEE Transactions on Very Large Scale Integration Systems, 2001

Floorplanning is a crucial phase in VLSI physical design. The subsequent placement and routing of the cells/modules are coupled very closely with the quality of the floorplan. A widely used technique for floorplanning is simulated annealing. It gives very good floorplanning results but has major limitation in terms of run time. For circuit sizes exceeding tens of modules simulated annealing is not practical. Floorplanning forms the core of many synthesis applications. Designers need faster prediction of system metrics to quickly evaluate the effects of design changes. Early prediction of metrics is imperative for estimating timing and routability. In this work we propose a constructive technique for predicting floorplan metrics. We show how to modify the existing top-down partitioning-based floorplanning to obtain a fast and accurate floorplan prediction. The prediction gets better as the number of modules and flexibility in the shapes increase. We also explore applicability of the traditional sizing theorem when combining two modules based on their sizes and interconnecting wirelength. Experimental results show that our prediction algorithm can predict the area/length cost function normally within 5-10% of the results obtained by simulated annealing and is, on average, 1000 times faster.

2006

Abstract Large macro blocks, predesigned datapaths, embedded memories, and analog blocks are increasingly used in application-specific integrated circuit (ASIC) designs. However, robust algorithms for large-scale placement of such designs have only recently been considered in the literature. Large macros can be handled by traditional floorplanning, but are harder to account for in min-cut and analytical placement.

Proceedings of 9th International Conference on VLSI Design

W e identify a n e w problem called geometric bipartitioning that is useful in VLSI layout design. Given a floorplan w i t h rectilinear modules, t h e problem is t o partition t h e floor by a staircase (monotone increasing) channel f r o m o n e corner of t h e floor t o its diagonally opposite corner, such that t h e numbers of modules in t h e t w o halves become equal. As the partition is heavily dependent o n t h e geometry of t h e fioorplan, this i s quite different f r o m t h e classical graph bisection problem. This problem can be captured using a weighted permutation graph w i t h integer edge weights, which m a y be positive, negative o r zero; t h e goal is t o find a path between t w o designated nodes such that t h e absolute value of t h e s u m of edge weights along t h e path is minimum. W e t h e n show that this problem is NP-complete, and present a heuristic algorithm based o n branch-andbound. Experimental results w i t h benchmarles and randomly generated floorplans reveal that t h e algorithm produces optimal results quickly m o s t of the time. Geometric bipartitioning problem m a y find m a n y applicat i o n s t o hierarchical decomposition, floorplanning, and routing.

2004

Abstract We propose a new floorplanner BloBB based on multi-level branch-and-bound. It is competitive with annealers in terms of runtime and solution quality. We empirically quantify the gap between optimal slicing and non-slicing floorplans by comparing optimal packings and best seen results. Optimal slicing and non-slicing packings for apte, xerox and hp are reported. We also discover that the soft versions of all MCNC benchmarks, except for apte, and all GSRC benchmarks can be packed with zero dead-space.

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.

Large macro blocks, pre-designed datapaths, embedded memories and analog blocks are increasingly used in ASIC designs. However, robust algorithms for large-scale placement of such designs have only recently been considered in the literature, and improvements by over 10% per paper are still common. Large macros can be handled by traditional floorplanning, but are harder to account for in min-cut and analytical placement. On the other hand, traditional floorplanning techniques do not scale to large numbers of objects, especially in terms of solution quality. We propose to integrate min-cut placement with fixed-outline floorplanning to solve the more general placement problem, which includes cell placement, floorplanning, mixed-size placement and achieving routability. At every step of min-cut placement, either partitioning or wirelength-driven, fixed-outline floorplanning is invoked. If the latter fails, we undo an earlier partitioning decision, merge adjacent placement regions and re-floorplan the larger region to find a legal placement for the macros. Empirically, this framework improves the scalability and quality of results for traditional wirelengthdriven floorplanning. It has been validated on recent designs with embedded memories and accounts for routability. Additionally, we propose that free-shape rectilinear floorplanning can be used with rough module-area estimates before synthesis.

2009 International Conference on Microelectronics - ICM, 2009

A new and efficient heuristic methodology, called Full-and-Elimination (FAE), is proposed to solve the floorplan area minimization problem. This approach is inspired by the game, Tetris . The modules are selected one at a time and placed to the partial floorplan, while attempting to grow on upper, in a row-by-row manner, until all the modules are arranged to the floorplan. In each row, modules are tried to be placed without deadspace. If any row is filled up, this row is viewed as "full" and thus it is "eliminated". The modules are sorted and constructively moved into the partial floorplan. A contour that encloses the top of the packed modules in the floorplan is constructed to help for arrangement of the modules. Experimental results on MCNC and GSRC benchmarks demonstrate that we obtain significant improvements on the area minimization and computational efforts. Particularly, our methodology provides greater improvement over other floorplanners as the number of modules increases, which is a feature of scalability.

International Journal of Engineering and Advanced Technology, 2019

Nowadays in VLSI number of transistors integrated on a single silicon chip is increasing day by day and the complexity of the design is increases tremendously. This makes very difficult for the designer and EDA tools. As number of instances increases the run time and memory for implementing the design increases. This will make more pressure on the designer because if product is not completed within the time to market company will lost so much of money. Floorplanning is the basic building step for any hierarchical physical design flow. Floorplanning is taking more amount of time in entire design hierarchical flow. If floorplanning is not good the entire design will take more time and it will increase a greater number of iterations to complete the design. In the top-level chip planning the quality of the floorplanning depends on the proper alignment of blocks and easy to meet the timing and congestion. To reduce memory size of CPU and run time, in this project we are using a method of...

International Journal of Circuit Theory and Applications, 2013

From the industrial perspective, floorplanning is a crucial step in the VLSI physical design process as its efficiency determines the quality and the time-to-market of the product. A new perturbation method, called Cull-and-Aggregate Bottom-up Floorplanner (CABF), which consists of culling and aggregating stages, is developed to perform variable-order automated floorplanning for VLSI. CABF will generate VLSI floorplan layout by calculating the modules' dimensions' differences (hard module floorplanning problems) and the modules' areas' differences (soft module floorplanning problems). Through mathematical derivation, the hard modules floorplanning area minimization cost function (two-dimensional) during culling stage is proven that a dimensional reduction can be carried out to be the difference-based cost function (one-dimensional) which simplifies the computation. During the culling stage, CABF employs linear ordering method to select and determine the order of modules where this linear runtime complexity property allows CABF to cull the modules faster. The aggregating stage of CABF will reduce the subsequent search space of this floorplanner, and the variable order aggregation enables CABF to search for the best near-optimal solution. Based on Gigascale Systems Research Center and Microelectronics Center of North Carolina circuit benchmarks, CABF gives better optimal solutions and faster runtimes for floorplanning problems involving 9 to 600 modules. This has established that CABF is performing well in respect of reliability and scalability. Besides, CABF shows its potential to be implemented in VLSI physical design as the runtime of CABF is faster with a near-optimal outcome as compared to the other existing algorithms.