Hardware-software cosynthesis for digital systems

1992

The authors formulate the synthesis problem of complex behavioral descriptions with performance constraints as a hardware-software co-design problem. The target system architecture consists of a software component as a program running on a re-programmable processor assisted by application-specific hardware components. System synthesis is performed by first partitioning the input system description into hardware and software portions and then by implementing each of them separately. The synthesis of dedicated hardware is then achieved by means of hardware synthesis tools (D.D. Mitchell, D.C.Ku, F. Mailhot, and T. Truong, `The Olympus Synthesis System for digital design' IEEE Design and Test Magazine, p.37-53, Oct. 1990), while the software component is generated using software compiling techniques. The authors consider the problem of identifying potential hardware and software components of a system described in a high-level modeling language and they present a partitioning procedure. They then describe the results of partitioning a network coprocessor

ABSTRACT This paper describes a parameterizable RISC processor core and its associated co-synthesis environment for embedding mixed hardware/software systems in sea-of-gates integrated circuits. The core is fully configurable so that the program and data memory sizes, the number and size of the I/O ports, the stack size and the number and type of its peripheral blocks can be automatically adjusted to the system requirements.

This article gives a design overview of the new hardware synthesis tool ConPro used for development of applicationspecific digital logic systems providing a high-level approach with imperative programming features filling the gap between hardware and software level. It is an experimental platform for studying different hybrid scheduling strategies, too. The ConPro development tool and programming language guides the user from an algorithmic programmer software view to RTL hardware architecture. Concurrency is explicitly modelled with communicating processes and interprocess communication primitives known from traditional and well-known parallel software development using leight weight processes (threads), like semaphores or mutexes. The process modell provides only a single control path resulting in strict sequential instruction scheduling. Concurrency inside processes is limited to the data path. Beneath explicitly modelled concurrency, automatic exploitation of inherent concurrency is provided by the synthesis compiler using a multi-pass hybrid scheduler.

2010

One of the key problems in complex digital system design is the rapid generation of efficient hardware functionality. The paper introduces an architecture template for targeting FPGA implementations as part of a dataflow based design flow for heterogeneous platforms, thereby allowing a designer to perform system level optimizations for consistent FPGA performance. The architecture provides scalable capabilities in both communications and processing allowing the core to be scaled to the problem size. Matrix ...

Abstract This paper describes a parameterizable RISC processor core developed in the scope of a co-synthesis environment for embedding mixed hardware/software systems in sea-of-gates integrated circuits. The core is fully configurable so that the program and data memory sizes, the number and size of the I/O ports, the stack size and the number and type of its periphera blocks can be automatically adjusted to the system requirements.

2010

Hardware/software co-design has been an area of research for a few decades. Currently co-design is utilized to create hardware coprocessors for compute intensive tasks of a system (which otherwise, performed in software, will not meet the performance goals). Design of correct hardware coprocessors with area, timing and power constraints is a time consuming task. In this paper, we present a methodology to alleviate this problem up to a certain extent. First, we show how to adopt a high-level synthesis tool in design space exploration to converge towards efficient hardware coprocessors. Second, we show, through a series of case studies that, a system-level approach, keeping platform specific optimizations in mind, can help in doing such an exploration efficiently.

[1992 Proceedings] The Third International Workshop on Rapid System Prototyping, 1992

Current state-of-the-art in design automation presents a slew of design aids for low level logic construction, layout planning and chip design. Synthesis, in its various forms, have been a major contribution in the design automation area. Synthesis is an operation whereby a given specification of system behaviour with its associated set of constraints and goals are used to find a suitable structure that implements the behaviour while satisfying the constraints and goals. This paper will present a framework for system level synthesis and propose a suitable laguage for capturing design specifications and generating control graphs amiable to 2ynthesis. Digital system design can be described at different levels of abstraction and synthesis can occur at any one of these design levels. Bell and Newel1 [BEL] first classified the various levels of computer design and a complete representation of the design hierarchy based upon their classification is presented in table 1. Traditional synthesis and design literature defines various forms of synthesis possible between levels [McF]. Although the terminology used may fluctuate in the literature, these levels are typically defined as (in increasing order of abstraction!: i) Logic level, ii) Register transfer level, iii) High level and iv) System level synthesis. It is useful to provide an overview of the different issues at each level.

2005 IEEE International Symposium on Circuits and Systems, 2005

The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper, we present a methodology and a tool that allow the High-Level Synthesis of DSP algorithm, under both I/O timing and memory constraints. Based on formal models and a generic architecture, this tool helps the designer to find a reasonable trade-off between both the required I/O timing behavior and the internal memory access parallelism of the circuit. The interest of our approach is demonstrated on the case study of a FFT algorithm.

Embedded Systems - Theory and Design Methodology, 2012

IEEE Micro, 1994

Our approach to digital system simulation compiles a high-level system model into a highperformance simulator that consists of software and hardware components. The target architecture for the simulation compiler is a tightly coupled processor and fieldprogrammable gate array. We describe the simulation compiler and show how it can be used to improve simulation performance by up to a factor of two over an all-software simulator.

Sixth International Workshop on High-Level Synthesis, 1992

This paper presents Achilles, a High-Level Synthesis System for asynchronous digital circuits. A new architecture model based on a completely distributed control structure is proposed. The most relevant di erences from synthesis systems for synchronous circuits appear in the phases of scheduling and synthesis of the control. Signal Transition Graphs are automatically generated to describe the behavior of local controllers.

2014 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

High-Level Synthesis (HLS) is an automated design process that deals with the generation of behavioral hardware descriptions from high-level algorithmic specifications. The main benefit of this approach is that ever-increasing system-on-chip (SoC) design complexity and ever-shorter time-to-market can still be both manageable and achievable. This advantage, coupled with the increasing number of available heterogeneous platforms that loosely couple general-purpose processors with Field-Programmable Gate Array (FPGA)-based co-processors, led to an increasing attention for HLS tool development and optimization from both the academia as well as the industry. However, in order for HLS to fully reach its potential, it is imperative to look simultaneously at local HLS optimizations as well as to HLS system-level integration and design space exploration issues. In this paper, we present the Delft Workbench tool-chain that takes C-code as input and generates, in a semiautomatic way, a complete system. Subsequently, we describe the design and output code optimization of the DWARV 3.0 HLS compiler using the CoSy compiler framework. Based on this experience, we provide an overview of similarities and differences in leveraging this commercial compiler framework to build a hardware compiler as opposed to building a software compiler. Finally, we report speedups up to 3.72x at application level and development times measurable in hours rather than weeks.

1997

Abstract In this paper we describe a technique for hardwaresoftware co-simulation that is almost cycle-accurate, but does not require the use of interprocess communication nor a C language interface for the software components. Software is modeled by using behavioral VHDL constructs, annotated with timing information derived by basic block-level timing estimates. Execution of the VHDL processes modeling software tasks is coordinated by a process emulating the target RTOS behavior.

16th International Conference on VLSI Design, 2003. Proceedings., 2003

Design of efficient System-on-Chips (SoCs) require thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardware in order to meet the cost as well as the performance constraints. However, faster time to market requires automation of synthesis of these code segments of the application from high level specification such as C alongwith its interfaces. Such synthesis system should be able to generate hardware which is easily plug-gable in various types of architectures, as well as augment the application code to automatically take advantage of this new hardware component. In this paper, we address this problem and present an approach for complete SoC synthesis. We automatically generate synthesizable VHDL for the compute intensive part of the application alongwith necessary interfaces. Our approach is generic in the sense that it supports various processors and buses by keeping a generic hardware interface on one end and a dedicated one on the other. The generated hardware can be used in a tightly or loosely coupled manner in terms of memory and register communication. We present the effectiveness of this approach for some commonly used image processing spatial filter applications.

Proceedings of the 28th ACM/IEEE Design …, 1991

This paper describes a formal technique for automated synthesis of multiprocessor systems for given applications. The application task is specified in terms of a graph, and the architecture synthesized includes a set of processing elements and the interconnection architecture between them. The technique generates a task execution schedule along with the architecture. The technique involves creation of a Mixed Integer-Linear Programming (MILP)model and solution of the model. Synthesis of a few example architectures is reported.