Compilers for Reconfigurable Architectures

Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems - CASES '01, 2001

The rapid growth of silicon densities has made it feasible to deploy reconfigurable hardware as a highly parallel computing platform. However, in most cases, the application needs to be programmed in hardware description or assembly languages, whereas most application programmers are familiar with the algorithmic programming paradigm. SA-C has been proposed as an expression-oriented language designed to implicitly express data parallel operations. Morphosys is a reconfigurable system-on-chip architecture that supports a data-parallel, SIMD computational model. This paper describes a compiler framework to analyze SA-C programs, perform optimizations, and map the application onto the Morphosys architecture. The mapping process involves operation scheduling, resource allocation and binding and register allocation in the context of the Morphosys architecture. The execution times of some compiled image-processing kernels can achieve up to 42x speed-up over an 800 MHz Pentium III machine.

1999

Image processing IP applications feature large, regular image data structures with regular access patterns and therefore can bene t from parallel implementations. The programmable nature of parallel recon gurable computing systems RCSs allows great exibility and promises massive ne-grain parallelism with high throughput. RCSs are therefore interesting candidates for special purpose IP acceleration hardware: they provide a large degree of ne-grained parallelism that can be con gured to e ciently t many simultaneous small-data-size pixel operations. Recon gurable computing systems are typically based on Field Programmable Gate Arrays FPGAs, which are large arrays of programmable logic cells. These systems present new challenges to language designers and compiler writers. The task of programming and compiling applications consists of partitioning the algorithm between a host processor and recon gurable modules, and devising ways of producing e cient FPGA con gurations. Presently, FPGAs are programmed in hardware description languages, such as VHDL or Verilog. While such languages are suitable for chip design, they are poorly suited for the kind of algorithmic expression that takes place in IP programming. The programming language SA-C, developed as part of the Cameron Project 1 , is designed to provide high level, algorithmic language support for RCSs, allowing applications experts, rather than only hardware experts, to reap the bene ts of these systems. This paper introduces SA-C, its optimizing compiler that generates data ow graphs DFGs, and the mapping of the DFGs to recon gurable systems.

2010

Abstract Reconfigurable computing platforms offer the promise of substantially accelerating computations through the concurrent nature of hardware structures and the ability of these architectures for hardware customization.

Parallel …, 1999

This paper presents the Cameron Project 1 , which aims to provide a high level, algorithmic language and optimizing compiler for the development of image processing applications on Reconfigurable Computing Systems (RCSs). SA-C, a single assignment variant of the C programming language, is designed to exploit both coarse-grain and fine-grain parallelism in image processing applications. Khoros, a software development environment commonly used for image processing, has been modified to support SA-C program development.

2017

This work describes the implementation of a compiler for Versat, a Coarse Grained Reconfigurable Array (CGRA). Before this work, Versat was only programmable in its assembly language. The developed compiler uses a simple and high-level Intermediate Representation (IR), contrasting with the complex and low-level IR found in compiler frameworks such as GCC or LLVM. Our IR is more easily translated into hardware datapaths, which are mapped to Versat partial reconfiguration instructions. The language syntax is a small subset of the C++ language, for the compiler is used only for sequences of loop nests containing operations on data arrays, as found in the target applications: digital filters, transforms and big data algorithms such as deep learning and k-means clustering. Experimental results show fast compilation time, and code size / execution time similar to handwritten assembly code.

Field-Programmable Logic …, 2002

In addition to high performance requirements, future generation mobile telecommunications brings new constraints to the semiconductor design world. In order to associate the flexibility to the highperformances and the low-energy consumption needed by this application domain we have developed a functional level dynamically reconfigurable architecture, DART. Even if this architecture supports the processing complexity of the UMTS while allowing the portability of the devices and their evolutions, another challenge is to develop efficient high-level design tools. In this paper, we discuss about a methodology allowing the definition of such development tool based on the joint used of compilation and behavioral synthesis schemes.

Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186)

ACM Transactions on Embedded Computing Systems, 2003

The rapid growth of device densities on silicon has made it feasible to deploy reconfigurable hardware as a highly parallel computing platform. However, one of the obstacles to the wider acceptance of this technology is its programmability. The application needs to be programmed in hardware description languages or an assembly equivalent, whereas most application programmers are used to the algorithmic programming paradigm. SA-C has been proposed as an expression-oriented language designed to implicitly express data parallel operations. The Morphosys project proposes an SoC architecture consisting of reconfigurable hardware that supports a data-parallel, SIMD computational model. This paper describes a compiler framework to analyze SA-C programs, perform optimizations, and automatically map the application onto the Morphosys architecture. The mapping process is static and it involves operation scheduling, processor allocation and binding, and register allocation in the context of the Morphosys architecture. The compiler also handles issues concerning data streaming and caching in order to minimize data transfer overhead. We have compiled some important image-processing kernels, and the generated schedules reflect an average speedup in execution times of up to 6× compared to the execution on 800 MHz Pentium III machines.

2008 Canadian Conference on Electrical and Computer Engineering, 2008

In this paper a novel approach for compiling parallel applications to a target Coarse-Grained Reconfigurable Architecture (CGRA) is presented. We have given a formal definition of the compilation problem for the CGRA. The application will be written in HARPO/L, a parallel object oriented language suitable for hardware. HARPO/L is first compiled to a Data Flow Graph (DFG) representation. The remaining compilation steps are a combination of three tasks: scheduling, placement and routing. For compiling cyclic portions of the application, we have adapted a modulo scheduling algorithm: modulo scheduling with integrated register spilling. For scheduling, the nodes of the DFG are ordered using the hypernode reduction modulo scheduling (HRMS) method. The placement and routing is done using the neighborhood relations of the PEs.

2012

Abstract The development of applications for high-performance Field Programmable Gate Array (FPGA) based embedded systems is a long and error-prone process. Typically, developers need to be deeply involved in all the stages of the translation and optimization of an application described in a high-level programming language to a lower-level design description to ensure the solution meets the required functionality and performance.