Hardware/Software Co-Design Using Bayesian Belief Networks

ACM Transactions on Design Automation of Electronic Systems, 2003

This paper presents an in-depth study of several system partitioning procedures. It is based on the appropriate formulation of a general system model, being therefore independent of either the particular co-design problem or the specific partitioning procedure. The techniques under study are a knowledge-based system and three classical circuit partitioning algorithms (Simulated Annealing, Kernighan&Lin and Hierarchical Clustering). The former has been entirely proposed by the authors in previous works while the later have been properly extended to deal with system level issues. We will show how the way the problem is solved biases the results obtained, regarding both quality and convergence rate. Consequently it is extremely important to choose the most suitable technique for the particular co-design problem that is being confronted.

IJCA Proceedings on National …, 2012

Circuit partitioning problem is a well known NP hard problem. The potential of Genetic Algorithm has been used to solve many computationally intensive problems (NP hard problems) because existing conventional methods are unable to perform the required breakthrough in terms of complexity, time and cost. The presented work deals with the problem of partitioning of a circuit using Genetic Algorithm. The program inputs the adjacency matrix, generates graph of the circuit and partitions the circuit based on crossover operator. The program produces a set of vertices that are highly connected to each other but highly disconnected from the other partitions.

Computación Y Sistemas, 2013

Hardware/Software partitioning (HSP) is a key task for embedded system co-design. The main goal of this task is to decide which components of an application are to be executed in a general purpose processor (software) and which ones, on a specific hardware, taking into account a set of restrictions expressed by metrics. In last years, several approaches have been proposed for solving the HSP problem, directed by metaheuristic algorithms. However, due to diversity of models and metrics used, the choice of the best suited algorithm is an open problem yet. This article presents the results of applying a fuzzy approach to the HSP problem. This approach is more flexible than many others due to the fact that it is possible to accept quite good solutions or to reject other ones which do not seem good. In this work we compare six metaheuristic algorithms: Random Search, Tabu Search, Simulated Annealing, Hill Climbing, Genetic Algorithm and Evolutionary Strategy. The presented model is aimed to simultaneously minimize the hardware area and the execution time. The obtained results show that Restart Hill Climbing is the best performing algorithm in most cases.

Energy Procedia, 2011

This paper presents an approach based on hardware/software partitioning to minimize the logic area of System on a Programmable Chip (SOPC) while respecting a time constraint. Our contribution focuses on introducing a new hardware/software partitioning algorithm. This algorithm is based on the principle of Binary Search Trees (BST) and genetic algorithms. It aims to define the tasks that will run on the Hardware (HW) part and those that will run on the Software (SW) part. The proposed algorithm will determine the best partition that will reduce the number of tasks used by the HW and increase the number of tasks used by the SW and thereafter the area will be reduced. The results show that our algorithm significantly reduces the logic area compared to other well known algorithms.

2020

Key words: The relevance of VLSI in performance computing, telecommunications, and consumer electronics has been expanding progressively, and at a very hasty pace. In order to build complex digital logic circuits it is often essential to sub-divide multi -million transistors design into manageable pieces. Circuit partitioning is a general approach used to solve problems that are too large and complex to be handled at once. In partitioning, the problem is divided into small and manageable parts recursively, until the required complexity level is reached. In the area of VLSI, circuit complexity is rapidly multiplying, together with the reducing chip sizes; the integrated chips being produced today are highly sophisticated. There are many diverse problems that occur during the development phase of an IC that can be solved by using circuit partitioning which aims at obtaining the sub circuits with minimum interconnections between them. This paper aims at circuit partitioning using clust...

Applied Intelligence, 1999

Hardware-software co-design addresses the development of complex heterogeneous systems looking for the best tradeoffs among the different solutions. The basic idea is to combine the hardware and software design cycles. This article shows how knowledge-based techniques can be used to solve the hardware-software partitioning problem, the co-design task that makes the decision on the best implementation of the different components of a digital system. In particular, a fuzzy-logic-based expert system, SHAPES, has been developed based on the CommonKADS methodology. This tool takes advantage of two important artificial intelligence bases: the use of an expert's knowledge in the decision-making process and the possibility of dealing with imprecise and usually uncertain values by the definition of fuzzy magnitudes.

ACM Transactions on Design Automation of Electronic Systems, 2003

This paper presents an in-depth study of several system partitioning procedures. It is based on the appropriate formulation of a general system model, being therefore independent of either the particular co-design problem or the specific partitioning procedure. The techniques under study are a knowledge-based system and three classical circuit partitioning algorithms (Simulated Annealing, Kernighan&Lin and Hierarchical Clustering). The former has been entirely proposed by the authors in previous works while the later have been properly extended to deal with system level issues. We will show how the way the problem is solved biases the results obtained, regarding both quality and convergence rate. Consequently it is extremely important to choose the most suitable technique for the particular co-design problem that is being confronted.

ijcee.org

In this paper multiway circuit partitioning of circuits using Genetic Algorithms has been attempted. Due to the random search, inherent parallelism, and robustness of genetic algorithms, the solution of a circuit partitioning problem is global optimum. Results obtained show the versatility of the proposed method in solving NP hard problems like circuit partitioning. Results obtained show an improvement over the results of UCLA Branch and Bound partitioner [27]. Information of the circuit has been given in accordance with circuit netlist files used in ISPD'98 circuit benchmark suite.

Scientific Reports, 2016

Belief networks represent a powerful approach to problems involving probabilistic inference, but much of the work in this area is software based utilizing standard deterministic hardware based on the transistor which provides the gain and directionality needed to interconnect billions of them into useful networks. This paper proposes a transistor like device that could provide an analogous building block for probabilistic networks. We present two proof-of-concept examples of belief networks, one reciprocal and one non-reciprocal, implemented using the proposed device which is simulated using experimentally benchmarked models.

International Journal on Intelligent Electronic Systems

The relevance of VLSI in performance computing, telecommunications, and consumer electronics has been expanding progressively, and at a very hasty pace. In order to build complex digital logic circuits it is often essential to subdivide multi-million transistors design into manageable pieces. Circuit partitioning is a general approach used to solve problems that are too large and complex to be handled at once. In partitioning, the problem is divided into small and manageable parts recursively, until the required complexity level is reached. In the area of VLSI, circuit complexity is rapidly multiplying, together with the reducing chip sizes; the integrated chips being produced today are highly sophisticated. There are many diverse problems that occur during the development phase of an IC that can be solved by using circuit partitioning which aims at obtaining the sub circuits with minimum interconnections between them. This paper aims at circuit partitioning using clustering technique by applying two clustering algorithms K-Means and PAM(Partitioning around mediods). These two algorithms were tested on a BCD to Seven Segment Code Converter circuit consisting of eight nodes and also were tested on a circuit consisting of 15 nodes. The two algorithms were implemented on VHDL. The tested results show that PAM yield better subcircuits than K-Means.

2003

This paper proposes ‘CIRPART’ – architecture for implementing Hybrid Genetic Algorithm (GA) used for circuit Multiway Partitioning in VLSI physical design automation. CIRPART applies Hybrid Genetic Algorithm to considerably reduce the number of generations required. CIRPART provides flexibility and also achieves speedups over software based GA. CIRPART achieves more than 100x improvement in processing speed as compared to the software implementation.

2007

Partitioning is a critical area of VLSI CAD. In order to build complex digital logic circuits its often essential to sub-divide multi -million transistor design into manageable Pieces. This paper looks at the various partitioning techniques aspects of VLSI CAD, targeted at various applications. We proposed an evolutionary time- series model and a statistical glitch prediction system using a neural network with selection of global feature by making use of clustering method model, for partitioning a circuit. For evolutionary time-series model, we made use of genetic, memetic & neuro-memetic techniques. Our work focused in use of clustering methods - K- means & EM methodology. A comparative study is provided for all techniques to solve the problem of circuit partitioning pertaining to VLSI design. The performance of all approaches is compared using benchmark data provided by MCNC standard cell placement benchmark net lists. Analysis of the investigational results proved that the Neuro-...

Computational Optimization and Applications, 2002

As general-purpose parallel computers are increasingly being used to speed up different VLSI applications, the development of parallel algorithms for circuit testing, logic minimization and simulation, HDL-based synthesis, etc. is currently a field of increasing research activity. This paper describes a circuit partitioning algorithm which mixes Simulated Annealing (SA) and Tabu Search (TS) heuristics. The goal of such an algorithm is to obtain a balanced distribution of the target circuit among the processors of the multicomputer allowing a parallel CAD application for Test Pattern Generation to provide good efficiency. The results obtained indicate that the proposed algorithm outperforms both a pure Simulated Annealing and a Tabu Search. Moreover, the usefulness of the algorithm in providing a balanced workload distribution is demonstrated by the efficiency results obtained by a topological partitioning parallel test-pattern generator in which the proposed algorithm has been included. An extented algorithm that works with general graphs to compare our approach with other state of the art algorithms has been also included.

Mathematical Journal of Interdisciplinary Sciences, 2014

Decompositions of interconnected components, to achieve modular independence, poses the major problem in VLSI circuit partitioning. This problem is intractable in nature, Solutions of these problem in computational science is possible through appropriate heuristics. Reduction of cost that occurs due to interconnectivity between several VLSI components is referred in this paper. Modification of results derived by classical iterative procedures with probabilistic methods is attempted. Verification has been done on ISCAS-85 benchmark circuits. The proposed design tool shows remarkable improvement result in comparison to the traditional one, when applied to the standard benchmark circuits like ISCAS-85.

Bulletin of Electrical Engineering and Informatics, 2021

This study discusses hardware-software partitioning, which is useful for system-on-chip (SoC) applications. Hardware-software partitioning attempts to obtain the lowest execution time by combining a hardware processor system and a field programmable gate array on the SoC platform in embedded system applications. A three-level hybrid algorithm called GAGAPSO is proposed in this study. The algorithm consists of two successive genetic algorithms (GAs) and one particle swarm optimization (PSO). The drawbacks of these two algorithms are GA has low convergence speed and PSO has premature convergence because of low diversity. These algorithms are combined in this study to achieve high-capacity global convergence and enhanced search efficiency. In this study, three algorithms are developed, namely, GA, GAPSO and GAGAPSO using MATLAB. These algorithms are evaluated on the basis of the number of nodes and the minimum cost that can be achieved. The number of nodes varies from 10 to 1000 nodes. The minimum cost and the number of iterations to achieve the minimum cost are recorded. Results show that GAGAPSO can converge faster than GA and GAPSO. Furthermore, GAGAPSO can achieve the lowest cost for all nodes.