Use of short-loop electrical measurements for yield improvement

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000

As semiconductor technology advances into the nanoscale era and more functional blocks are added into systemson-chip, the interface between circuit design and manufacturing is becoming blurred. An increasing number of features, traditionally ignored by designers, are influencing both circuit performance and yield. As a result, design tools need to incorporate new factors. One important source of circuit-performance degradation comes from deterministic within-die variation from lithography imperfections and Cu-interconnect chemical-mechanical polishing (CMP). To determine how these within-die variations impact circuit performance, we need a new analysis tool. Thus, we have proposed a methodology to involve layout-dependent within-die variations in static timing analysis. Our methodology combines a set of scripts and commercial tools to analyze a full chip. The tool has been applied to analyze delay of ISCAS85 benchmark circuits in the presence of imperfect lithography and CMP variation.

IEEE Transactions on Semiconductor Manufacturing, 1995

The results of a worldwide study on yield improvement are presented. Die yields collected from 21 fabs are transformed via a logit formula and compared. The die yields and die yield improvement rates of the fabs are compared, and manufacturing yield improvement practices are evaluated. Preliminary results of this continuing study indicate that die yield improvement is a function of computer-aided manufacturing practices and statistical process control practices in addition to commonly cited practices such as particle control and advanced manufacturing technology.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2011

Modeling spatial variation is important for statistical analysis. Most existing works model spatial variation as spatially correlated random variables. We discuss process origins of spatial variability, all of which indicate that spatial variation comes from deterministic across-wafer variation, and purely random spatial variation is not significant. We analytically study the impact of across-wafer variation and show how it gives an appearance of correlation. We have developed a new die-level variation model considering deterministic across-wafer variation and derived the range of conditions under which ignoring spatial variation altogether may be acceptable. Experimental results show that for statistical timing and leakage analysis, our model is within 2% and 5% error from exact simulation result, respectively, while the error of the existing distance-based spatial variation model is up to 6.5% and 17%, respectively. Moreover, our new model is also 6× faster than the spatial variation model for statistical timing analysis and 7× faster for statistical leakage analysis.

This work reconsiders within-wafer non-uniformity (WIWNU) metrics for semiconductor processes. Simulations of typical chemical-mechanical polishing (CMP) scenarios are used to demonstrate that these metrics may vary with the pre-process thickness profile, the removal rate characteristics, and processing time. These metrics are compared and contrasted. Some of these metrics are shown to be biased with processing time, while others are shown to be insensitive to improvements in WIWNU. Finally, experimental data is compared with these simulations. It is suggested that multiple metrics may be necessary to determine the actual characteristics of a process.

Photomask and Next-Generation Lithography Mask Technology XX, 2013

We describe SEMATECH's recent defect printability work categorizing native phase defects by type and dimension using a NXE3100 EUV scanner and DPS (Defect Printability Simulator) software developed by Luminescent Technologies. Since the critical dimension (CD) error on a wafer simulated by the DPS is strongly affected by the multilayer (ML) geometry, it was very important to select the optimal multilayer (ML) growth model for each defect. By investigating the CD results obtained from 27 nm HP node imaging on NXE3100 and comparing those with simulation results, it was clear that reconstructed ML geometry generated by the AFM measurement showed much better simulation accuracy than conformal ML geometry. In order to find a typical ML growth model to predict the best ML geometry for a given dimension and height of defect, we calibrated a general ML growth model with AFM data and obtained ML growth model parameters. Using the fitted ML geometry generated from ML growth model parameters, CD error for 22 nm HP node was simulated and the result showed that conformal ML geometry is good for 24 nm defect simulation while not appropriate for 36 nm defect simulation. Downloaded From: http://proceedings.spiedigitallibrary.org/ on 09/16/2013 Terms of Use: http://spiedl.org/terms Proc. of SPIE Vol. 8701 870111-6 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 09/16/2013 Terms of Use: http://spiedl.org/terms

IEEE Design & Test of Computers, 2004

TODAY'S SEMICONDUCTOR fabrication processes for nanometer technology allow the creation of very high-density and high-speed SoCs. Unfortunately, this results in defect susceptibility levels that reduce process yield and reliability. This lengthens the production ramp-up period and hence affects profitability. The impact of nanometer technology on yield and reliability creates a dilemma for users of the conventional chip realization flow. Each chip realization phase affects manufacturing yield and field reliability. To optimize yield and reach acceptable reliability levels, the industry uses advanced optimization solutions, designed in and leveraged at different phases of the chip realization flow. Recognizing the importance of this topic, IEEE Design & Test has dedicated this special issue to design for yield and reliability solutions.

2016

Any manufacturing process has natural variations, even when it remains within its control limits. Inevitable fluctuations in the manufacturing processes and environmental operating conditions of the integrated circuits cause circuit parameters to vary randomly about their nominal target value. The concept of parametric yield loss of ICs arises because of the design intolerance to these variations. Such losses are due to the effects such as mask mis-alignments and implant dose variations over a whole lot of wafer and dice. It can be distinguished from catastrophic yield loss, which is loss due to local effects such as dust particles. The global effect in turn induces variations in process parameters such as sheet resistance of the MOSFET oxide, Capacitance Cox and threshold voltage VT that lead to different instances of the IC having different performance, see O’Leary (1995). Many methods have been used to predict parametric yield of Analog Ics, see Becker and Jensen (1977), Elias (1...

IEEE Transactions on Semiconductor Manufacturing, 2001

This paper describes the steps used in addressing a final visual yield loss in a Compound Semiconductor process. These visual defects also have some electrical as well as assembly implications associated with them, thus they cannot be easily dismissed. Using a structured approach to problem solving and by isolating the device and defect types, studying the process flow, performing is/is not analysis as well as using quality tools such infinity diagrams and inter-relationship diagraphs helped in identifying the phenomena which resulted in identifying key process improvements that led to recovering the yield loss.

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168), 1998

1997

In this paper we present an experimental methodology for parametric yield estimation that accounts for spatial correlations between features of the same device at specific wafer locations. Each device feature is representative of a device parameter that must fit with a specific tolerance box and may be influenced by several steps of the manufacturing process. If the process how is known and each of its steps is characterized in a spatially correlated manner, the feature pointwise probability density functions (PDFs) can be accurately reconstructed from the processing step pointwise PDFs. This method thus permits the estimation of pointwise device yield more accurately than the common multilevel (run, wafer, die) averaging approach. Because spatially correlated phenomena is subject to both random and systematic nonuniformities, the pointwise step (PDFs) are determined by a decomposition process that separates the systematic and random error components. The systematic PDFs are determined from interpolation functions representing the spatial variations across the entire wafer lot, and the random PDFs are approximated using a combination of principle component analysis and factor analysis with a few uncorrelated random variables valid for the entire lot.

A major element of the CSM program is to survey world-wide fabrication performance and managerial practices. This report summarizes findings from benchmarking ten manufacturing facilities processing eight-inch silicon wafers to fabricate digital devices with feature sizes of 350nm and smaller. All of these fabrication plants were constructed in the 1993 -1996 time frame. Performance data were collected from each participant for some or all of the time frame 1996 -2000. The individual identities of the participants are confidential. Sponsors of this survey include SEMATECH, the Electronics Industry Association of Japan, the Semiconductor Research Institute of Japan, Taiwan Semiconductor Manufacturing Corp., United Microelectronics Corp., Winbond Electronics, Samsung Electronics Corp., Micrus, Inc., Cypress Semiconductor, and ST Microelectronics. The survey was conducted without oversight or direction of the sponsors, and the conclusions expressed herein are not necessarily consistent with the views of any sponsor. Fabrication benchmarks presented in this report include the following: * Fabrication line yield per twenty layers; * Defect density (accounting for all die yield losses, whether random or systematic) for 500, 350 and 250nm memory and logic CMS process technologies; * Integrated yield (line yield times die yield for a 0.5 cm 2 device with 20 layers) for each of the above technology generations; * Stepper throughput; * Integrated stepper throughput (integrated yield times stepper throughput); 3 * Productivity of clean room floor space; * Productivity of direct labor and of total facility workforce; * Fabrication cycle time per mask layer; * Time required for process development and qualification in the mass production facility; and * Time required process qualification until mature die yield is attained.

IEEE Design & Test of Computers, 2010

The cost and cycle time for determining the root cause of yield loss continues to increase as semiconductor technology scales down. A new technique, Axiom, helps yield and product engineers determine the root cause of loss directly from diagnosis results. Consequently, root-cause cycle time is dramatically reduced, resulting in a higher physical-failure analysis success rate and reduced costs.

2013 Winter Simulations Conference (WSC), 2013

Fab operations management strives to decrease cycle-time (CT) for driving low inventory, improved quality, short time-to-market and lower cost. This work studies factors contributing to production variability, and evaluates the variability's influence on CT. It relies on queueing networks, CT and variability approximations, operational curve modeling, and common practice. It demonstrates that increasing variability drives longer CT at a growing pace, and has a larger effect on CT than utilization. Growing machine inventory weakens the impact of utilization on CT and almost eliminates it at high inventory, while the impact of variability on CT remains significant. Decline of machine availability prolongs CT at a growing pace, and is affected by variability more than utilization. Overall the primary factor of production variability is attributed to machine availability, and specifically to repair time. Reducing variability for achieving decreased CT is less costly and more effective than reducing machine utilization or increasing capacity.

Semiconductor International, 2006