A Proposed Novel Description Language in Digital System Modeling

IEEE Transactions on Industrial electronics, 1999

1992

A framework for system level synthesis is presented, and a suitable language, DSL, for capturing design specifications and generating control graphs amiable to synthesis is proposed. The three stages in the synthesis process-design specification, intermediate representation, and synthesis-are examined in detail. A rough version of the language is used to model a simple system

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1994

Energy Systems in Electrical Engineering, 2020

Over the years, a rapid growth has been witnessed in electronics semiconductor industry because of the huge demand for system-level designs. System-level designs are prominently used for various applications such as high-performance computing, controls, telecommunications, image and video processing, consumer electronics and others. Hence to accomplish such applications using very largescale integration (VLSI) design, it is recommended to have an efficient registertransfer-level (RTL) design abstraction, as it can provide a low power and highperformance outcome (Wu and Liu in IEEE Trans Very Large Scale Integr (VLSI) Syst 6:707-718, Wu and Liu 1998). In digital integrated circuit (IC) design, RTL models a synchronous digital circuit in terms of the flow of digital signals or data between hardware registers and the logical operations performed on these signals. RTL abstraction is used in hardware description languages (HDLs) to create highlevel representations of a circuit (Chinedu et al. in 3rd IEEE international conference on adaptive science and technology (ICAST 2011). IEEE, pp 262-267, Chinedu et al. 2011). From these lower-level representations, ultimately actual circuitry can be derived. Design at the RTL level is a typical practice in modern digital system designs. This chapter mainly focuses on design of RTLs for application-specific integrated circuits (ASICs) and how it differs for field-programmable gate arrays (FPGAs). The examples and modules discussed in this chapter are written in HDL, viz. Verilog language.

Microelectronics Journal, 2015

Due to the rapid technology advancement in integrated circuit era, the need for the high computation performance together with increasing complexity and manufacturing costs has raised the demand for high-performance configurable designs; therefore, the Application-Specific Instruction Set Processors (ASIPs) are widely used in SoC design. The automated generation of software tools for ASIPs is a commonly used technique, but the automated hardware model generation is less frequently applied in terms of final RTL implementations. Contrary to this, the final register-transfer level models are usually created, at least partly, manually. This paper presents a novel approach for automated hardware model generation for ASIPs. The new solution is based on a novel abstract ASIP model and a modeling language (Algorithmic Microarchitecture Description Language, AMDL) optimized for this architecture model. The proposed AMDL-based pre-synthesis method is based on a set of pre-defined VHDL implementation schemes, which ensure the qualities of the automatically generated register-transfer level models in terms of resource requirement and operation frequency. The design framework implementing the algorithms required by the synthesis method is also presented. & 2015 Elsevier Ltd. All rights reserved. than the general purpose microprocessors [2,3]. Due to the rigorous time-to-market requirements, reducing the time-consumption of ASIP design is essential. The primary design tools of ASIPs are the Architecture Description Languages (ADLs), which are specific modeling tools for instruction sets and microarchitecture. The design frameworks based on these formal language Contents lists available at ScienceDirect

Proceedings of The IEEE, 1990

Digital signal processing (DSP) is a rapidly growing discipline as VLSl technology makes real-time digital algorithms for speech, audio, image processing, video, and control systems economically feasible. Due to the competitiveness of the application field, cutting design time is a key issue for DSP. Silicon compilation is a way to achieve this. In this paper the state of the art of compiling DSP algorithms into silicon is discussed. First it is indicated how digital signal processing differs from numerical data processing, including the consequences on the synthesis tools. Unlike compilers generating general-purpose microprocessors, DSP synthesis requires tools for analysis, optimization and simulation of the bittrue behavior of the algorithm at the highest level. An applicative input language for specifying the behavior of DSP systems is advocated. Based on a wide span of DSP applications, four classes of architectures are distinguished to serve as templates for four different synthesis systems. Although each of these four silicon compilers is tuned to a specific class of applications in order to generate area-efficient chips, they all accept as input the same behavioural DSP specification. The four selected architectural styles are best characterized by the following keywords: hard-wired bitserial data-paths, microcoded multiprocessors, cooperating bitparallel data-paths and, finally, regular arrays. Each of the CATHEDRAL compilers is based on a mixture of knowledge-based architecture generation techniques and algorithmic optimizations. Silicon is generated from technology-updatable libraries of primitive cells, by means of structured module-generators or by using a standard-cell design system. Attention is paid to the assembly of test patterns for the synthesized chips. The CATHE- DRAL programs support interactive synthesis for the four abovementioned architectures, all the way from the applicative bit-true specification to silicon. For each compiler the design trajectory starting from a high-level specification down to layout is analyzed in the paper. Each of the CArHEDRALs and their underlying methodology is illustrated with the complete design of a representative example.

2008

This paper presents BURAQ, a DSP development framework, which aims at optimizing cost, efficiency and turn around time of System-On-Chip development. BURAQ accepts an Instruction and Architecture description (IAD) file that represents the DSP and its instruction set at a higher level of abstraction, in a proprietary language. The system then synthesizes a complete hardware description of the processor core, along with accompanying tools i.e. ILP Assembler, Linker and Instruction Set Simulator. The synthesized processor core is composed of a processor kernel, registers, addressing units and functional units. A user friendly IDE for the above mentioned framework has also been developed and it allows easy specification and detailed analysis of the target architecture. Hence BURAQ allows a platform for hardware/software Co-Simulation of a DSP. Co-Simulation is a very powerful tool for early design space exploration and thus reducing production cost and development time of SOC architectu...

International Conference on Acoustics, Speech, and Signal Processing

In this paper, we introduce a novel approach for high level syn-Lhesis for DSP algorithms. Two features are provided by the approach: completeness and correctness. A given algorithm will be represented in a new developed language termed Algorithm Specification Language (ASL). ASL has the abilit,y to describe any general algorithm. An automatic procedure is used to transform an ASL representation into a specific realization specification using a correctness preserving set of transformations. The realization format is based on representing the digital architectures by another developed language called Realization Specification Language(RSL). Logic Programming is used as a user interface for the synthesis procedure.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990

Abslracl-The process by which computer systems are designed and implemented has become a topic of considerable interest in recent years. Work in this area includes techniques for the automatic generation and optimization of microcode, synthesis of datapaths and control units, and machine description and simulation tools. An important aspect of these efforts i s the use of one or more models of the machine as the basis for the design system. The adequacy and generality of these models becomes particularly important when the design system i s to be useful for several types of machines (i.e., is retargetable) and across several abstraction levels (i.e., is multilevel). As a result of this desire for retargetable and multilevel capabilities, investigations have also been carried out on the design of models of computer architecture.

Proceedings of IEEE Workshop on VLSI Signal Processing

This paper describes how a modular machine description, which speci es the functionality and the binary representation of an instruction set, can be transformed into a hardware model. This model is built from few generic hardware entities (registers, memories, arithmetic/logic operators, selectors and connections) and may e v entually serve as an input to high-level hardware synthesis tools. The transformation steps on the way from the machine description to the hardware model are explained by giving an example.