Reversible Logic Synthesis

Proc. RM, 2001

Logic synthesis for reversible logic differs considerably from standard logic synthesis. The gates are multi-output and the unutilized outputs from these gates are called "garbage". One of the synthesis tasks is to reduce the number of garbage signals. Previous approaches to reversible logic synthesis minimized either only the garbage or (predominantly) the number of gates. Here we present for the first time a method that minimizes concurrently the number of gates, their total delay and the total garbage. Our method adopts for reversible logic many ideas developed previously for standard logic synthesis (such as Ashenhurst/Curtis Decomposition, Dietmeyer's Composition, non-linear preprocessing for BDDs), methods created in Reed-Muller Logic (such as Pseudo-Kronecker Decision Diagrams with Complemented Edges, Pseudo-Kronecker Lattice Diagrams and their generalizations) and introduces also new methods specific to reversible logic.

2004

Reversible logic has applications in many fields, including quantum computing. Synthesis techniques for reversible circuits are not well developed, even for functions with a small number of inputs and outputs. This paper proposes an approach to reversible logic synthesis using a new complexity measure based on shared binary decision diagrams with complemented edges (instead of truth tables or PPRM forms, as in the previous algorithms). The approach can be used with arbitrary libraries of reversible logic gates and arbitrary cost functions. Experiments show promising results in comparison with the known approaches.

2006 IEEE International Conference on Evolutionary Computation, 2006

This paper presents a constructive synthesis algorithm for any n-qubit reversible function. Given any nqubit reversible function, there are N distinct input patterns different from their corresponding outputs, where N ≤ 2 n , and the other (2 n − N) input patterns will be the same as their outputs. We show that this circuit can be synthesized by at most 2n • N '(n − 1)'-CNOT gates and 4n 2 • N NOT gates. The time complexity of our algorithm has asymptotic upper bound O(n • 4 n). The space complexity of our synthesis algorithm is also O(n • 2 n). The computational complexity of our synthesis algorithm is exponentially lower than the complexity of breadthfirst search based synthesis algorithm.

International Workshop on Logic …, 2002

A reversible circuit maps each output vector into a unique input vector, and vice versa. CMOS reversible / adiabatic circuits are currently the most important approaches to power optimization. This paper introduces an approach to synthesize generalized multi-rail reversible cascades for singleoutput Boolean functions. Minimizing the "garbage bits" is the main challenge of reversible logic synthesis. Experimental results over a set of single output functions (derived from Espresso PLAs) will be presented at IWLS 2002.

Applied Logic Series, 2008

Advances in Electrical and Electronic Engineering, 2014

Reversible logic circuits have been historically motivated by theoretical research in low-power, and recently attracted interest as components of the quantum algorithm, optical computing and nanotechnology. However due to the intrinsic property of reversible logic, traditional irreversible logic design and synthesis methods cannot be carried out. Thus a new set of algorithms are developed correctly to synthesize reversible logic circuit. This paper presents a comprehensive literature review with comparative study on heuristic based reversible logic synthesis. It reviews a range of heuristic based reversible logic synthesis techniques reported by researchers (BDD-based, cycle-based, search-based, non-search-based, rule-based, transformation-based, and ESOP-based). All techniques are described in detail and summarized in a table based on their features, limitation, library used and their consideration metric. Benchmark comparison of gate count and quantum cost are analysed for each synthesis technique. Comparing the synthesis algorithm outputs over the years, it can be observed that different approach has been used for the synthesis of reversible circuit. However, the improvements are not significant. Quantum cost and gate count has improved over the years, but arguments and debates are still on certain issues such as the issue of garbage outputs that remain the same. This paper provides the information of all heuristic based synthesis of reversible logic method proposed over the years. All techniques are explained in detail and thus informative for new reversible logic researchers and bridging the knowledge gap in this area.

2009

Synthesis of reversible logic has received significant attention in the recent years and many synthesis approaches for reversible logic have been proposed so far. In this paper, a librarybased synthesis approach for reversible circuits is proposed where an input specification is considered as a permutation comprising a set of cycles. In order to synthesize a given permutation, a library which contains seven building blocks is used where each building block is a cycle of length less than 6. We also propose a decomposition algorithm which produces all possible minimal and inequivalent factorizations for a given cycle of length greater than 5. All decompositions contain the maximum number of disjoint cycles. The generated decompositions are used in conjunction with a cycle assignment algorithm which is proposed based on the graph matching problem to select the best possible cycle pairs. Then, each pair is synthesized by using the available components of the library. The decomposition a...

In order to discuss new trends and projects in the area of reversible logic one must first have an understanding of what this is. First of all, we'll restrict our discussion of logic functions to two-valued functions describing switching logic. Reversible multiple-valued functions are also possible, but are beyond the scope of this report. We will be discussing functions that describe Boolean logic circuits. These functions are generally built using logic gates. According to Shende et. al.[16],

2005

This report provides an overview of the current state of reversible sequential logic. We assume that the reader has a basic knowledge of reversible logic. An overview of necessary information is provided in [1]. Most research in reversible logic has concentrated on synthesis techniques for combinational logic. Sequential logic synthesis requires the incorporation of memory cells and feedback in a circuit, which seems to violate the definition of reversible logic.