Academia.edu no longer supports Internet Explorer.
To browse Academia.edu and the wider internet faster and more securely, please take a few seconds to upgrade your browser.
2009
In this paper we propose a study of properties of SAT (satisfiability) instances produced by SAT-based Automatic Test Pattern Generators (ATPGs). Standard non-commercial SAT solvers are being widely used for the purpose of solving these instances. We show an analysis of properties of these special SAT instances. Even though these ATPG SAT instances have been thoroughly studied in the past, we show some newly found properties. Particularly, reasons why ATPG SAT instances are ‘easy to be solved’ are shown by analysis of the SAT instances. Then, unexpected behavior of ATPG SAT instances, in terms of their satisfiability, was observed. Next, we propose solution-preserving SAT transformations and study the properties of the reduced SAT instances.
2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC), 2009
Due to ever increasing design sizes more efficient tools for Automatic Test Pattern Generation (ATPG) are needed. The application of the Boolean satisfiability problem (SAT) to ATPG has been shown to be a robust alternative to traditional ATPG techniques. A major challenge of research in the field of SAT-based ATPG is to obtain a robust algorithm which can solve hard SAT instances reliably without slowing down easy-to-solve SAT instances. This is particular important, since easy-to-solve SAT instances form the majority of an ATPG run. This paper proposes two structural heuristics. The first one uses testability measurements to obtain an improved initial variable order, while the second heuristic prunes many easy-to-test faults by finding easy-to-control paths. Experimental results on large industrial designs confirm that the proposed methodologies result in a significant overall speed-up.
SAT-based ATPG has proven to be a beneficial complement to traditional ATPG techniques. The generation of a CNF-representation is a vital issue in SAT-based test pattern generation. Firstly, the generation of the problem instances for SAT-based ATPG requires a significant portion of the overall runtime. Secondly, the performance of the SAT solver strongly depends on the properties of the resulting CNF-representation.
Microprocessors and Microsystems, 2013
Testing of digital circuits seems to be a completely mastered part of the design flow, but constrained test patterns generation is still a highly evolving branch of digital circuit testing. Our previous research on constrained test pattern generation proved that we can benefit from an implicit representation of test patterns set in CNF (Conjunctive Normal Form). Some techniques of speeding up the constrained SATbased test patterns generation are described and closely analyzed in this paper. These techniques are experimentally evaluated on a real SAT-based algorithm performing a constrained test patterns compression based on overlapping of test patterns. Experiments are performed on a subset of ISCAS'85 and '89 benchmark circuits. Results of the experiments are discussed and recommendations for a further development of similar SAT-based tools for constrained test patterns generation are given.
Sixth IEEE International High-Level Design Validation and Test Workshop, 2000
We analyze the performance of satisfiability (SAT) and Automatic Test Pattern Generation (ATPG) algorithms in two state-of-the-art solvers. The goal is to best understand how features of each solver are suited for hardware verification. For ATPG, we analyze depthfirst and breadth-first decision orderings and effects of two weighting heuristics in the decision ordering, and also study the effect of randomization of decisions. Features of ATPG and SAT that affect their robustness and flexibility on real circuits are studied, and the two solvers are compared on 24 industrial circuits. We further analyze the results to identify the strengths and shortcomings of each solver. This will enable incorporation of features from each solver in order to optimize performance, since they both operate on the same principles.
2009 Asian Test Symposium, 2009
ABSTRACT SAT-based automatic test pattern generation has several ad- vantages compared to conventional structural procedures, yet often yields too large test sets. We present a dynamic compaction procedure for SAT-based ATPG which utilizes internal data structures of the SAT solver to extract essen- tial fault detection conditions and to generate patterns which cover multiple faults. We complement this technique by a state-of-the-art forward-looking reverse-order simulation procedure. Experimental results obtained for an industrial benchmark circuit suite show that the new method outper- forms earlier static approaches by approximately 23%.
Lecture Notes in Computer Science, 2005
2010
Abstract Model checking techniques are promising for automated generation of directed tests. However, due to the prohibitively large time and resource requirements, conventional model checking techniques do not scale well when checking complex designs. In SAT-based BMC, many variable ordering heuristics have been investigated to improve counterexample (test) generation involving only one property.
Artificial Intelligence Review, 2018
Boolean satisfiability (SAT) has been studied for the last twenty years. Advances have been made allowing SAT solvers to be used in many applications including formal verification of digital designs. However, performance and capacity of SAT solvers are still limited. From the practical side, many of the existing applications based on SAT solvers use them as blackboxes in which the problem is translated into a monolithic conjunctive normal form instance and then throw it to the SAT solver with no interaction between the application and the SAT solver. This paper presents a comprehensive study and analysis of the latest developments in SAT-solver and new approaches that used in branching heuristics, Boolean constraint propagation and conflict analysis techniques during the last two decade. In addition, the paper provides the most effective techniques in using SAT solvers as verification techniques, mainly model checkers, to enhance the SAT solver performance, efficiency and productivity. Moreover, the paper presents the remarkable accomplishments and the main challenges facing SAT-solver techniques and contrasts between different techniques according to their efficiency, algorithms, usage and feasibility.
IEEE Trans. on CAD, 1989
The Western Research Laboratory (WRL) is a computer systems research group that was founded by Digital Equipment Corporation in 1982. Our focus is computer science research relevant to the design and application of high performance scientific computers. We test our ideas by designing, building, and using real systems. The systems we build are research prototypes; they are not intended to become products.
2010
Abstract Directed test generation is important for the functional verification of complex system-on-chip designs. SAT based bounded model checking is promising for counter example generation which can be used in directed testing. Existing research has explored two directions to accelerate the SAT solving process: learning during solving of one property with different bounds, or solving multiple properties with known bounds.
16th Euromicro Conference on Digital System Design (Dsd 2013), 2013
This paper presents a novel ATPG algorithm directly producing compressed test patterns. It benefits both from the features of satisfiability-based techniques and symbolic simulation. The ATPG is targeted to architectures comprised of interconnected embedded cores, particularly to the RESPIN architecture. We show experimentally that the proposed ATPG significantly outperforms the state-of-the-art approaches in terms of the test compression ratio.
2007
Due to ever increasing design sizes, more ecient tools for Automatic Test Pattern Generation (ATPG) are needed. Recently, SAT-based approaches for test pattern generation have been shown to be very ecient even on large industrial circuits. But these SAT-based techniques are not always superior to classical ATPG approaches. An integration of SAT-based engines into the classical ATPG flow can improve
2009 22nd International Conference on VLSI Design, 2009
We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully chosen mix of various optimization techniques, multimillion-gate industrial circuits are handled without aborts. TIGUAN supports both conventional single-stuck-at faults and sophisticated conditional multiple stuck-at faults which allows to generate patterns for non-standard fault models.
International Journal of Parallel Programming, 2010
We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully chosen mix of various optimization techniques, multimillion-gate industrial circuits are handled without aborts. TIGUAN supports both conventional single-stuck-at faults and sophisticated conditional multiple stuck-at faults which allows to generate patterns for non-standard fault models.
2011
Abstract Recent advances in propositional satisfiability (SAT) and Satisfiability Modulo Theories (SMT) solvers are increasingly rendering SAT and SMT-based automatic test generation an attractive alternative to traditional algorithmic test generation methods. The use of SAT/SMT solvers is particularly appealing when testing Boolean expressions: These tools are able to deal with constraints over the models, generate compact test suites, and they support fault-based test generation methods.
Research in Computing Science
We propose a novel method to review the satisifiability of (K ∧ φ), where K is a two conjunctive form and φ is a three conjunctive form, both formulas defined on the same set of variables. We extend our method to solve the incremental satisfiablity problem (ISAT), and we present different cases where ISAT can be solved in polynomial time. Our proposal is adequate to solve the 2-ISAT problem, and our method allows to recognize tractable instances of 2-ISAT. We illustrate a practical application of our algorithm in the area of recognizing faults on combinatorial circuits.
Journal of Advances in Information Technology, 2010
The growing size and complexity of VLSI circuits have made quality and reliability requirements increasingly stringent. The work presented in this paper investigates the application of Boolean Satisfiability (SAT)-based techniques to address two distinct VLSI testing activities, namely, test vector generation to excite stuck-open faults in CMOS circuits, and test vector generation for dynamic burn-in testing. The presence of a stuck-open fault renders an otherwise combinational logic gate sequential, therefore causing a malfunction of the integrated circuit. On the other hand, burn-in screening has been an integral part of semiconductors manufacturing to assure that reliability goals are achieved. The purpose of this type of testing is to apply to the device under test a set of input patterns which maximizes the circuits nodal activity, and by so doing causing an increase in its power dissipation that leads to device failures like electromigration and hot-carrier degradation at an early stage of the device operation.
To cope with the problems of technology scaling, a robust design has become desirable. Self-checking circuits combined with rollback or repair strategies can provide a low cost solution for many applications. However, standard synthesis procedures may violate design constraints or lead to sub-optimal designs. The SAT-based strategies for the verification and synthesis of self-checking circuits presented in this paper can provide efficient solutions.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
This article describes the Boolean satisfiability method for generating test patterns for single stuck-at faults in combinational circuits. This new method generates test patterns in two steps: First, it constructs a formula expressing the Boolean diference between the unfaulted and faulted circuits. Second, it applies a Boolean satisjiability algorithm to the resulting formula. This approach differs from previous methods now in use, which search the circuit structure directly instead of constructing a formula from it. The new method is general and effective: it allows for the addition of heuristics used by structural search methods, and it has produced excellent results on popular test pattern generation benchmarks.
The Computer Journal, 2015
In the context of automatic test generation, the use of propositional satisability (SAT) and Satisability Modulo Theories (SMT) solvers is becoming an attractive alternative to traditional algorithmic test generation methods, especially when testing Boolean expressions. The main advantages are the capability to deal with constraints over the inputs, the generation of compact test suites, and the support for fault detecting test generation methods. However, these solvers normally require more time and a greater amount of memory than classical test generation algorithms, making their applicability not always feasible in practice. In this paper we propose several ways to optimize the SAT/SMT-based process of test generation for Boolean expressions and we compare several solving tools and propositional transformation rules. These optimizations promise to make SAT/SMT-based techniques as ecient as standard methods for testing purposes, especially when dealing with Boolean expressions, as proved by our experiments.
Loading Preview
Sorry, preview is currently unavailable. You can download the paper by clicking the button above.