An Improved Performance Ring Oscillator Design

International Journal of Electrical and Computer Engineering (IJECE), 2019

A common voltage-controlled oscillator (VCO) architecture used in the phase locked loop (PLL) is the ring oscillator (RO). RO consist of number of inverters cascaded together as the input of the first stage connected to the output of the last stage. It is important to design the RO to be work at desired frequency depend on application with low power consumption. This paper presents a review the performance evaluation of different delay cell topologies the implemented in the ring oscillator. The various topologies analyzed includes current starved delay cell, differential delay cell and current follower cell. Performance evaluation includes frequency range, frequency stability, phase noise and power consumption had been reviewed and comparison of different topologies has been discussed. It is observed that starved current delay cell have lower power consumption and the different of the frequency range is small as compared to other type of delay cell. 1. INTRODUCTION Basically, oscillator is a frequency translation that translate information signal with time reference. There is variation of oscillator with different principle operation, frequency oscillation and its noise performance. For instant, voltage-controlled oscillator (VCO) is one type of oscillator that output oscillation frequency can be varied by varying the amplitude of its input signal. There are two architectures of VCO namely; the ring oscillator and the LC oscillator. Ring oscillator is widely used in the communication system design especially in the wireless ssystem [1]-[5] and FPGA application [6], [7] because of its wide tuning range, making them more robust over process and temperature variations. It also use used to study the degradation of logic CMOS circuit [8], [9]. Many trade-offs in terms of speed, power, area and application domain need to be considered in designing a ring oscillator. Thus, it is important to determine accurate frequency oscillation of the ring oscillator so that the designer able to make informed decisions regarding these trade-offs. This paper is organized as follows. Section 2 discuss the basic concept of ring oscillator and the equations related to oscillation frequency that have been derived in previous works. In Section 3 investigates the available delay topologies used ring oscillator. Section 4 compares the performance and discuss the advantage and disadvantages of each topology. Section 5 presents our conclusions.

2017

This Paper reports on design and analysis of CMOS Voltage Controlled Ring Oscillator (VCRO) based on the delay cells proposed by Changzhi Li and Jenshan Lin. The two stage CMOS VCRO exhibits very low power consumption and wide tuning range when realized using GPDK 45 nm CMOS process. The oscillator has a very wide tuning range from 6 GHz to 17 GHz. Because of its wide tuning range, it can be used for electronic warfare applications. It has also very low power consumption of about 3µW with a supply voltage of 1 V. The phase noise of this ring oscillator is found to be-78 dBC/Hz @10 MHz offset which can be improved by adding more number of stages.

Voltage Controlled Oscillator is one of the most important basic building block for analog, digital as well as in mixed signal circuits. This paper presents a new technique to improve the performance of ring oscillator. The VCO is based on single ended ring oscillator. The circuit is designed using 0.13 μm CMOS technology with supply voltage of 3.3 V. A VCO with high frequency range from 2.26GHz to 3.50 GHz is achieved by using this technique. Simulation results reveal the better performance of the proposed design as compared to existing current staved ring VCO in terms of oscillation frequency and power consumption.

Indian Journal of Pure and Applied …, 2010

The structure and operating principle of ring oscillators (RO) have been described. The expression for the frequency of oscillation of a complementary metal oxide semiconductor (CMOS) delay cell based conventional ring oscillator is presented and propagation delay of the delay stages is calculated. The limitations of a conventional RO have been studied and a few techniques to overcome these limitations have been mentioned. In this context, some modified structures of ring oscillators such as negative skewed delay RO, multi feedback RO, coupled RO are described for high frequency oscillation. The effect of noise sources on the output of ring oscillators has also been studied. Some potential applications of such ring oscillator based on its voltage tuning characteristics and multiphase outputs are also mentioned.

Microelectronics Journal

This paper can be divided into two parts. The first part contains a comprehensive survey on the applications of voltage-controlled oscillators and the innovations in their designs. The second part presents a voltage-controlled ring oscillator (VCRO) based on using a floating-gate metal-oxide semiconductor (FGMOS) transistor in its delay element. According to this VCRO, there are no extra elements; instead, the control behavior is included in the delay element itself. The presented VCRO is analyzed quantitatively with the expressions of the oscillation frequency in terms of the control voltage and the average power consumption derived. The presented VCRO has a good linearity over the full range from 0 V to the power-supply voltage and doesn't suffer from the need to turn on the MOS transistor. The effects of the process, voltage, and temperature (PVT) variations and the technology scaling on the performance of this VCRO are also investigated. The performance of the presented VCRO is compared with that of other schemes by simulation adopting the Berkeley predictive technology model (BPTM) of the 45 nm CMOS technology with a power-supply voltage, V DD , equal to 1 V. 1.1. Oscillator applications The applications of oscillators include clock-signal generation in microprocessors or synchronous digital systems, carrier synthesis in cellular telephones [3], phase-locked loops (PLLs), and frequency translation in cellular phones. A CMOS VCO can be realized using ring oscillators, relaxation oscillators, or an LC resonant circuit [6]. LC oscillators and ring oscillators are considered the most common types of CMOS oscillators. In the following, a comparison between these two types is provided.

Journal of emerging technologies and innovative research, 2018

The more we are heading towards the future the demand for low power and small size of electronic devices is growing rapidly. CMOS (complementary metal oxide semiconductor) integrated circuits are the digital flourishing technology for the modern information era. Ring oscillator find perspective applications in biomedical devices, RFID tags and wireless sensor networks. In this paper CMOS based 7 stage ring oscillator has been designed and simulated by using LT spice for various parameters such as power consumption, frequency and delay. Index Terms Complementary metal oxide semiconductor (CMOS), Radio frequency identification (RFID), Ring Oscillator.

Applied Mechanics and Materials, 2013

This paper presents varied CMOS ring oscillator topologies using Silterra 0.13-µm Process. Three topologies of ring oscillators have been designed which is the single-ended ring oscillator, differential ring oscillator and ring oscillator based variable resistor for 2.4 GHz wireless applications. The proposed designs consist of five stages delay cell. The simulation results show that a single-ended ring oscillator obtained the lowest power consumption of 0.41 mW, while differential oscillator achieves phase noise of −64.44 dBc/Hz at 1 MHz offset frequency. However, ring oscillator based variable resistor did not achieve any significant improvement. The proposed design is oscillates at 2.4 GHz.

This project deals with the design and performance analysis of a ring oscillator using CMOS 180 nm technology process in Cadence virtuoso environment. The design of optimal Analog and Mixed Signal (AMS) very large scale integrated circuits (VLSI) is a challenging task for the integrated circuit(IC)designer. A Ring Oscillator is an active device which is made up of odd number of NOT gates and whose output oscillates between two voltage levels representing high and low. There are a number of challenges ahead while designing the CMOS Ring Oscillator which are delay, noise and glitches. CMOS is the technology of choice for many applications, CMOS oscillators with low power, phase noise and timing jitter are highly desired. In this project, we have designed a CMOS ring oscillator with nine stages. The researchers were unable to reduce the phase noise in ring oscillators substantially with nine stages. We have successfully reduced the phase noise to -6.4kdBc/Hz at 2GHz centre frequency of oscillation.

2008 IEEE International Conference on Semiconductor Electronics, 2008

This paper presents the design of two new ring oscillators based on differential and single-ended topologies using a 0.13µm 1P8M CMOS technology. The differential oscillator utilizes feed-forward technique and a new composite load with inductive impedance, reducing the delay per stage and widening the tuning range. The output frequency ranges from 0.5 to 9.5 GHz and the circuit consumes only 9mW. The simulation result of phase noise is -85.3dBc/Hz @ 1MHz offset from centre frequency. The singleended ring oscillator with inductive composite load oscillates from 6.3 to 13.9 GHz and consumes only 5.1 mW with phase noise of -81.5dBc/Hz @ 1MHz offset from centre frequency.

In this paper, a simple method allowing optimization of the CMOS ring oscillator frequency dispersion and power consumption is presented. It is shown, that for range of tens of MHz and less, the power consumption and variation of the frequency can be considerably reduced by using 3-stage, resistively coupled ring oscillator, with minimum channel width W and large channel length L MOS transistors. In addition, a simple analysis allowing to estimate the oscillator frequency from the process and transistor parameter values is provided. Keywords Ring oscillator, CMOS inverter delay, CMOS inverter chain, Frequency stability of ring oscillator.