A leaf-cell generator for silicon compilers

2000

| A genetic algorithm for the physical design of VLSI-chips is presented. The algorithm simultaneously optimizes the placement of the cells with the total routing. During the placement the detailed routing is done, while the global routes are optimized by the genetic algorithm. This is just opposed to the usual serial approach, where the computation of the detailed routing is the last step in the layout-design.

Lecture Notes in Computer Science, 1996

The generation of a high quality layout during the design of a VLSI microchip is a very complex combinatorial optimization problem. Components of a circuit have to be placed, and signal nets have to be routed on an overall minimal area. In this paper a parallel Genetic Algorithm for the combined optimization of placement and routing is presented. The main focus is on the self-adaptation of the search process: Several islands execute a sequential GA with di erent strategies. At xed intervals these strategies are ranked and each strategy is adjusted to the next better one by assimilating its characteristical parameters.

Proc. of …, 2000

With the advent of deep sub-microntechnologies,interconnectloads and delays are becoming dominant. Consequently, the currently used design ow of iterativelyperforming logic synthesis with statistical wire-load models, doing placement & routing, extracting parasitics, and using them back in the synthesis tool runs into serious timing convergence problems. Layout-driven synthesis has become the need of the day. In this paper, we present a layout-driven optimization methodology that incorporates logic-level transformations for improving the delay and area of a mapped, block-placed, and globally routed design under certain constraints such as area availability, congestion, hold-time, and pin drive, etc. We argue that this is the right stage for optimization. Only those transformations that are local, incremental, and layout-friendly are incorporated. Examples of such transformations are net bu ering, gate resizing, generalized DeMorgan transform, and pin permutation. We propose a simple ow to simultaneously improve the delay and area of the design under these constraints. We applied this ow on large, already optimized, industrial designs and obtained signi cant delay and area improvements.

International Journal of Engineering Sciences & Research Technology, 2014

Very-large-scale-integration (VLSI) is defined as a technology that allows the construction and interconnection of large numbers (millions) of transistors on a single integrated circuit. Integrated circuit is a collection of one or more gates fabricated on a single silicon chip. The major objective in designing of VLSI integrated circuits is overall chip area reduction. Genetic Algorithm is an iterative and evolutional approach that could be applied to VLSI module placement problem. In this paper a Genetic Algorithm based approach is proposed to reduce the chip area by means of effective placement of the modules. Major placement constraints are considered such that the modules are placed based on best fit position values. As an idea to improve the result of final floor plan, a condition is given such that the modules whose heights are greater than the width in their dimensions are rotated 90 degrees (i.e.) the height is converted into width and the width into height. This yield an area optimized floor plan.

Solving discrete optimization problems with genetic algorithms is in many aspects different from the solution of continuous problems. The blindness of the algorithm during the search in the space of encodings must be abandoned, because this space is discrete and the search has to reach feasible points after the application of the gentic operators. This can be achieved by the use of a problem specific genotype encoding, and hybrid, knowledge based techniques, which support the algorithm during the creation of the initial individuals and the following optimization process. In this paper a genetic algorithm for the layout generation of VLSI-chips is presented, which optimizes two, usually consecutively solved tasks simultaneously: together with the placement of the modules, the routes for the interconnection nets are optimized. INTRODUCTION One of the main feature of a genetic algorithm applied to an optimization problem is the fact, that it does not deal with the problem itself, but w...

IEE Proceedings - Circuits, Devices and Systems, 1995

In a system level or logic level design process, the decisions made during early phases of the high level design have the greatest impacts on the performance of the final chip. However, these impacts will not be realised until very late in the physical design stage. In addition, it has been observed repeatedly that the most frustrating problem in IC design is to understand the relationship between the early phase decisions and the final layout result. It is therefore important, in logic synthesis to optimise a cost function which could relate the logic equation and the final layout performance. The authors develop a logic synthesis approach which relies on an accurate design evaluation program to estimate the final design attributes such as layout area and speed. Given a candidate design implementation, an evaluation programme will be called upon to provide quick and accurate estimates of the layout area or critical path delay. This information will then be used as a feedback to the logic optimisation system. Based on this feedback, the system will 'reorient' itself toward a new direction for optimisation. Such a scheme represents a more realistic way of generating optimal layout implementations. m c IEE, 1995 Paper 19256 (ElO), first received 15th September 1994 and in revised form 27th February 1995 Y . Chen is with the Hitachi

The results of a genetic algorithm optimisation of the scheduling and allocation phases of high-level synthesis are reported. Scheduling and allocation are NP complete, multi-objective phases of high-level synthesis. A high-level synthesis system must combine the two problems to produce optimal results. The genetic algorithm described provides a robust and efficient method of search capable o] combining scheduling and allocation phases, and responding to the multiple and changing objectives of high-level synthesis. The results show the genetic algorithm succeeds in finding optimal or near optimal results to classic benchmarks in small computational time spans. 1 I n t r o d u c t i o n High-level synthesis (HLS) is the automated synthesis of a register transfer level circuit from a behavioural description, summarised in [W94]. A behavioural circuit description specifies the ultimate goals of the circuit in terms of its logical function, timing and chip area constraints. High-level synthesis systems use the behavioural description to generate a structural design implementing a specified behaviour. The structural design consists of functional units such as arithmetic logic units (ALUs), multipliers, registers and buses. High-Level Synthesis involves two NP Complete optimisations. The first is a problem of scheduling in which the operations given by the behavioural description are assigned a control step. The second, which may be performed before, after or simultaneously to scheduling, is allocation, which assigns functional units to operations given in the behavioural description. These two optimisation phases have multiple minimisation objectives; i.e. to minimise functional units, control steps needed by the circuit, registers needed to store values, and the number of buses to interconnect the circuit. It is not possible to minimise all objectives; the desired goals for the circuit must be considered by the optimisation process for the optimisation of all objectives. Previous solutions to the problem have failed to adapt well to changing objectives.

IEEE Transactions on Automatic Control, 1983

In this paper, we present a new methodology for custom VLSI layout which aims at a low turnaround time and a high quality of design. VLSI circuits are highly complex, and to speed up the design process we exploit the hierarchical structure of a design, splitting the problem domain into several levels. The process of layout at each level is divided into steps such as placement of rectangular blocks, determining block dimensions, determining interconnection paths, etc. In order to obtain high quality designs, we have systematically analyzed the relationship among the parameters being computed at various steps and have accordingly organized the flow of data and control through these steps. There are two novel features in our scheme. First, we do not follow the usual pure top-down or pure bottom-up approach, so as to take into account the infl.uence of design decisions at the higher levels on design decisions made at the lower levels, as well as vice versa. For example, we determine the geomehy of a block taking into consideration the context in which it is placed, as well as the geometries of the lower level blocks it encloses. Second, we perform a look-ahead operation when the values of some. parameters are needed before they are actually deterministically computable by the process. For example, at the ,time of placement, the area required for routing is estimated statistically (before doing the actual routing) so that a more routable placement can be obtained, thereby avoiding some unnecessary iterations.

2000

This paper presents a survey and a taxonomy of layout compaction algorithms, which are an essential part of modern symbolic layout tools employed in VLSI circuit design. Layout compaction techniques are also used in the low-end stages of silicon compilation tools and module generators. The paper addresses the main algorithms used in compaction, focusing on their implementation characteristics, performance, advantages and drawbacks. Compaction is a highly important operation to optimize the use of silicon area, achieve higher speed through wire length minimization, support technology retargeting and also allow the use of legacy layouts. Optimized cells that were developed for a fabrication process with a set of design rules have to be retargeted for a new and more compact process with a different set of design rules

2005

This paper browses through some well-known meta-heuristic search strategies, and briefly discusses some of their recent applications to the VLSI layout design process. It starts with very brief description of the different phases of VLSI layout design, and a brief overview of Meta-Heuristic search strategies. Since most of the VLSI layout design problems are hard optimization problems, the concept of NP-hardness for such problems is next explained along with the various algorithmic frameworks to solve them. Four selected well-known meta-heuristic strategies, namely, Simulated Annealing, Genetic Algorithm, Tabu Search and Ant Colony Optimization are next explained, followed a comparison of these methods. Next, selected applications of these meta-heuristics to VLSI layout design are discussed. Some of their advanced variants and different hybridization techniques, adopted for superior result, are also discussed to highlight the recent research trends in meta-heuristics.