OneChip: An FPGA processor with reconfigurable logic

To accelerate the execution of an application, repetitive logic and arithmetic computation tasks may be mapped to reconfigurable hardware, since dedicated hardware can deliver much higher speeds than those of a general-purpose processor. However, this is only feasible if the run-time reconfiguration of new tasks is fast enough, so as not to delay application execution. Currently, this is opposed by architectural constraints intrinsic to current Field-Programmable Logic Array (FPGA) architectures. Despite all new features exhibited by current FPGAs, architecturally they are still largely based on general-purpose architectures that are inadequate for the demands of reconfigurable computing. Large configuration file sizes and poor hardware and software support for partial and dynamic reconfiguration limits the acceleration that reconfigurable computing may bring to applications. The objective of this work is the identification of the architectural limitations exhibited by current FPGAs...

International Journal of Computer Applications, 2014

A new architecture type that is recently evolving is the reconfigurable architecture which combines the benefits of ASIPs (Application Specific Instruction Set Processors) and FPGAs (Field Programmable Gate Arrays). Reconfigurable computing combines software flexibility with high performance hardware. FPGAs are generally employed to construct a reconfigurable block as it provides an instant timeto-market advantage. Reconfigurable devices like FPGA offers improved computational efficiency as compared to traditional processor architectures. Reconfigurable block in these architectures provides the required flexibility for a large variety of embedded applications. Design space exploration of reconfigurable block involves a wide range of alternatives like logic block granularity in FPGA, interconnect topology, etc. The goal of this paper is to explore the reconfigurable architectures.

R. Phani Vidyadhar & J. Selva Kumar, 2013

Coarse-Grained Reconfigurable Architecture (CGRAs) requires many Processing Elements (PEs) and a configuration cache memory unit for reconfiguration of its PE array. This structure is meant for high performance and flexibility, it consumes significant power. The applications of Field Programmable Gate Arrays (FPGAs) are multi fold in real-time systems. They have several advantages over Application Specific Integrated Circuits (ASICs), but CGRAs applications have been restricted to integer arithmetic, since existing CGRAs supports only integer arithmetic or logical applications. In this work proposed here main objective is to design existing 4 x 4 Processing Elements (PEs) array for integer arithmetic. The main idea of this paper is to explore the advantages of FPGA in real world by mapping applications that supports integer arithmetic and the mapping can be done by using the Fast Heuristic algorithm to get the required results. The focus is to do synthesis of both existing 4 x 4 PE array design and modified 4 x 4 PE array design for speed, power and delay using Xilinx and Xpower analysis tool. This design uses HDL, Modelsim simulator and Xilinx9.1i Synthesizer targeted on Vertex platform. Heuristic approach using Quantum- inspired Evolutionary Algorithm (QEA) used here supports for integer arithmetic applications. The proposed Modified Processing Elements proves to be 20 - 25% reduction in delay and power dissipation, when compared to the existing PEs of 4 x 4 elements. The proposed PEs might lead a significant reduction in power and delay when used in multimedia application, with maximum throughput.

Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871), 2000

In this paper the idea of the general-purpose processor implemented in dynamically reconfigurable FPGA is presented. The novelty of the proposed solution lays in the lack of typical sequential processing -all operations are realized in parallel in the hardware. At the same time the new architecture does not impose any modification of the software development process.

Abstract There are agrowing,number,of reconfigurable architectures that combine the advantages of a hardwired implementation (performance, power consumption) with the advantages of a software solution (flexibility, time to market). Today, there are devices on the market that can be dynamically reconfigured at run-time within one clock cycle. But the benefits of these architectures can only be utilized if applications can be mapped efficiently. In

Mixed Design of Integrated Circuits and Systems International Conference, 2007

This paper presents reconfigurable FPGA-based hardware accelerator for embedded DSP. At first the principle of shared-memory based processor are shown and then specific universal balanced architecture is proposed. An example of processor for TVDFT on the given accelerator is also given. Implementation of multiplier and adder based on the serial arithmetic are included as processor elements.

Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays - FPGA '00, 2000

With increased logic density due to the shift towards Deep Submicron technologies (DSM), FPGAs have become a viable option for implementing large designs. However, most commercial FPGAs, due to their general purpose architectural nature, cannot handle designs which require very high throughput. In this paper, we propose a novel high throughput FPGA architecture which tries to combine the high-performance of Application Specific Integrated Circuits (ASICs) and the flexibility afforded by the reconfigurability of FPGAs. This architecture utilizes the concept of 'Wave-Steering' and works best for designs which are highly regular and have almost equal delays along all paths. It has enormous potential in Digital Signal and Image Processing applications since a good portion of these applications are regular in nature. Preliminary results for some commonly used DSP designs are encouraging and yield throughputs in the neighborhood of 770 MHz in 0.5µ CMOS technology.

Lecture Notes in Computer Science, 1999

For high-performance, embedded digital signal processing, digital signal processors (DSPs) are very important. Further, they have many features which make their integration with on-chip reconfigurable logic (RL) resources feasible and beneficial. In this paper, we discuss how this integration might be done and the potential area costs and performance benefits of incorporating RL onto a DSP chip. For our proposed architecture, a reconfigurable coprocessor can provide speed-ups ranging from 2-32x with an area cost of about a second DSP core for a set of signal processing applications and kernels. Effort sponsored by the Defense Advanced Research Projects Agency (DARPA) and Rome Laboratory, Air Force Materiel Command, USAF, under agreement number F30602-97-1-0222. The U.S. Government is authorized to reproduce and distribute reprints for Governmental purposes notwithstanding any copyright annotation thereon.

2013

— Reconfigurable systems can offer the high spatial parallelism and fine-grained, bit-level resource control traditionally associated with hardware implementations, along with the flexibility and adaptability characteristic of software. While reconfigurable systems create new opportunities for engineering and delivering high-performance programmable systems, the traditional approaches to programming and managing computations used for hardware systems (e.g. Verilog, VHDL) and software systems (e.g. C, Fortran, Java) are inappropriate and inadequate for exploiting reconfigurable platforms. To address this need, we develop a stream-oriented compute model, system architecture, and execution patterns which can capture and exploit the parallelism of spatial computations while simultaneously abstracting software applications from hardware details (e.g., timing, device capacity, microarchitectural implementation details) and consequently allowing applications to scale to exploit newer, larg...