VPR: A new packing, placement and routing tool for FPGA research

VLSI Design, 1998

This paper presents a performance-oriented placement and routing tool for fieldprogrammable gate arrays. Using recursive geometric partitioning for simultaneous placement and global routing, and a graph-based strategy for detailed routing, our tool optimizes source-sink pathlengths, channel width and total wirelength. Our results compare favorably with other FPGA layout tools, as measured by the maximum channel width required to place and route several benchmarks.

ACM Transactions on Reconfigurable Technology and Systems, 2015

Dynamic Partial Reconfiguration (DPaR) enables efficient allocation of logic resources by adding new functionalities or by sharing and/or multiplexing resources over time. Placement and routing (P&R) is one of the most time-consuming steps in the DPaR flow. P&R are two independent NP-complete problems, and, even for medium size circuits, traditional P&R algorithms are not capable of placing and routing hardware modules at runtime. We propose a novel runtime P&R algorithm for Field-Programmable Gate Array (FPGA)-based designs. Our algorithm models the FPGA as an implicit graph with a direct correspondence to the target FPGA. The P&R is performed as a graph mapping problem by exploring the node locality during a depth-first traversal. We perform the P&R using a greedy heuristic that executes in polynomial time. Unlike state-of-the-art algorithms, our approach does not try similar solutions, thus allowing the P&R to execute in milliseconds. Our algorithm is also suitable for P&R in fragmented regions. We generate results for a manufacturer-independent virtual FPGA. Compared with the most popular P&R tool running the same benchmark suite, our algorithm is up to three orders of magnitude faster.

VLSI Design, 1996

Field Programmable Gate Arrays (FPGAs) have a pre-defined chip boundary with fixed cell locations and routing resources. Placement objectives for flexible architectures (e.g., the standard cell design style) such as minimization of chip area do not reflect the primary placement goals for FPGAs. For FPGAs, the layout tools must seek 100% routability within the architectural constraints. Routability and congestion estimates must be made directly based on the demand and availability of routing resources for detailed routing of the particular FPGA. We. present a hierarchical placement approach consisting of two phases: a global placement phase followed by a detailed placement phase. The global placement phase minimizes congestion estimates of the global routing regions and satisfies all constraints at a coarser level. The detailed placer seeks to maximize the routability of the FPGA by considering factors which cause congestion at the detailed routing level and to precisely satisfy all ...

2009 11th IEEE International Conference on Computer-Aided Design and Computer Graphics, 2009

In this paper, we propose a fast placer for FPGA placement on a new commercial hierarchical FPGA device. The novelty of this research lies in the application of a multilevel V-shape optimization flow including an architecture related cluster process and a constructive placement. The new placer can handle large-scale FPGA placement problem quickly. Experimental results show that the proposed placer can further reduced the wirelength average 28.3% compared with simulated annealing based tool while achieving near 5X speedup in runtime for the five largest MCNC benchmarks. _____________________________ 978-1-4244-3701-6/09/$25.00 ©2009 IEEE

Field Programmable Logic and Application, 2004

Traditional placement algorithms for FPGAs are normally carried out on a fixed clustering solution of a circuit. The impact of clustering on wirelength and delay of the placement solutions is not well quantified. In this paper, we present an algorithm named SCPlace that performs simultaneous clustering and placement to minimize both the total wirelength and longest path delay. We also incorporate a recently proposed path counting-based net weighting scheme [16]. Our algorithm SCPlace consistently outperforms the state-of-the-art FPGA placement flow (T-VPack + VPR) with an average reduction of up to 36% in total wirelength and 31% in longest path delay.

2005

Place and Route Techniques for FPGA Architecture Advancement Akshay Sharma Chair of the Supervisory Committee: Associate Professor Scott Hauck Electrical Engineering Efficient placement and routing algorithms play an important role in FPGA architecture research. Together, the place-and-route algorithms are responsible for producing a physical implementation of an application circuit on the FPGA hardware. The quality of the place-and-route algorithms has a direct bearing on the usefulness of the target FPGA architecture. The benefits of including powerful new features on an FPGA might be lost due to the inability of the place-and-route algorithms to fully exploit these features. Thus, the advancement of FPGA architectures relies heavily on the development of efficient place-and-route algorithms. The subject of this dissertation is the development of place and route techniques that could play an important role in FPGA architecture advancement. The work presented in this dissertation is divided into two topics: Architecture-Adaptive FPGA Placement-The first topic deals with the development of a universal placement algorithm (Independence) that adapts to the target FPGA architecture. We have successfully demonstrated Independence's adaptability to three different architectures. Our results also show that Independence is able to adapt to a class of routing-poor FPGA architectures. Pipelined Routing-The second topic focuses on the development of a routing algorithm (PipeRoute) that can be used to route application circuits on high-speed, pipelined FPGA architectures. In our experiments, PipeRoute was able to successfully route netlists on a coarse-grained pipelined architecture. The algorithm incurred a 20% overhead when compared to a realistic lower bound. We also used PipeRoute in an exploratory flow to find an architecture that was up to 19% better than a hand-architected pipelined architecture. i

Field-Programmable Gate Arrays (FPGAs) are digital integrated circuits (ICs) that contain configurable logic and interconnect to provide a means for fast prototyping and also for a cost-effective chip design. The innovative development of FPGAs spurred the invention of a new field in which many different hardware algorithms could execute on a single device .

2007 IEEE Northeast Workshop on Circuits and Systems, 2007

Field Programmable Gate Arrays (FPGA) have become solutions of choice for embedded applications with small to medium production numbers. As a result, good CAD tools to support their use are in demand. This paper presents a solution to the FPGA placement problem. Some of the best solutions to date use iterative improvement heuristics such as simulated annealing. However,the run-times of these stochastic solvers becomes unacceptably long for performing placement on large FPGAs. Instead a deterministic iterative solver is proposed that is implemented in hardware. It implements a node-swap heuristic that starts from an initial random placement and iterates until it finds locally optimal solution. Initial results indicate speedups of 3-4 times over software.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019

Placement and packing are two important but separated optimization steps in a conventional FPGA implementation flow. A packing engine clusters logic elements, like lookup tables (LUTs) and flip-flops (FFs), into configurable logic blocks (CLBs), while a placement engine determines their physical locations in FPGA layouts. This paper presents a new paradigm for FPGA placement without an explicit packing stage. In the proposed framework, the solution spaces of placement and packing are simultaneously explored in a smooth and elegant way. Our experiments on ISPD 2016 and 2017 benchmark suites demonstrate the effectiveness of the proposed framework.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017

FPGA packing and placement without routability consideration could lead to unroutable results for high-utilization designs. Conventional FPGA packing and placement approaches are shown to have severe difficulties to yield good routability. In this paper, we propose an FPGA packing and placement engine called UTPlaceF that simultaneously optimizes wirelength and routability. A novel physical and congestion aware packing algorithm and a hierarchical detailed placement technique are proposed. UTPlaceF outperforms state-of-the-art FPGA placers simultaneously in runtime and solution quality on ISPD 2016 benchmark suite. Compared with the top 3 winners of ISPD'16 FPGA placement contest, UTPlaceF can deliver 6.2%, 11.6% and 29.1% better routed wirelength with shorter runtime.