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1999
Efficient methods to evaluate the quality of a test set in terms of its coverage of arbitrary defects in a circuit are presented. Our techniques rapidly estimate arbitrary defect coverage because they are independent of specific, physical, fault models. We overcome the potentially explosive computational requirements associated with considering all possible defects by implicitly evaluating multiple faults (of all types) simultaneously and by exploiting the local nature of defects. Our experiments show that a strong correlation exists between stuck-at fault coverage and defects whose behavior is independent of the input vectors. Our techniques are capable of identifying regions in the circuit where defects may escape the test set. We also demonstrate how the chances of detection of an arbitrary defect by a test set vary when a single stuck-at-fault within the vicinity of that defect is detected multiple times by the test set
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1997
It was recently observed that, in order to improve the defect coverage of a test set, test generation based on fault models such as the single-line stuck-at model may need to be augmented so as to derive test sets that detect each modeled fault more than once. In this work, we report on test pattern generators for combinational circuits that generate test sets to detect each single line stuck-at fault a given number of times. Additionally, we study the effects of test set compaction on the defect coverage of such test sets. For the purpose of experimentation, defect coverage is measured by the coverage of surrogate faults, using a framework proposed earlier. Within this framework, we show that the defect coverage does not have to be sacrificed by test compaction if the test set is computed using appropriate test generation objectives. Moreover, two test sets generated using the same test generation objectives, except that compaction heuristics were used during the generation of one but not the other, typically have similar defect coverages, even if the compacted test set is significantly smaller than the noncompacted one.
Proceedings of the conference on Design, …, 2001
The number of times a fault f in a combinational circuit is detected by a given test set T was shown earlier to affect the defect coverage of the test set. The earlier definition counted each test in T, that detects f, as a distinct detection of f. This definition counts two tests as distinct detections even if they differ only in the values of inputs that do not affect the activation or propagation of the fault. In this work, we introduce a stricter definition that requires that two counted tests would be different in the way they activate and/or propagate the fault. We describe procedures for constructing test sets based on the stricter definition, and compare them to test sets for the earlier, less strict definition. The results show a simple criterion to decide when it may be necessary to combine the two definitions in order to obtain a high quality test set.
VLSI Test Symposium, 1998. …, 1998
N-detection stuck-at test sets were shown to be effective in achieving high defect coverages for benchmark circuits. However, the definition of n-detection test sets allows the same set of faults to be detected by several different tests, thus potentially detecting the same defects. We propose an extension of the ndetection model that alleviates this problem by considering mtuples of faults and requiring that different tests would detect different m-tuples. We present experimental results to support this model.
Information Technology and Control, 2015
The design complexity of systems on a chip drives the need to reuse legacy or intellectual property cores, whose gate-level implementation details are unavailable. The core test depends on manufacturing technologies and changes permanently during a design lifecycle. In this paper we consider the impact of circuit realization on the fault coverage of the test set. We have performed various comprehensive experiments with combinational benchmark circuits. Our experiments show that the test sets generated for a particular circuit realization fail to detect in average only less than one and a half percent of the stuck-at faults of the re-synthesized circuit but in some cases this figure is more than nine percent. The double test sets declined almost twice both the maximum and the average percent of undetected faults. The experiments exhibit that the supplement of the test set with sensitive adjacent test patterns significantly increases the fault coverage of the re-synthesized core.
2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
Testing modeled faults multiple times has been shown to increase the likelihood of a test set to detect non-modeled faults, either static or dynamic, when compared to a single detect test set. Test sets that guarantee detecting every modeled fault with at least n different tests are known as n-detect test sets. Moreover, recent investigations examine how different the various tests for a fault should be, in order to further increase their ability in detecting defects. This work proposes a new test generation methodology for multiple-detect (including n-detect) test sets that increases their diversity in terms of the various fault propagation paths excited by the different tests. Specifically, the various tests per modeled fault are guaranteed to propagate the fault effect via different propagation paths. The proposed method can be applied to any linear, to the circuit size, static or dynamic fault model for multiple fault detections, such as the stuck-at or transition delay fault models, and avoids any path or path segment enumeration. Experimental results show increased numbers of propagation paths and non-modeled fault coverages when compared to traditional n-detect test sets.
2009 Asian Test Symposium, 2009
Diagnostic ATPG has traditionally been used to generate test patterns that distinguish pairs of modeled faults. In this work, we investigate the use of n-distinguishing test sets, which distinguish pairs of single stuck-at faults n times, to enhance the probability of distinguishing unmodeled defects. The basis for the use of n-distinguishing test sets to enhance defect diagnosis is similar to that for using n-detection test sets to improve the detection of unmodeled defects. We use a heuristic to target a subset of fault pairs for n-distinguishing in order to improve the efficacy of the patterns generated for aiding diagnosis. Experimental results on the larger ISCAS benchmark circuits are presented to demonstrate the improvements in defect diagnostic resolution due to the use of n-distinguishing test sets. We use randomly selected resistive bridges to represent unmodeled defects. The experimental results also show that the coverage of unmodeled defects by ndistinguishing test sets is similar to that by n-detection test sets even though the number of n-distinguishing tests is typically smaller. This suggests the possibility of using n-distinguishing test sets in place of n-detection test sets in manufacturing test.
IEEE Transactions on …, 1990
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000
methods, the hardware except the storage elements requires simple logic circuits as compared to previous method.
Computers & Electrical Engineering, 1977
A new algorithm is presented for the detection of single gate faults in combinational networks. A gate fault is any unknown transformation of the Boolean function realized by a particular gate or singie-output subnetwork. Detection of such faults is accomplished by verifying the truth table of the correct gate function.
Modern diagnosis algorithms are able to identify the defective circuit structure directly from existing fail data without being limited to any specialized fault models. Such algorithms however require test patterns with a high defect coverage, posing a major challenge particularly for embedded testing. In mixed-mode embedded test, a large amount of pseudorandom (PR) patterns are applied prior to deterministic test pattern. Partial Pseudo-Exhaustive Testing (P-PET) replaces these pseudo-random patterns during embedded testing by partial pseudo-exhaustive patterns to test a large portion of a circuit fault-model independently. The overall defect coverage is optimized compared to random testing or deterministic tests using the stuck-at fault model while maintaining a comparable hardware overhead and the same test application time. This work for the first time combines P-PET with a fault model independent diagnosis algorithm and shows that arbitrary defects can be diagnosed on average much more precisely than with standard embedded testing. The results are compared to random pattern testing and deterministic testing targeting stuck-at faults.
1997
Abstract We propose a novel procedure for testing all multiple stuck-faults in a logic circuit using two complementary algorithms. The first algorithm finds pairs of input vectors to detect the occurrence of target single stuck-faults independent of the occurrence of other faults. The second uses a sophisticated branch and bound procedure to complete the test set generation on the faults undetected by the first algorithm. The technique is complete and applies to all circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1999
In this paper, we present methods for constructing optimal tests to detect structural faults in analog integrated circuits in the presence of process variation. The analog test determination problem is formulated as selecting an optimal subset from an initial large set of tests with optimality criteria defined in terms of fault coverage and fault separation on a given fault set. The process variation may be represented either deterministically by box constraints or statistically as random variables. Each of these representations require different methods for computing the detectabilities. In the deterministic case, the detectability measures are computed by a combination of analytical and numerical optimization techniques. Such an approach helps reduce the number of simulations by up to three times over traditional Monte Carlo methods. This approach produces more compact test sets compared to a linear sensitivity analysis while being closer in accuracy to the Monte Carlo method. In the statistical case, the detectability measures are computed as separation distances between the good and faulty distributions. These distributions, represented nonparametrically are generated by traditional Monte Carlo techniques. Once the deterministic or statistical detectabilities are computed for the entire test set, a test compaction step is performed which is a covering problem. On solving this covering problem we get a test set with optimal fault coverage and fault separation.
2008
A method is presented for deterministic test pattern generation using a uniform functional fault model for combinational circuits. The fault model allows to represent the physical defects in components and defects in the communication network of components by the same technique. Physical defects are modeled as parameters in generic Boolean differential equations. Solutions of these equations give the conditions at which defects are locally activated. The defect activation conditions are used as functional fault models for logic level test generation purposes. A method is proposed which allows to find the types of faults that may occur in a real circuit and to determine their probabilities. A defect-oriented deterministic test generation tool was developed, and the experimental data obtained by the tool for ISCAS'85 benchmarks are presented. It was shown that for the majority of cases 100% stuck-at fault tests do not cover 100% of the physical defects. The main feature of the new tool is that it allows to reach 100% coverage for the given set of defects or to prove the redundancy of not detected defects. Shorts are the dominant cause of faults in modern CMOS processes. In current approach the wired-AND fault model was considered.
1998
Abstract We present a fast, dynamic fault coverage estimation technique for sequential circuits that achieves high degrees of accuracy by significantly reducing the number of injected faults and faulty-event evaluations. Specficdy, we dynamically reduce injection of two types of faults:(1) hyperactive faults that never get detected, and (2) faults whose effects never propagate to a flip-flop or primary output. The cost of fault simulation is greatly reduced as injection of most of these two types of faults is prevented.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990
A sequence of input vectors which detects all transistor stuck-open faults in a CMOS combinational circuit is a complete test sequence. Given a complete set of two-pattern tests for transistor stuckopen faults in a C M O S circuit, we show that a complete test sequence of minimum length can be obtained efficiently.
IET Computers & Digital Techniques, 2007
Test sets that detect each target fault n times (n-detection test sets) are typically generated for restricted values of n due to the increase in test set size with n. We perform both a worst-case analysis and an average-case analysis to check the effect of restricting n on the unmodeled fault coverage of an (arbitrary) n-detection test set. Our analysis is independent of any particular test set or test generation approach. It is based on a specific set of target faults and a specific set of untargeted faults. It shows that, depending on the circuit, very large values of n may be needed to guarantee the detection of all the untargeted faults. We discuss the implications of these results.
A method is presented for deterministic test pattern generation using a uniform functional fault model for combinational circuits. The fault model allows to represent the physical defects in components and defects in the communication network of components by the same technique. Physical defects are modeled as parameters in generic Boolean differential equations. Solutions of these equations give the conditions at which defects are locally activated. The defect activation conditions are used as functional fault models for logic level test generation purposes. A method is proposed which allows to find the types of faults that may occur in a real circuit and to determine their probabilities. A defect-oriented deterministic test generation tool was developed, and the experimental data obtained by the tool for ISCAS'85 benchmarks are presented. It was shown that for the majority of cases 100% stuck-at fault tests do not cover 100% of the physical defects. The main feature of the new...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013
This paper introduces a new metric to characterize test sets in terms of their diagnostic power. Our method uses much less space compared to the existing ones and is quite accurate. The metric can be utilized to increase the diagnosability of incompletely specified test sets via don't care filling. The Xfilling approach can be integrated with test pattern generation tools to aid in better diagnostic pattern set generation. Index Terms-Fault clustering, fault diagnosis, fault dictionary, indistinguishable fault pairs, X filling. I. Introduction F AULT DIAGNOSIS plays a major role in fast yield ramp up. With the increasing complexity of integrated circuit (IC) logic design and increasing difficulty of physical inspection in today's multilayer deep sub-micron devices, the observation has become exceedingly expensive and time consuming. The primary responsibility of any diagnosis algorithm is to accurately narrow down the list of suspected candidates. Almost all the diagnosis algorithms proposed in the literature [1]-[3] use the failure information produced by the tester. Some diagnosis algorithms [4], [5] also use the pass patterns to narrow down the list further. Overall, the backbone of any diagnosis algorithm is the test set in use. Consider two faults f 1 and f 2 having similar responses for all patterns in the test set in use. If any of these two faults occur, all diagnosis algorithms (which use this test set) will report both the faults with same rank. This leads us to the problem of assessing test sets in terms of their diagnosing capability. The exact brute force method requires building fault dictionary, which consists of all the faulty responses for each test vector. However, for a test set, memory required for storing the fault dictionary is O(F * T * O), where F is the number of faults, T is the number of patterns in the test set, and O is the number of outputs of the circuit. In [6], authors have proposed a single structure to store all information related to all F faults in the circuit with respect to a pattern k. They have used a F * F distinguishability matrix D k. The generic element d k (i, j) of the matrix is one if and only if the pattern k can distinguish between faults f i and f j , 0
ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575), 2002
A new era began in microelectronics with the advent of integrated circuit (IC) technology. With dramatic improvement of integration technology, the complexities of IC testing has increased and become mucb more acute. Fault simulation technique for maximization of fault detection in IC testing is presented in this paper.
1993
This paper presents new cost-effective heuristics for the generation of minimal test sets. Both dynamic techniques, which are introduced into the test generation process, and a static technique, which is applied to already generated test sets, are used. The dynamic compaction techniques maximize the number of faults that a new test vector detects out of the yet-undetected faults as well as out of the already-detected ones. Thus, they reduce the number of tests and allow tests generated earlier in the test generation process to be dropped. The static compaction technique replaces N test vectors by M < N test vectors, without loss of fault coverage. During test generation, we also find a lower bound on test set size. Experimental results demonstrate the effectiveness of the proposed techniques.
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