Compact XOR-bi-decomposition for lattices of Boolean functions

2017

Bi-Decomposition is a very powerful approach for the synthesis of multi-level combinational circuits because it utilizes the properties of the given functions to find small circuits, with low power consumption and low delay. Compact bi-decompositions restrict the variables in the support of the decomposition functions as much as possible. Methods to find compact AND-, OR-, or XOR-bi-decompositions for a given completely specified function are well known. Lattices of Boolean Functions significantly increase the possibilities to synthesize a minimal circuit. However, so far only methods to find compact ANDor OR-bi-decompositions for lattices of Boolean functions are known. This gap, i.e., a method to find a compact XOR-bi-decomposition for a lattice of Boolean functions, has been closed by the approach suggested in this paper. A lattice of Boolean functions represents all possible functions which are defined by an incompletely specified function. In the context of vectorial bi-decompo...

In this paper, we consider the problem of logic simplification for a special class of logic functions, namely complementary Boolean functions (CBF), targeting low power implementation using static CMOS logic style. The functions are uniquely characterized by the presence of terms, where for a canonical binary 2-tuple, D(m j ) ∪ D(m k ) = { } and therefore, we have | D(m j ) ∪ D(m k ) | = 0 [19]. Similarly, D(M j ) ∪ D(M k ) = { } and hence | D(M j ) ∪ D(M k ) | = 0. Here, 'm k ' and 'M k ' represent a minterm and maxterm respectively. We compare the circuits minimized with our proposed method with those corresponding to factored Reed-Muller (f-RM) form, factored Pseudo Kronecker Reed-Muller (f-PKRM) form, and factored Generalized Reed-Muller (f-GRM) form.

IEEE Transactions on Computers, 1969

A decomposition and reconstruction approach for syn- thesizing an arbitrary Boolean function with a minimum number of threshold logic elements connected by feedforward paths only is presented. Attention is mainly focused on cascade-type realizations. The approach has the advantage that near-minimal solutions are readily derived. An estimate of how closely the minimality has been approached is obtainable in this method. The method has been suc- cessfully applied by the authors to Boolean functions of 5 and 6 vari- ables.

Microprocessors and Microsystems, 2018

In this paper we propose a novel approach to the synthesis of minimal-sized lattices, based on the decomposition of logic functions. Since the decomposition allows to obtain circuits with a smaller area, our idea is to decompose the Boolean functions according to generalizations of the classical Shannon decomposition, then generate the lattices for each component function, and finally implement the original function by a single composed lattice obtained by glueing together appropriately the lattices of the component functions. In particular we study the two decomposition schemes defining the bounded-level logic networks called Pcircuits and EXOR-Projected Sums of Products (EP-SOPs). Experimental results show that about 34% of our benchmarks achieve a smaller area when implemented using the P-circuit decomposition for switching lattices, with an average gain of at least 25%, and about 27% of our benchmarks achieve a smaller area when implemented using the EP-SOP decomposition, with an average gain of at least 22%.

Arxiv preprint arXiv:0710.0664, 2007

Reversible logic [4, 11] is one of the hot areas of research. It has many applications in quantum computation [13, 23], low-power CMOS [8, 31] and many more. Synthesis and optimization of reversible circuits cannot be done using conventional ways [29]. The design and analysis ...

Objective of this paper is to present historiography of logic switching circuits. The research mainly focuses on chronological development and application of logic in the field of electronic and computer applications. This paper briefly discussed on the basic needs of logic synthesis and also discuss few interesting facts and design consideration regarding logic synthesis. It also enhances student’s deep understanding of different logic function minimization technique during a lecture and practical implementation.

VLSI Design, 1995

An effective logic synthesis procedure based on parallel and serial decomposition of a Boolean function is presented in this paper. The decomposition, carried out as the very first step of the .synthesis process, is based on an original representation of the function by a set of r-partitions over the set of minterms. Two different decomposition strategies, namely serial and parallel, are exploited by striking a balance between the two ideas. The presented procedure can be applied to completely or incompletely specified, singleor multiple-output functions and is suitable for different types of FPGAs including XILINX, ACTEL and ALGOTRONIX devices. The results of the benchmark experiments presented in the paper show that, in several cases, our method produces circuits of significantly reduced complexity compared to the solutions reported in the literature.

We study Boolean circuits as a representation of Boolean functions and consider different equivalence, audit, and enumeration problems. For a number of restricted sets of gate types (bases) we obtain efficient algorithms, while for all other gate types we show these problems are at least NP-hard.

2006

We introduce a new method for obtaining optimal architectures that implement arbitrary Boolean functions using threshold functions. The standard threshold circuits using threshold gates and weights are replaced by nodes computing directly a threshold function of the inputs. The method developed can be considered exhaustive as if a solution exist the algorithm eventually will find it. At all stages different optimization strategies are introduced in order to make the algorithm as efficient as possible. The method is applied to the synthesis of circuits that implement a flip-flop circuit and a multi-configurable gate. The advantages and disadvantages of the method are analyzed.