A Genetic Approach for Area Reduction in VLSI Layout.

Artificial Intelligence Research, 2012

Floor planning is an important problem in very large scale integrated-circuit (VLSI) design automation domain as it evaluates the performance, size, yield and reliability of ICs. Due to rapid increase in number of components on a chip, floor planning has gained its importance further in determining the quality of the design achieved. In this paper we have devised an approach for placement of modules in a given area with bounding constraints in terms of minimum placement area imposed. We have used Modified Genetic Algorithm (MGA) technique for determining and obtaining an optimal placement using an iterative approach.

International Journal of Circuit Theory and Applications, 2005

This paper presents an integrated approach of simulated annealing (SA) and genetic algorithm (GA) for the analogue module placement in mixed-signal integrated circuit layout designs. The proposed algorithm follows the optimization ow of a normal GA controlled by the methodology of SA. The bitmatrix chromosomal representation is employed to describe the location and the orientation of modules. Compared with the conventional bit-string representation, the proposed chromosomal representation tends to signiÿcantly improve the search e ciency. In addition, a slide-based at scheme is developed to transform an absolute co-ordinate placement of modules to a relative placement. In this way, the symmetry constraints imposed on analogue very large scale integration circuits can be easily fulÿlled in the placement run. Use of a radiation-decoder can also drastically shrink the conÿguration space without degrading search opportunities. The proposed algorithm has been tested with several example circuits. The experiments show this promising algorithm makes the better performance than the simpler SA or GA approaches working alone, and the quality of the automatically generated layouts is comparable to those done manually. 488 L. ZHANG ET AL.

IEEE Transactions on Automatic Control, 1983

In this paper, we present a new methodology for custom VLSI layout which aims at a low turnaround time and a high quality of design. VLSI circuits are highly complex, and to speed up the design process we exploit the hierarchical structure of a design, splitting the problem domain into several levels. The process of layout at each level is divided into steps such as placement of rectangular blocks, determining block dimensions, determining interconnection paths, etc. In order to obtain high quality designs, we have systematically analyzed the relationship among the parameters being computed at various steps and have accordingly organized the flow of data and control through these steps. There are two novel features in our scheme. First, we do not follow the usual pure top-down or pure bottom-up approach, so as to take into account the infl.uence of design decisions at the higher levels on design decisions made at the lower levels, as well as vice versa. For example, we determine the geomehy of a block taking into consideration the context in which it is placed, as well as the geometries of the lower level blocks it encloses. Second, we perform a look-ahead operation when the values of some. parameters are needed before they are actually deterministically computable by the process. For example, at the ,time of placement, the area required for routing is estimated statistically (before doing the actual routing) so that a more routable placement can be obtained, thereby avoiding some unnecessary iterations.

Vlsi Design, 1994

In this paper, we present a Simulated _Evolution _Gate-Matrix_ layout Algorithm (SEGMA) for synthesizing CMOS random logic modules. The gate-matrix layout problem is solved as a one-dimensional transistor gates placement problem. Given a placement of all the transistor gates, simulated evolution offers a systematic method to improve the quality of the layout that is measured by the number of tracks needed for the given netlist. This is accomplished by identifying a subset of gates whose relative placements are deemed "poor quality" according to a heuristic criterion. By rearranging the placement of these identified subsets of gates, it is hoped that a gate placement with better quality, meaning fewer tracks, may emerge. Since this method enables the current "generation" of gate placement to evolve into a more advanced one in a way similar to the biological evolution process, this method is called simulated evolution. To apply simulated evolution to solve the gate-matrix layout problem, we propose a novel heuristic criterion, called randomized quality factor, which facilitates the judicious selection of the subset of poor quality gates. Several carefully devised and tested strategies are also implemented. Extensive simulation results indicate that SEGMA is producing very compact gate-matrix layouts.

IFIP International Federation for Information Proc

New technologies present a widely range of challenges in the design of standard-cell libraries, layout generation and validation of macro-blocks. Thus, the development of new tools being able to deal with these challenges is mandatory. This work presents a transistor placement technique using genetic algorithm associated to analytical programming. The genetic algorithm is used to reduce the search space of possible solutions while analytical equations are used to find out the position of each transistor in the layout.

Proceedings of the 2005 conference on Genetic and evolutionary computation - GECCO '05, 2005

Simulated Evolution (SimE) is a sound stochastic approximation algorithm based on the principles of adaptation. If properly engineered it is possible for SimE to reach nearoptimal solutions in lesser time then Simulated Annealing [1], [2]. Nevertheless, depending on the size of the problem, it may have large run-time requirements. One practical approach to speed up the execution of SimE algorithm is to parallelize it. This is all the more true for multi-objective cell placement, where the need to optimize conflicting objectives (interconnect wirelength, power dissipation, and timing performance) adds another level of difficulty [3]. In this paper a distributed parallel SimE algorithm is presented for multiobjective VLSI standard cell placement. Fuzzy logic is used to integrate the costs of these objectives. The algorithm presented is based on random distribution of rows to individual processors in order to partition the solution and distribute computationally intensive tasks while efficiently traversing the complex search space. A series of experiments are performed on ISCAS-85/89 benchmarks to compare speedup with serial implementation and other earlier proposals. Discussion on comparison with parallel implementations of other iterative heuristics is included.

Computer Sciences Forum (Honeywell), 1984

This article describes a chip planning tool called SPIDER (Spatial Planning and Interactive Environment for Research) for planning the layout of custom VLSI circuits. Some of the algorithms used are technology independent while others are specific to ISL (integrated Schottky Logic) technology. Thus, in the case of ISL, a close match between the layout tool, the design style and the technology is possible. The ISL dependent portions of SPIDER are insulated from the technology independent portions. The planning tool provides estimates of the chip area, the interconnection wiring space between the function blocks and a floor plan indicating the relative placement of the function blocks. An overview of SPIDER which outlines the overall philosophy and the various tasks in chip planning, is given. Some experiments in chip planning with SPIDER are then described. Finally extensions to the scope of the planning tool are discussed. (With Raja S. Ramnarayan, PhD)

1995

A VLSI chip can today contain millions of transistors and is expected to contain more than 100 million transistors in the next decade. This tremendous growth is made possible by the development of sophisticated design tools and software. To deal with the complexity of millions of components and to achieve a turn around time in terms of a couple of months, VLSI design tools must not only be computationally fast but also generate layouts close to optimal. The work in this thesis involves exploring algorithmic solutions to the problem of circuit layout in VLSI design. The exploration is an attempt to evaluate, design, improve and integrate the best combinatorial algorithms to solve the circuit layout problem. Advanced search heuristic techniques in the form of Tabu Search, GRASP and Genetic Algorithms are used extensively to solve most of the problems in circuit layout. We show in this thesis that new hybrid partitioning techniques based on the above mentioned heuristics outperform traditional heuristic methods. In fact, these novel approaches consistently find better solutions than other methods in a fraction of the time. A new placement algorithm that is suitable for standard cell layout is also presented. The initial placement is obtained using the partitioning algorithm. An efficient clustering based algorithm is developed to further reduce the complexity of circuit partitioning and placement and improve the performance of the design process in terms of quality and computation time. Finally, parallel implementations of the developed heuristics on a network of workstations are presented and significant speedups are reported. The ability of the hybrid heuristics to find near optimal solutions is assessed by comparing their performance with a general purpose mixed integer programming package. Experimental results indicate that our heuristics based on clustering and hybridization schemes give very good results and are suitable for VLSI circuits. v xv C.4 GRASP 2-Way partitioning .

IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1996

The earliest and the most critical stage in VLSI layout design is the placement. The background of which is the rectangle packing problem: Given set of rectangular modules of arbitrary sizes, place them without overlap on a plane within a rectangle of minimum area. Since the variety of the packing is uncountably infinite, the key issue for successful optimization is the introduction of a finite solution space which includes an optimal solution. This paper proposes such a solution space where each packing is represented by a pair of module name sequences, called a sequence-pair. Searching this space by simulated annealing, hundreds of modules have been packed efficiently as demonstrated. For applications to VLSI layout, we attack the biggest MCNC benchmark ami49 with a conventional wiring area estimation method, and obtain a highly promising placement.

International Journal of Systems Science, 2004

This paper deals with a Very-Large-Scale Integrated systems design problem that belongs to the NP(Nondeterministic Polynomial)-hard class. The Gate Matrix Layout problem has numerous applications in the chip-manufacturing industry and in other industrial settings. A memetic algorithm is employed to solve a set of benchmark instances, and numerical comparisons with a highly competitive method-a microcanonical optimization approach-are performed. Beyond the effectiveness of the method, shown by the results obtained for these instances, an additional goal of this work is to study how the performance of the algorithm is affected by the use of multiple populations and of different individual-migration policies between such populations. The results signal a strong performance improvement of multiple populations over single population approaches. Finally, the proposed algorithm presents several refinements, like structured populations and a specially tailored local search.

ijpam, 2017

Floorplanning plays an important role within the physical design method of very large Scale Integrated (VLSI) chips. It’s a necessary design step to estimate the chip area before the optimized placement of digital blocks and their interconnections. Since VLSI floorplanning is an NP-hard problem, several improvement techniques were adopted to find optimal solution. In this paper, a hybrid algorithm which is genetic algorithm combined with Ant colony optimization (ACO) algorithm is employed for the fixed die outline constrained floorplanning, with the ultimate aim of reducing the full chip area. Initially, B*-tree is employed to come up with the first floorplan for the given rectangular hard modules and so Ant Colony Optimization (ACO) is applied in any stages in genetic algorithm to get an optimum solution for the economical floorplan. The experimental results of the HGA algorithm are obtained for the MCNC benchmark circuits.

2005

This paper browses through some well-known meta-heuristic search strategies, and briefly discusses some of their recent applications to the VLSI layout design process. It starts with very brief description of the different phases of VLSI layout design, and a brief overview of Meta-Heuristic search strategies. Since most of the VLSI layout design problems are hard optimization problems, the concept of NP-hardness for such problems is next explained along with the various algorithmic frameworks to solve them. Four selected well-known meta-heuristic strategies, namely, Simulated Annealing, Genetic Algorithm, Tabu Search and Ant Colony Optimization are next explained, followed a comparison of these methods. Next, selected applications of these meta-heuristics to VLSI layout design are discussed. Some of their advanced variants and different hybridization techniques, adopted for superior result, are also discussed to highlight the recent research trends in meta-heuristics.

Seventh International Conference on Intelligent Systems Design and Applications (ISDA 2007), 2007

Floorplanning is an important problem in Very Large-Scale Integrated-circuit (VLSI) design automation as it determines the performance, size, yield and reliability of VLSI chips. From the computational point of view, floorplan area minimization is an NP-hard problem. This paper presents a parallel genetic algorithm (GA) for floorplan area optimization. The parallel GA is based an island model with an asynchronous migration mechanism, and is implemented using Web services and multithreading technologies. The parallel GA is compared with a sequential GA that the parallel GA is based on. Experimental results show that the parallel GA can produce better results than the sequential GA when they use the same amount of computing resources. In addition, since the number of islands and migration interval are two important parameters that directly affect the performance of island-based parallel GAs, the impact of the two parameters on the performance of the parallel GA are empirically studied in this paper.

2002

This paper addresses a Very Large Scale Integrated (VLSI) design problem that belongs to the NP-hard class. The Gate Matrix Layout problem has strong applications on the chip-manufacturing industry. A Memetic Algorithm is employed to solve a set of benchmark instances, present in previous works in the literature. Beyond the results found for these instances, another goal of this paper is to study how the use of multiple populations and different migration strategies affects the algorithm's performance. This comparison has shown to be fruitful, sometimes producing a strong performance improvement over single population approaches.

Floor-planning is one of the key design flow of VLSI chip designing process.Area miniaturization is the essence of compaction of any application circuit in chip designing. The physical design stages involve virtual design realizations iterated for their efficiency.For this purpose, the CAD algorithms offer avariety of solutions depending on the needs and specifications of the designer. The use of EDA tools help invisualization of the effects of design algorithms on the circuit performance and the dimensions of the floor areaoccupied by the design. It also uses a genetic algorithm (GA) .GA has been implemented and tested on popular benchmark problems. Experimental results show that GA can quickly produce optimal solutions for all tested benchmark problems.The hybrid algorithm on the circuit design is, effect of applying the move based partitioning algorithms KL,FM to circuits and optimizing the cells of the circuit using Hybrid Genetic Algorithm (HGA) is discussed. The results suggest that, this approach on circuits provides scope to unify the stages of physical design stages of partitioning and placement and also optimize the area parameter of a physical design process.