Serial LDPC decoding on a SIMD DSP using horizontal-scheduling
Marco Gomes2015
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Abstract
In this paper we propose an efcient vectorized low den-sity parity check (LDPC) decoding scheme based on the min-sum algorithm and the horizontal scheduling method. Also, the well known forward-backward algorithm, used in the check-node messages update, is improved. Results are presented for 32 and 16 bits logarithm like-lihood ratio messages representation on a high performance and modern xed point DSP. The single instruction multiple data (SIMD) feature was explored in the 16 bits case. Both regular and irregular codes are considered. 1.
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