A design by example regular structure generator

Computer Sciences Forum (Honeywell), 1984

This article describes a chip planning tool called SPIDER (Spatial Planning and Interactive Environment for Research) for planning the layout of custom VLSI circuits. Some of the algorithms used are technology independent while others are specific to ISL (integrated Schottky Logic) technology. Thus, in the case of ISL, a close match between the layout tool, the design style and the technology is possible. The ISL dependent portions of SPIDER are insulated from the technology independent portions. The planning tool provides estimates of the chip area, the interconnection wiring space between the function blocks and a floor plan indicating the relative placement of the function blocks. An overview of SPIDER which outlines the overall philosophy and the various tasks in chip planning, is given. Some experiments in chip planning with SPIDER are then described. Finally extensions to the scope of the planning tool are discussed. (With Raja S. Ramnarayan, PhD)

When designing systems-on-a-chip (SoCs), a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be used. The inclusion of such devices provides an efficient compromise between the flexibility of software and the performance of hardware, while at the same time allowing for postfabrication modification of the SoC. To automate the layout of reconfigurable subsystems for systems-on-a-chip, we present three alternative methods, namely Template Reduction, Circuit Generator, and Standard Cell methods. Template Reduction begins with a full-custom layout as a template that is a superset of the required resources, and removes those resources that are not needed by a given application domain. Circuit Generator takes advantage of the regularity that exists in FPGAs by using circuit generators to create the custom reconfigurable devices. Finally, Standard Cell automates the creation of circuits by using a standard cell library that has been optimized for reconfigurable devices. This paper presents algorithms for each of these approaches, and quantifies the relative quality in terms of area and delay.

2015

1997

We introduce a concept in VLSI layout which can nd applications in submicron design, quantum devices, and designing new ne-grain FPGAs. This concept is called Lattice Structure and it extends the concepts from 8] and 1, . In the regular arrangement of cells, every cell is connected to 4, 6 or 8 neighbors and to vertical, horizontal and diagonal buses. Methods for expanding arbitrary binary and multi-valued combinational functions to this layout are illustrated.

2012

Abstract There are two prominent problems with technology scaling: increasing design complexity and more challenges with interconnect design, including routability. High-level synthesis has been proposed to solve the complexity problem by raising the abstraction level. In this paper, we share our vision that high-level synthesis can potentially help the routability problem as well.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1994

Folding or topological compaction of array-based VLSI layouts is an important optimization step that is carried out after logic synthesis. In this paper, a new approach to two-dimensional multiple folding of array-based VLSI layouts is presented. From the specification of the problem a pair of intersection gruphs is created. We show that any pair of interval graphs that contain the intersection graphs as spanning subgraphs corresponds to a set of feasible foldings. Next, a complete and exact characterization of the folding problem is presented. In particular, it is shown that the set of all feasible foldings associated with a given pair of interval graphs corresponds to the set of independent colorings of a pair of compatibility graphs. The compatibility graphs are derived from a pair of interval graphs that contain the intersection graphs as spanning subgraphs. Thus, minimizing the area of a layout is tantamount to finding a pair of compatibility graphs such that the product of their chromatic numbers is minimum. As important as minimizing the area of a layout is, the ability to rapidly generate compact layouts over a wide range of aspect ratios is often equally, if not more, important. The interval graphbased formulation of the folding problem permits a controlled and systematic generation of compact layouts with varying aspect ratios. Efficient and provably correct algorithms to generate compact layouts that have a given number of rows or a given number of columns within their minimum and maximum possible values are given. The basic theory and methods are extended to include U 0 and other types of constraints. Finally, the results of experiments that were carried out on a large number of benchmark problems are given. These results are compared with those obtained by previously reported methods. I. INTRODUCTION TRUCTURED LOGIC refers to logic forms that exhibit S a high degree of regularity in their layout and interconnections. The use of such regular structures makes it possible to automatically generate the layout from an abstract specification. The most widely used regular structure is the Programmable Logic Array (PLA). In addition, a variety of other regular structures have been proposed over the past two decades. Examples include Doubly Folded Transistor Matrix [19], Metal-Metal Matrix (M 3) [12], Flexible Transistor Matrix (FTM) [8], and Gate Matrix [21]. All these forms have a two-dimensional structure consisting of an array of row and column elements. An element can be as simple as a single transistor or as complex as a small network of transistors. When used in their most basic form, the advantage Manuscript

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1995

System-level design involves making major design decisions without having accurate information on the eventual system characteristics. This paper presents a novel constraintdriven methodology to support system-level design. The software assists a designer or a tool in partitioning behavioral specifications onto multiple VLSI chips and in system design while satisfying hard constraints such as individual chip areas, chip pin counts, system throughput (inverse of system initiation interval) and system latency (delay). The software uses search and estimation techniques to perform comprehensive design-space exploration and evaluates partitions supplied by the user or by other synthesis software. The technique determines what design characteristics each partition must possess in order to satisfy area, pin, throughput and latency constraints. The paper also includes results of extensive experiments with the methodology.

Proceedings of MELECON '94. Mediterranean Electrotechnical Conference, 1994

In this paper we present a complete design and implementation of a CMOS cell library which supports a formal high level synthesis framework. The library contains the logic level models and VLSI layouts of all primitive functions of the Realization Specification Language (RSL) [l] as well as some commonly used functions which are also built using these basic functions. Modular design methodology is employed to support the expandibility of the basic cells. Example of a formal matrix-matrix multiplier is presented to illustrate the application of the cell library.

Proceedings of the IEEE, 2001

To implement high-performance global interconnect without impacting the placement and performance of existing blocks, the use of buffer blocks is becoming increasingly popular in structured-custom and block-based application specified integrated circuit methodologies. Recent works by Cong et al. (1999) and give algorithms to solve the buffer block planning problem. In this paper, we address the problem of how to perform the buffering of global multiterminal nets given an existing buffer block plan. We give provably good and heuristic algorithms for this problem based on a recent approach of Garg and Könemann (1998)

Proc. 9th VLSI Design …, 2005

Today's VLSI technology allows us to construct large, complex systems with million transistors on a single chip. Most of the existing high level synthesis systems give more priority to optimization of area, power, resource and time steps compared to interconnection cost, whereas the later becomes predominant with the technology scaling and increase in complexity. Further, field programmable gate arrays (FPGA) are now becoming attractive platform for prototyping. Programmable devices tend to have limited wiring resources between the data path elements. This work is concerned with the development of a CAD tool for HLS named, "Structured Architecture Synthesis Tool (SAST)", which incorporates structured architecture generation with special emphasis on optimization of interconnect area. The too takes a behavioral description written in 3-address form and generates synthesizable RTL codes with scripts for compliance with standard design tools like Synopsys, Magma etc.