FPGA based implementation of MPEG-2 compression algorithm

All current video coding standards are motion-compensated video coders (MCVC’s), where the current frame is predicted using a previously reconstructed frame and motion information, which needs to be estimated. The most common approach to exploit the temporal redundancy is motion-compensated prediction. MPEG-2 bit stream is basically just a series of coded frames one after the other. There are headers and time stamps to help decoders align audio and scrub through the bit stream, but those details are not important to understand the basic coding techniques. What follows is a brief description of MPEG-2 compression techniques without focusing on the exact specification of the bit stream, standard format used for satellite TV, digital cable TV, DVD movies, and HDTV. In addition, MPEG-2 is a commonly used format to distribute video files on the internet.

2012 6th International Conference on Signal Processing and Communication Systems, 2012

This paper presents the implementation of the JPEG compression on a field programmable gate array as the data are streamed from the camera. The goal was to minimise the logic resources of the FPGA and the latency at each stage of compression. The modules of these architectures are fully pipelined to enable continuous operation on streamed data. The designed architectures are detailed in this paper and they were described in Handel-C. The compliance of each JPEG module was validated using MATLAB. The resulting JPEG compressor has a latency of 8 rows of image readout plus 154 clock cycles.

Compression is playing a vital role in data transfer. Hence, Digital camera uses JPEG standard to compress the captured image. Hence, it reduces data storage requirements. Here, we proposed FPGA based JPEG encoder. The processing system is coupled with DCT and then it is quantized and then it is prepared for entropy coding to form a JPEG encoder.

Signal Processing: Image Communication, 1995

We address the problem of compressing IO-bits per pixel video using the tools of the emerging MPEG-2 standard, which is primarily targeted to &bits per pixel video. We show that an amplitude scalable compression scheme for IO-bit video can be developed using the MPEG-2 syntax and tools. We experimentally evaluate the performance of the scalable approach and compare it with the straightforward non-scalable approach where the lo-bit input is rounded to 8 bits and usual b-bit MPEG-2 compression is applied. In addition to general performance evaluation of scalable and non-scalable approaches, we also evaluate their multi-generation characteristics where the input video undergoes successive compression-decompression cycles. We show that it is possible to quantitatively analyze the multi-generation characteristics of the non-scalable approach using the theory of generalized projections. Enhancement Bit-stream c Deco&d Video (lo-bit) Decoded Video (a-bit, lower Bit-stream Store spat. res.) Fig. 2. Spatio-amplitude scalable IO-bit decoder.

Digital video compression technologies have become part of life, in the way visual information is created, communicated and consumed. Some application areas of video compression focused on the problem of optimizing storage space and transmission bandwidth (BW). The two dimensional discrete cosine transform (2-D DCT) is an integral part of video and image compression, which is used in Moving Picture Expert Group (MPEG) encoding standards. Thus, several video compression algorithms had been developed to reduce the data quantity and provide the acceptable quality standard. In the proposed study, the Matlab Simulink Model (MSM) has been used for video coding/compression. The approach is more modern and reduces error resilience image distortion.

International Journal of Engineering Research and, 2015

Discrete Cosine Transform (DCT) is an essential tool of most of the image and video compression standards, because of its better energy compaction properties. As the demands for the two-way video transmission and video messaging over mobile communication systems increasing, the encoding complexity needs to be optimized. The threedimensional discrete cosine transform (3D-DCT) and its inverse (3D-IDCT) can be used as an alternative to motion compensated transform coding, because it extends the spatial compression property of 2D-DCT to spatial-temporal compression of video data. In the proposed architecture, a low complexity video encoder using 3D-DCT has been presented. This method converts video data into three-dimensional video cube of 8×8×8 pixels and 3D-DCT is then performed, followed by quantization, zigzag scanning and entropy encoding. The three-dimensional DCT circuit can be realized using few additions and subtractions, thus increasing the area efficiency with low complexity. The proposed architecture is coded in Verilog HDL, synthesized in Xilinx ISE design suite 14.2 and physically realized as a digital prototype circuit using Xilinx Virtex-5 FPGA.

IEEE Access, 2020

Versatile video coding (VVC) will be released by 2020, and it is expected to be the nextgeneration video coding standard. One of its enhancements is multiple transform selection (MTS) for core transform. MTS uses three different types of 2D discrete sine/cosine transforms (DCT-II, DCT-VIII and DST-VII) and up to 64 × 64 transform unit sizes. With this schema, significant enhancements of the compression ratio are obtained at the expense of more computational complexity on both encoders and decoders. In this paper, a deeply pipelined high-performance architecture is proposed that implements the three transforms for sizes from 4 × 4 to 64 × 64 according to working draft 4 of the standard. The design has been described in very high-speed integrated circuit hardware description language (VHDL), and it has been prototyped in a system on a programmable chip (SoPC). It is able to process up to 64 fps@3840 × 2.160 for 4 × 4 transform sizes. To the best of our knowledge, this is the first implementation of an architecture for VVC MTS supporting the 64 × 64 size. INDEX TERMS FPGA, hardware architecture, multiple transform selection, pipeline, SoPC, versatile video coding. * The architecture proposed in this paper has been implemented and tested in accordance with WD 4. † The number of multiplications required by a direct implementation of a 2D N×N point DCT/DST is N 2 .

In the MPEG-1 multimedia standard, no encoding scheme is defined, but a generally accepted scheme includes the following building blocks: discrete cosine transform, quantization, zig-zag scanning, run-level coding, variable-length encoding, and motion estimation. In this paper, we describe the investigation into how such building blocks can be implemented in reconfigurable hardware, more specifically field-programmable gate arrays (FPGAs). The investigation focuses on the area requirements and the expected speed of such building blocks. Since our investigation will be applied to increase the performance of a programmable processor (running an MPEG-1 software application) augmented with an FPGA structure, we have selected four known to be time-consuming operations for implementation in FPGA: forward discrete cosine transform, the quantization, the Huffman encoding, and the sum of absolute differences. All designs were implemented by writing high-level VHDL code and target two FPGA families from Altera Corp.: FLEX10K and APEX20K. The synthesis results show that the implementations can be clocked between 36 and 162 MHz and that the area utilization is small compared to the largest available FPGA chip within the APEX20K family.

International Journal of Engineering Research and Technology (IJERT), 2015

https://www.ijert.org/fpga-implementation-of-low-complexity-video-encoder-using-optimized-3d-dct https://www.ijert.org/research/fpga-implementation-of-low-complexity-video-encoder-using-optimized-3d-dct-IJERTV4IS070813.pdf Discrete Cosine Transform (DCT) is an essential tool of most of the image and video compression standards, because of its better energy compaction properties. As the demands for the two-way video transmission and video messaging over mobile communication systems increasing, the encoding complexity needs to be optimized. The three-dimensional discrete cosine transform (3D-DCT) and its inverse (3D-IDCT) can be used as an alternative to motion compensated transform coding, because it extends the spatial compression property of 2D-DCT to spatial-temporal compression of video data. In the proposed architecture, a low complexity video encoder using 3D-DCT has been presented. This method converts video data into three-dimensional video cube of 8×8×8 pixels and 3D-DCT is then performed, followed by quantization, zigzag scanning and entropy encoding. The three-dimensional DCT circuit can be realized using few additions and subtractions, thus increasing the area efficiency with low complexity. The proposed architecture is coded in Verilog HDL, synthesized in Xilinx ISE design suite 14.2 and physically realized as a digital prototype circuit using Xilinx Virtex-5 FPGA.

Journal of Real-Time Image Processing, 2012

Despite the diversity of video compression standard, the motion estimation still remains a key process which is used in most of them. Moreover, the required coding performances (bit-rate, PSNR, image spatial resolution,etc.) depend obviously of the application, the environment and the network communication. The motion estimation can therefore be adapted to fit with these performances. Meanwhile, the real time encoding is required in many applications. In order to reach this goal, we propose in this paper a flexible hardware implementation of the motion estimator which enables the integer motion search algorithms to be modified and the fractional search as well as variable block size to be selected and adjusted. Hence this novel architecture, especially designed for FPGA targets, proposes high-speed processing for a configuration which supports the variable size blocks and quaterpel refinement, as described in H.264. The proposed low-cost architecture based on Virtex 6 FPGA can process integer motion estimation on 1080 HD video streams respectively at 13 fps using full search strategy (108k MBlocks/s) and up to 223 fps using diamond search (1.8M MBlocks/s). Moreover subpel refinement in quaterpel mode is performed at 232k Macroblocks/s.