Design and Analysis of Low Power SRAM using CMOS Technology

IEEE Journal of Solid-State Circuits, 1995

Absauct-The recent trends in portable computing technologies have established the need for energy efficient design strategies. To achieve minimum energy design goals, system designers need a technique to accurately model the energy consumption of their design alternatives without performing a full physical design and full-circuit simulation. This paper presents and compares five approaches for modeling the energy consumption of CMOS circuits. These five modeling approaches have been chosen to represent the various levels of model complexity and accuracy found in the current literature. These modeling approaches are applied to the energy consumption of SRAM's to provide examples of their use and to allow for the comparison of their modeling qualities. It was found that a mixed characterization model-ing a CVz prediction for digital subsections and fitted simulation results for the analog subsections-is satisfactory (within f l process variation) for predicting the absolute energy consumed per cycle. This same model is also very good (within 2%) for predicting an optimum organization for the internal structures of the SRAM. Several common architectures and circuit designs for SRAM's are analyzed with these models. This analysis shows that global, rather than local improvements, produce the largest energy savings.

International Journal of Engineering Sciences & Research Technology, 2013

Low power is an important factor when designing chips as well as memories. That is driven by the increasing complexity and operating speeds of microprocessors and the demands of portable electronic Many techniques have been developed for getting low power. This term paper report includes a summary of conventional low power circuit design techniques, as well as a discussion on low power memory. Those discussed will be techniques for reducing power in memory, including intelligent and OS Controlled refresh in DRAMs, multi divided arrays and power/performance ratios, and a survey of low power SRAM and DRAM. The paper will also discuss power requirements of microprocessors, as one aspect of IRA DRAM.

International Journal of Computer Applications, 2014

Power reduction in electronic and computing system is one of the basic requirements and is increasingly demanded for the battery operated mobile systems. Although the power is required for every part of the system but the devices accessed most frequently (processor, DRAM) are takes special attention, because the improvement in power dissipation in these devices can dramatically reduce the overall power requirement. Since the many approaches have been already proposed for the power reduction in processor this paper focuses on the power reduction in DRAM. The DRAM may be considered as most power consuming device after processor, even when it is idle. Although the DRAMs inherently supports different power saving modes, like selfrefresh and power-down, but these techniques are not as efficient and also causes the unwanted delay which in noncomprisable for the many multimedia applications. Hence in this paper, we propose and evaluate an efficient DRAM rank grouping and power gating technique for power-saving that optimizes the power saving with marginal performance degradation. The proposed approach is developed and tested on several multimedia operations and the experimental results show that it reduces the total DRAM energy consumption between 56% and 183%(approx)at a negligible performance penalty between 3% and 5%(approx).

BEST Journals, 2014

Reliability is a major concern in the microprocessor industry. SRAM plays a significant role in energy consumption due to increases in computing power. In order to get high efficiency in the SRAM, the array structure has to be modified. In traditional practices where SRAM array enclose more number of rows than columns. Previously proposed techniques improve the efficiency by 10% for 8kbit and 40% for 64kbit for same SRAM bit density and same supply voltage. The proposed techniques such as deep sub micron technology are implemented for getting better reliability. Many proposed design concern only on the low power dissipation but generally degrade response time. The power consumption of the system on chip devices having SRAMs increase largely with technology scaling because at low scale, Gate leakage current, sub threshold current, tunnelling plays a significant role in the SRAM operation. This work reveals that better SRAM energy efficiencies can be achieved with a wider SRAM array structure with fewer rows than columns particularly at low supply voltage. In this proposed 10T cell shows better performance with reduced power consumption and different Temperature as against conventional 8T SRAM.

IEEE Transactions on Multimedia, 2012

This paper presents domain-specific techniques to reduce DRAM energy consumption for image data access in video processing. In mobile devices, video processing is one of the most energy-hungry tasks, and DRAM image data access energy consumption becomes increasingly dominant in overall video processing system energy consumption. Hence, it is highly desirable to develop domain-specific techniques that can exploit unique image data access characteristics to improve DRAM energy efficiency. Nevertheless, prior efforts on reducing DRAM energy consumption in video processing pale in comparison with that on reducing video processing logic energy consumption. In this work, we first apply three simple yet effective data manipulation techniques that exploit image data spatial/temporal correlation to reduce DRAM image data access energy consumption, then propose a heterogeneous DRAM architecture that can better adapt to unbalanced image access in most video processing to further improve DRAM energy efficiency. DRAM modeling and power estimation have been carried out to evaluate these domain-specific design techniques, and the results show that they can reduce DRAM energy consumption by up to 92%.

International Journal of Engineering & Technology, 2018

In deep sub-micron technologies, high number of transistors is mounted onto a small chip area where, SRAM plays a vital role and is considered as a major part in many VLSI ICs because of its large density of storage and very less access time. Due to the demand of low power applications the design of low power and low voltage memory is a demanding task. In these memories majority of power dissipation depends on leakage power. This paper analyzes the basic 6T SRAM cell operation. Here two different leakage power reduction approaches are introduced to apply for basic 6T SRAM. The performance analysis of basic SRAM cell, SRAM cell using drowsy-cache approach and SRAM cell using clamping diode are designed at 130nm using Mentor Graphics IC Studio tool. The proposed SRAM cell using clamping diode proves to be a better power reduction technique in terms of power as compared with others SRAM structures. At 3.3V, power saving by the proposed SRAM cell is 20% less than associated to basic 6T ...

2011

SRAM is a type of semiconductor memory which does not need to be periodically refreshed. With scaling down of the technology, the feature sizes have shrink more and more and miniaturization at chip level has occurred. But as a trade off, the demand for power has also increased. SRAM continues to be a critical component across a gamut of microelectronics applications. Leakage is a serious problem particularly for SRAM. To address sub threshold leakage issue sleepy stack approach is used .The sleepy stack SRAM cell design, is a new technique which involves changing the circuit structure as well as using high-V th. The sleepy stack technique achieves greatly reduced leakage power while maintaining precise logic state in sleep mode. This paper compares performance of SRAM using sleepy stack approach with that of conventional design. The impact of temperature and voltage on the performance of sleepy stack design is also analyzed. Berkeley Predictive Technology Model (BPTM), level 49 targeting 0.18μm technology is used. The design is successfully simulated and analyzed using HSPICE tools.

IRJET, 2023

The cache memory design of microprocessors makes use of Static Random-Access Memory (SRAM) cells. Their efficiency is crucial because they are an integral part of the central computer system. Only 10-15 percent of a modern system on a chip's (SoC) transistors are dedicated to logic, whereas the rest are used for cache memory, increasing the performance strain. On top of that, the AI-reliant nature of today's implantable, portable, as well as wearable electronic equipment highlights the need for a robust SRAM architecture for CIM. Modern mobile communication devices include ample storage space for users' extensive media collections. Here, we adapt the Multi-threshold CMOS design to create a low-power SRAM cell. Power usage and read/write cycle Access Time can be lowered by using CMOS transistors with various threshold voltages. This work proposes a novel approach to reducing leakage in the idle state to cut down on power usage. The power usage of an SRAM cell is affected by the temperature, size of the transistors as well as the voltage used in the test. Data storage is an important function of several electronic components, specifically digital ones. The overall power usage of an SRAM is heavily influenced by leakage current. The research utilized a 1-bit 6T SRAM cell to construct a 1 KB memory array using CMOS technology and 0.6 volts for the supply voltage. In this section, we use deep submicron (130nm, 90nm, and 65nm) CMOS technology and the six-transistor (6T) SRAM cell to analyze how varying topologies impact the performance of a 12T SRAM array.

International Journal of Recent Trends in Engineering and Research, 2017

The main issue in VLSI design are optimizing speed, scaling in silicon technology and increased packing density. These issues account for increased power dissipation in SoC (System on Chips) making them unsuitable for portable operations. Since SRAM consist of almost 60% of VLSI circuits, hence, it is needed that a low power SRAM design to maximize the run time with minimum requirements on size, battery life and weight allocated to batteries. In this paper the basic operation of SRAM along with techniques to reduce total power dissipation are discussed.

IJRET, 2013

Technology scaling results in significant increase of leakage currents in MOS devices due to which power consumption in Nano scale devices increases. As memory accounts for the largest share of power consumption, thus there is need to design such a memory which will consume less power. Through this paper, we propose a systematic approach by Block partitioning which provides a methodology for reducing the dynamic power consumption of SRAM (static random access memory). Dynamic power dissipation in memory is due to charging/discharging of long capacitive lines (bit line and world line). So by block partitioning our goal is to reduce length of world line as well as bit line capacitances. instead of implementing 1KB SRAM at a time we are designing four blocks of 256 byte RAM, which reduces world line from 1024 bits to 256 bits. We implemented our design on TANNER TOOL using 180 nm technology

International Journal of Advanced …, 2011

The growing demand for high density VLSI circuits and the exponential dependency of the leakage current on the oxide thickness is becoming a major challenge in deep-submicron CMOS technology. In this work, a novel Static Random Access Memory (SRAM) Cell is proposed targeting to reduce the overall power requirements, i.e., dynamic and standby power in the existing dual-bit-line architecture. The active power is reduced by reducing the supply voltage when the memory is functional and the standby power is reduced by reducing the gate and sub-threshold leakage currents when the memory is idle. This paper explored an integrated approach at the architecture and circuit level to reduce the leakage power dissipation while maintaining high performance in deep-submicron cache memories. The proposed memory bit-cell makes use of the pMOS pass transistors to lower the gate leakage currents while fullsupply body-biasing scheme is used to reduce the sub-threshold leakage currents. To further reduce the leakage current, the stacking effect is used by switching off the stack transistors when the memory is ideal. In comparison to the conventional 6T SRAM bit-cell, the total leakage power is reduced by 50% while the cell is storing data '1' and 46% when data '0' at a very small area penalty. The total active power reduction is achieved by 89% when cell is storing data 0 or 1. The design simulation work was performed on the deep-sub-micron CMOS technology, the 45nm, at 25 0 C with V DD of 0.7V.

IEEE Transactions on Electron Devices, 2007

With technology scaling, there is a strong demand for smaller cell size, higher speed, and lower power in SRAMs. In addition, there are severe constraints for reliable read-and-write operations in the presence of increasing random variations that significantly degrade the noise margin. To understand these tradeoffs clearly and find a power-delay optimal solution for scaled SRAM, sequential quadratic programming is applied for optimizing 6-T SRAM for the first time. We use analytical device models for transistor currents and formulate all the cell-operation requirements as constraints in an optimization problem. Our results suggest that, for optimal SRAM cell design, neither the supply voltage (V dd) nor the gate length (L g) scales, due to the need for an adequate noise margin amid leakage and threshold variability and relatively low dynamic activity of SRAM. This is true even with technology scaling. The cell area continues to scale despite the nonscaling gate length (L g) with only a 7% area overhead at the 22-nm technology node as compared to simple scaling, at which point a 3-D structure is needed to continue the area-scaling trend. We also find that the suppression of gate leakage helps to reduce the power in ultralow-power SRAM, where subthreshold leakage is minimized at the cost of increase in cell area.

VLSI Design, 2014

In chip-multiprocessors (CMP) architecture, the L2 cache is shared by the L1 cache of each processor core, resulting in a high volume of diverse data transfer through the L1-L2 cache bus. High-performance CMP and SoC systems have a significant amount of data transfer between the on-chip L2 cache and the L3 cache of off-chip memory through the power expensive off-chip memory bus. This paper addresses the problem of the high-power consumption of the on-chip data buses, exploring a framework for memory data bus power consumption minimization approach. A comprehensive analysis of the existing bus power minimization approaches is provided based on the performance, power, and area overhead consideration. A novel approaches for reducing the power consumption for the on-chip bus is introduced. In particular, a serialization-widening (SW) of data bus with frequent value encoding (FVE), called the SWE approach, is proposed as the best power savings approach for the on-chip cache data bus. The...

The ever increasing power consumption of the components within a computing system have resulted in tremendous costs and substantial failure rates which are a roadblock in achieving optimal performance at reasonable costs. To mitigate these issues, strategies that reduce the dynamic power consumption of these components are needed. In this paper, we review a survey a subset of those strategies with their salient features and their efficacy in providing energy savings. The paper reviews energy saving strategies proposed and verified in both simulators and real-time systems.