Design of a MCML gate library applying multiobjective optimization

Integration, 2018

Most existing methodologies use either Logical Effort (LE) theory or stand-alone optimization algorithms for automated transistor sizing of CMOS logic circuits. LE theory optimizes a logic circuit only with respect to speed while it completely ignores power and area. Whereas heuristic algorithms when used as a stand-alone approach for optimization lead to huge computational effort since there is no predefined technique to apply constraints on transistor sizes in order to limit the design space for target specifications. The problem has been resolved in this paper by utilizing delay sensitivity factor based on LE theory proposed by Alioto et. al. [1] for estimating the highest operating speed of a logic circuit and determining the upper bound on the size of transistors. Recently proposed heuristic algorithms viz. Interior Search Algorithm (ISA) [2] and Gravitational Search Algorithm (GSA) [3] have been utilized further to converge towards minimum power-delay-area product (PDAP). Simulation results for various test circuits indicate upto 35.1% and 63.8% improvement in power-delay product (PDP) and PDAP respectively in 130nm/1.2V TSMC CMOS technology. PVT analysis and Monte Carlo simulations have been used to further validate the effectiveness of the proposed methodology.

We show the behavior of the generations of two multi-objective evolutionary algorithms (MOEAs) for the optimal sizing of two mixed-mode circuits. The non-sorting genetic algorithm (NSGA-II), and the MOEA based on decomposition (MOEA/D) are used to size a second generation current conveyor (CCII+) and a current-feedback operational amplifier (CFOA). Both MOEAs take into account design constraints, and link HSPICE to evaluate the electrical characteristics of the CCII+ and CFOA. Differential evolution is used as genetic operator to show the behavior of the generations of the two MOEAs.

Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06, 2006

With shrinking technology, the timing variation of a digital circuit is becoming the most important factor while designing a functionally reliable circuit. Gate sizing has emerged as one of the efficient way to subside the yield deterioration due to manufacturing variations. In the past single-objective optimization techniques have been used to optimize the timing variation whereas on the other hand multi-objective optimization techniques can provide a more promising approach to design the circuit. We propose a new algorithm called YOGA, based on multi-objective optimization technique called Non-dominated Sorting Genetic Algorithm (NSGA). YOGA optimizes a circuit in multi domains and provides the user with Pareto-optimal set of solutions which are distributed all over the optimal design spectrum, giving users the flexibility to choose the best fitting solution for their requirements. YOGA overcomes the disadvantages of traditional optimization techniques, while even providing solutions in very stringent bounds.

2011

Automated Complementary Metal Oxide Semiconductor (CMOS) logic circuit design leads to the reduction in costs associated with manpower and manufacturing time. Conventional methods use repetitive manual testing guided by Logical Effort (LE). Our previous works have shown the applicability of the Particle Swarm Optimization (PSO) algorithm guided by LE in searching for optimal gate widths for CMOS design. In this paper, we present a PSO variant called Mutative Particle Swarm Optimization (MPSO) to automate the sizing process of CMOS circuit design on an 8-stage full adder circuit. In our work, we choose gate widths inside the circuit as parameters to be optimized in order to achieve the target delay, with the solution fitness guided by the LE method. Various parameters, such as swarm size and iterations were tested under different initialization conditions to verify MPSO's performance on a 8-stage full-adder circuit. Results have indicated that the MPSO algorithm was an effective method to apply to the circuit design problem, with high convergence rates observed.

Internatial Rev Modell …, 2009

Lecture Notes in Computer Science, 2005

In this work, the optimization of circuits design by using multiobjective evolutionary algorithm is addressed. This methodology enable to deal with circuit specifications-formulated as objective functions-that can be conflicting and want to be optimize at the same time. After the optimization process, a set of different trade-off solutions for the design of the circuit is obtained. This way, SPEA (Strength Pareto Evolutionary Algorithm) has been tested as optimizer of an hybrid CBL/CMOS configurable cell. As a result, some conclusions about the optimized values of the transistor sizes of this cell in order to minimized some power comsumption and delay timing specifications are obtained.

International Journal on Cybernetics & Informatics, 2016

A novel approach for optimizing the transistor dimensions of two stage CMOS op-amp using Multi-Objective Genetic Algorithm (MOGA) is presented. The proposed approach is used to find the optimal dimensions of each transistor to improve op-amp performances for analog and mixed signal integrated circuit design. The aim is to automatically determine the device sizes to meet the given performance specifications while minimizing the cost function such as power dissipation and a weighted sum of the active area. This strongly suggests that the approach is capable of determining the globally optimal solutions to the problem. Exactness of performance prediction in the device sizing program (implemented in MATLAB) maintained. Here Six parameters are considered i.e., open loop gain, Phase Margin (PM), Area (A), Bandwidth of unity Gain (UGB), Power Consumption (P) and Slew Rate (SR). The circuit is simulated in cadence(Virtuoso Spectre) 0.18um CMOS technology.

2011

Automated Complementary Metal Oxide Semiconductor (CMOS) logic circuit design leads to the reduction in costs associated with manpower and manufacturing time. Conventional methods use repetitive manual testing guided by Logical Effort (LE). LE provides an easy way to compare and select circuit topologies, choose the best number of stages for path and estimate path delay. In this paper, we propose the Mutative Particle Swarm Optimization (MPSO) algorithm as a method to automate the process of CMOS circuit design by approaching the design process as an optimization problem. In our work, we choose gate widths inside the circuit as parameters to be optimized in order to achieve the target delay, and its fitness is guided by the LE method. Various parameters, such as swarm size and iterations were tested under different initialization conditions to verify MPSO's performance on a 12-stage ripple carry adder circuit. Results have indicated that the MPSO algorithm was an effective method to apply to the circuit design problem, with high convergence rates observed.

Foundations and Trends® in Electronic Design Automation, 2012

Gate Sizing and V t Assignment Fundamentals 3.1 Delay Trade-offs 3.2 Power Trade-offs 3.3 Gate Sizing Examples 4 Methods for Discrete Gate Sizing and V t Assignment 4.1 Preliminaries 4.2 Score and Rank Algorithms 4.3 Slack and Delay Budgeting Methods 4.4 Continuous Sizing Based Methods 4.5 Dynamic Programming Based Algorithms 4.6 Lagrangian Relaxation 4.7 Slew Targeting Methods 4.8 Linear Programming Based Assignment Methods 4.9 Summary 5 Comparing Sizing and Assignment Methods 5.1 Setting Up Experiments 5.2 Post-layout Considerations 5.3 Comparisons

International Journal of Reconfigurable and Embedded Systems (IJRES), 2013

In this paper, we proposed a novel heuristic method based on Imperialist competitive Algorithm (ICA) to design combinational logic modules which performing different arithmetic functions. According to conventional methods, for multi functional circuit, a distinct circuit is designed for each specific function and then all of them are combined together with multiplexer(s) to have desired circuit. But in our proposed method the whole circuit structure is designed and optimized in one procedure by ICA Algorithm. We tried to optimize the area of circuit by reducing the number of transistors forming logic gates. Simulation results show that our method significantly reduces the number of transistors and gates and accordingly the circuit area.