A New Error Correction Code

Errordetectionandcorrectionwhichhasbeenused in communication and memory design is becoming increasingly important in fault tolerant logic circuit design. As a result of the aggressive technology scaling, the current high-density integrated circuits are easily succumbed to faulty operations generated from many sources including stuck-at-faults, radiation induced faults, or malicious eavesdropper attacks. The currently used techniques like low-density parity-check (LDPC) and Hamming code based fault masking to mitigate bit flips in the digital circuits are either single bit error correcting or multiple error correctable with Bose-Choudhury-Hocquenghem (BCH) and Reed-solomon based methods with very large overheads. This paper introduce a novel cross code based method that can correct multiple errors with minimal compromise in error correction capability and area. The key idea of the novel method proposed in this paper is that do not correct all the errors but minimize their probability being escaped. Experimental results of the proposed methods show that the following: (1) area overhead is 101% for Hamming cross code and 106% for BCH cross code for a 90-bit finite field multiplier and (2) 150% for Hamming cross code and 170% for BCH cross codes for practically used 163bit digit serial polynomial basis multiplier. Thus, the proposed methods are significantly efficient compared to Triple Modular Redundancy (TMR), LDPC, Hamming based methods in terms of area overhead and also the first attempted approach to a low complexity multiple error correctable digit serial multiplier to the best of the authors knowledge.

Soft errors which are random errors induced by radiations may be produced due to transient faults and upsets in electronic systems. From the survey, it has been observed that the existing error correcting techniques and models have some limitations. The conventionally used error detection method named Triple Modular Redundancy (TMR) method has large overhead which makes it uneconomical. In this paper, the existing techniques like Time Redundancy based error Detection (TRDED) has been implemented and verified for different intervals of errors. It has been observed that only particular errors can be detected and no corrections are done. The modified circuits abbreviated as SETTOFF can be used for Soft Error and Timing Error Tolerant Flip Flop. These circuits which have both error correction and detection has been implemented and verified for different intervals of time. Since the chances of induced errors are increasing, there is a great necessity for developing a technique to provide more reliability and performance. Targeting towards the above features, self-checking register architecture for multi-bit error detection has been proposed and analyzed using Xilinx ISE Simulator for transient fault occurrence and has been analyzed.

Journal of Computer Science, 2015

The theory and application of (t-EC-AUED) codes was presented and among the methods proposed in literature, the most efficient was chosen and a software was written for encoding and decoding of the codes. Comparison and evaluation of the construction techniques were carried out. A tError Correction (EC)/All Unidirectional Error Detection (AUED) codes are constructed by appending a single check symbol to a linear t-EC code to achieve the AUED property.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000

Abstract| This paper proposes a methodology, implemented in a tool, to automatically generate the main classes of Error Control Codes (ECCs) widely applied in computer memory systems to increase reliability and data integrity. New code construction techniques extending the features of previous Single Error Correcting (SEC) -Double Error Detecting (DED) -Single Byte Error Detecting (SBD) codes have been integrated in the tool. The proposed techniques construct systematic odd-weight-column SEC-DED-SBD codes with Odd-bit-per-byte Error Correcting (OBC) capabilities to enhance reliability in high speed memory systems organized as multiple-bit-per-chip or card. The proposed tool chooses the best suited error control code for the characteristics of the application and the design constraints and returns the VHDL description of the encoding/decoding circuits. The tool has been successfully applied for the design of a 64 data bit ECC contained in an ASIC designed for a multiprocessor system.

1994

Abstract The basic theory of t-UEC d-UED codes is developed. Methods for construction of such codes from symmetric error-correcting and asymmetric error-correcting codes are developed. Some bounds for t-EC d-UED codes are improved. Encoding/decoding procedures for these codes are discussed

IEEE Transactions on Computers, 2000

Russian Microelectronics, 2019

The pace of development of the microelectronic industry and the progress in the development of computer-aided design tools make problems associated with the development of combinational circuits that are resistant to short self-clearing faults relevant again. These faults occur due to a combination of many different factors, such as extreme operating conditions and transition to nanometer design standards. Structural redundancy methods are often used to solve this problem by the principles of the noiseless coding theory to protect information during its transmission over communication channels. However, these methods have a significant drawback, i.e., large structural redundancy. In this paper, we propose to use an approach based on the synthesis of fault-tolerant combinational circuits based on the spectral R-code to solve the problem of developing fault tolerant combinational circuits. If a specific part of the coder is protected using special technological means, this code can correct a single-bit error and detect a double-bit error. The resulting circuit has less structural redundancy compared to the traditional method of triple modular redundancy (TMR). An approach is also proposed based on partitioning circuit outputs into groups followed by synthesizing faulttolerant combinational circuits based on the R-code, which increases the probability of error detection/correction, to minimize the probability of multiple-bit errors within a combinational circuit. The paper presents the results of a series of numerical experiments that show the efficiency of the proposed approaches.

The technology advancements in scaling-smaller dimensions, higher integration densities, and lower operating voltages-has lead to reduction of reliability not only in extreme radiation environments like spacecraft and avionics , but also in terrestrial environments. SRAM memory failure rates are increasing significantly, thereby raising a major reliability problem for many applications. This paper presents an error-detection method for difference-set cyclic codes with majority logic decoding. Majority logic decodable codes are suitable for memory applications due to their capability to correct a large number of errors. However, they require a large decoding time that impacts memory performance. The proposed fault-detection method significantly reduces memory access time when there is no error in the data read. The technique uses the majority logic decoder itself to detect failures, which makes the area overhead minimal and keeps the extra power consumption low. This technique will tend to correct burst errors of any length.

Lecture Notes in Electrical Engineering, 2021

ijmra.us

During digital data transmission in digital communication system, noise is added and physical defects in the communication medium can cause random errors during data transmission. Error coding is a method of detecting and correcting these errors to ensure information is transferred intact from its source to destination. Error coding is used for fault tolerant computing in computer memory, magnetic and optical data storage media, satellite and deep space communications, network communications, cellular telephone networks, and almost any other form of digital data communication. Error coding uses mathematical formulas to encode data bits at the source into longer bit words for is transmission. Decoding of the code word is possible at side of receiver. The extra bits in the code word provide redundant bit, according to the coding scheme used, will allow the destination to use the decoding process to determine if the communication medium's expected error rate, signal to noise ratio and whether or not data retransmission is possible. Faster processors and better communications technology make more complex coding schemes, with better error detecting and correcting capabilities, possible for smaller embedded systems, allowing for more robust communications. The proposed title discloses a novel approach for detection and correction of binary stream transmission errors such as random errors and bursts errors in digital communication systems. The fault detection and correction will be accomplished by Linear Block Code, Convolution Code or concatenated Code Error-Control Coding techniques.

Computer Design, 1978

IEEE Transactions on Computers, 1990

Abslmct-Codes are developed for detecting unidirectional errors in t bytes simultaneously ( t-UBED) while also providing all unidirectional error detection (AUED). These classes of codes differ from purely all unidirectional error detecting codes in that the errors in one byte may be of the form 1 -0 while in another byte they may be of the form 0 + 1. The codes utilize two bytes for parity check information. As an example, a code providing 3-UBED+AUED protection for up to 12 information bytes of 8 bits each can be constructed.

International Journal of Basic and Applied Sciences, 2017

Data communication is the process of exchanging information between sender and receiver. The basic objective of a communication system is to transmit data which is free of error. Advancement in technology has made various revolutions in data communication, with which come greater chances that the data to be sent becomes corrupted. The data is transferred from various transmission impairments and during this period various factors affect the signal, the data received at the receiver is different from the data transmitted. As digital signals exist in two states either high or low, the error occurred will change its state. In today's advance world different techniques have been made to detect and remove error in the data. The paper delivers a simple error correction and detection method which can detect and correct single, multiple and burst error simply by using XNOR and COMPLEMENT. In the proposed method key is calculated and is send as a redundant bits at the receiver different ...

Proceedings. International Symposium on Information Theory, 2005. ISIT 2005., 2005

Linear codes for error detection on a q-ary symmetric channel are studied. It is shown that for given dimension k and minimum distance d, there exists a value µ(d, k) such that if C is a code of length n ≥ µ(d, k), then neither C nor its dual C ⊥ are good for error detection. For d ≫ k or k ≫ d good approximations for µ(d, k) are given. A generalization to non-linear codes is also given.

2010

In order to achieve fault tolerance, highly reliable system often require the ability to detect errors as soon as they occur and prevent the speared of erroneous information throughout the system. Thus, the need for codes capable of detecting and correcting byte errors are extremely important since many memory systems use b-bit-per-chip organization. Redundancy on the chip must be put to make fault-tolerant design available. This paper examined several methods of computer memory systems, and then a proposed technique is designed to choose a suitable method depending on the organization of memory systems. The constructed codes require a minimum number of check bits with respect to codes used previously, then it is optimized to fit the organization of memory systems according to the requirements for data and byte lengths.