Filling algorithms and analyses for layout density control

Proceedings of the 2000 conference on Asia South Pacific design automation - ASP-DAC '00, 2000

Abstract| Chemical-mechanical polishing (CMP) and other manufacturing steps in very deep submicron VLSI have varying e ects on device and interconnect features, depending on local characteristics of the layout. To enhance manufacturability and performance predictability, we seek to make the layout uniform with respect to prescribed density criteria, by inserting \ ll" geometries into the layout. We propose several new Monte-Carlo based lling methods with fast dynamic data structures and report the tradeo between runtime and accuracy for the suggested methods. Compared to existing linear programming based approaches, our Monte-Carlo methods seem very promising as they produce nearly-optimal solutions within reasonable runtimes.

2007 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC), 2007

2005

Nanometer VLSI design is greatly challenged by the growing interdependency between manufacturing and design. Existing approaches in design for manufacturability (DFM) are still mostly post design, rather than during design. To really bridge the gap between design and manufacturing, it is important to model and feed proper manufacturing metrics and cost functions upstream, especially at the key physical layout optimization stages such as routing and placement, to have major impacts. In this paper, we show several aspects of the true manufacturability-aware physical design, from lithographyaware routing, to redundant-via aware routing, to CMP aware floorplanning and placement, and show their promises.

2007 Asia and South Pacific Design Automation Conference, 2007

Thickness range, i.e. the difference between the highest point and the lowest point of the chip surface, is a key indicator of chip yield. This paper presents a novel metal filling algorithm that seeks to minimize the thickness range of the chip surface during the copper damascene process. The proposed solution considers the physical mechanisms in the damascene process, namely ECP (which is the process used to deposit Cu in the trenches) and CMP (which is the process used to polish Cu after ECP), that affect thickness range. Key predictors for the final thickness range, which is the thickness range after ECP & CMP, that can be computed efficiently are identified and used to drive the metal filling process. To the best of our knowledge, this is the first metal filling algorithm that uses an ECP model among other things to guide metal filling. Experimental results are very promising and indicate that the proposed method can significantly reduce the thickness range after metal filling. This is in sharp contrast with the density-driven approaches which often increase the thickness range after metal filling, thereby potentially adversely impacting yield. In addition, the proposed method inserts significantly smaller amount of fill when compared to the densitydriven approaches. This is desirable as it limits the impact of metal filling on timing.

2001

Abstract| To i m p r o ve manufacturability and performance predictability, w e seek to make a l a yout uniform with respect to prescribed density criteria, by inserting ll" geometries into the layout. Previous approaches for at layout density control are not scalable due to the necessity of solving very large linear programs, the large data volume of the solution, and the impact of hierarchy-breaking on veri cation. In this paper, we give the rst methods for hierarchical layout density c o n trol for process uniformity. Our approach trades o naturally between runtime, solution quality, and output data volume. We also allow generation of compressed GDSII of ll geometries. Our experiments show that this hybrid hierarchical lling approach s a ves data volume and is scalable, while yielding solution quality that is competitive with existing Monte-Carlo and linear programming based approaches.

IEEE Transactions on Semiconductor Manufacturing, 1997

In this paper, we address the problem of identifying and evaluating "critical features" in an integrated circuit (IC) layout. The "critical features" (e.g., nested elbows and open ends) are areas in the layout that are more prone to defects during photolithography. As feature sizes become smaller (sub-micron range) and as the chip area becomes larger, new process techniques (such as, using phase shifted masks for photolithography), are being used. Under these conditions, the only means to design compact circuits with good yield capabilities is to bring the design and process phases of IC manufacturing closer. This can be accomplished by integrating photolithography simulators with layout editors. However, evaluation of a large layout using a photolithography simulator is time consuming and often unnecessary. A much faster and efficient method would be to have a means of automatically identifying "critical features" in a layout and then evaluate the "critical features" using a photolithography simulator. Our technique has potential for use either to evaluate the limits of any new and nonconventional process technique in an early process definition phase or in a mask house, as a postprocessor to improve the printing capability of a given mask. This paper presents a CAD tool (An Integrated CAD Framework) which is built upon the layout editor, Magic, and the process simulator, Depict 3.0, that automatically identifies and evaluates "critical features."

CMP fills are inserted to make metal density uniform and hence reduce post-polish height variations. Classical methods to insert fills focus on metal density uniformity, but do not take into consideration or are unable to minimize the impact of fills on circuit performance. In this paper, we develop a fill insertion method that heuristically minimizes coupling capacitance increase due to fill. Our optimization methodology builds on fill insertion guidelines previously developed in, e.g., and . Experiments show that the proposed optimization methods can reduce fill impact on coupling capacitances by up to 85% for 30% pattern density and up to 65% for 60% pattern density cases.

Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific, 2003

In traditional floorplanners, area minimization is an important issue. Due to the recent advances in VLSI technology, the number of transistors in a design and their switching speeds are increasing rapidly. This results in the increasing importance of interconnect delay and routability of a circuit. We should consider interconnect planning and buffer planning as soon as possible. In this paper, we propose a method to reduce interconnect cost of a floorplan by searching alternative packings. We found that if a floorplan F contains some rectangular supermodules, we can rearrange the blocks in the supermodule to obtain a new floorplan with the same area as F but possibly with a smaller interconnect cost. Experimental results show that we can always reduce the interconnect cost of a floorplan without any penalty in area and runtime by using this method.

Society of Photo- …, 2009

To provide fabless designers the same advantage as Integrated Device Manufacturer (IDMs), a design-oriented litho model has been calibrated and an automated lithography (litho) hotspot detection and fixing flow has been implemented during final routing optimization. This paper shows how a design-oriented litho model was built and used to automate a litho hotspot fixing design flow. The model, calibrated and validated against post-OPC contour data at 99%, was embedded into a Litho Physical Analyzer (LPA) tech file. It allowed the litho contour of drawn layouts to be simulated at full chip level to detect litho hotspots and to provide fixing guidelines. Automated hotspots fixing was hence made possible by feeding the guidelines to the fixing tools in an industry based integrated flow. Post-fixing incremental checks were also performed to converge to a clean design.

IEEE Journal of Solid-State Circuits, 1981

A general and practical method for design rule optimization (i.e., IC cost minimization) is presented, and then demonstrated in detail for spec~lc examples. The optimum design rules are shown to be insensitive to chip area or defect density, but strongly dependent on tolerance sizes, number of masking levels, and to a parameter which will be defined as the "area overhead factor." Throughout the development, limitations and assumptions are thoroughly discussed, with the overall result that the method is shown to be immediately useful for arbitrary, but well characterised, fabrication processes and lithography equipment.